KR100219598B1 - Decoder - Google Patents

Abstract

Residual data over a limited bit size in each area is recorded in the margins of other blocks, and decoded compressed data recorded using end-of-block (EOB) signals to distinguish data unique to each block and residual data. A decoding apparatus is disclosed.

The decoding apparatus according to the present invention reads a bitstream stored in a segment memory and provides it to the variable length decoder to control the read address of the segment memory with reference to the decoding result of the variable length decoder to real-time the bitstream read from the tape. It has the effect of being able to decode.

Description

Decryption device

1 is a block diagram showing the configuration of a decoding apparatus according to the present invention.

FIG. 2 is a diagram illustrating an example of segment data stored in the segment memory shown in FIG. 1.

3 is a block diagram showing a detailed configuration of the index generator shown in FIG.

4 is a diagram showing the contents stored in the remaining data memory after processing the data shown in FIG. 2 by the apparatus shown in FIG.

FIG. 5 is a diagram showing an example of contents stored in the flag memory shown in FIG.

FIG. 6 is a view showing other contents of contents stored in the flag memory shown in FIG.

FIG. 7 is a block diagram showing the detailed configuration of the address generator shown in FIG.

The present invention relates to a decoding apparatus for decoding image compressed data obtained by region division, variable length coding, and storing the result in a block having a fixed size. More particularly, the present invention relates to decoding a residual data recorded in another block in real time. The present invention relates to a decoding apparatus that can be used.

The data of a digital video tape recorder (hereinafter referred to as DVTR) is recorded in a complicated format due to the limitations of tape, which is a sequential recording method.

In the DVCR encoding method, one frame picture is divided into a plurality of segments, and each segment is divided into five macro blocks. The macro block consists of six DCT blocks. Here, four DCT blocks are for the luminance signal Y, and the other two are for the color difference signals Cr and Cb.

In the DVCR recording method, a bitstream obtained as a result of encoding one frame screen is recorded in a plurality of segment recording areas, each segment recording area being composed of five macro block recording areas. It consists of six DCT block recording areas.

In the segment recording area, the macro block recording area, and the DCT block recording area, a bit stream obtained as a result of encoding a segment, a macro block, and a DCT block serving as coding units, respectively, is recorded.

In encoding a frame screen, the length of a bitstream obtained by encoding a segment, a macroblock, and a DCT block is not constant.

Therefore, two methods can be considered in writing the bit strip to the tape. One is a method of discarding a portion of the bit strip that exceeds the recording capacity of the corresponding recording area without recording, and the other is a method of recording a portion exceeding the recording content of the recording area in the margin of another recording area.

The former method is often used because the recording method is simple while the image quality of the reproduced screen is degraded.

This will be described in detail as follows. When a bitstream obtained by encoding a DCT block has more than the recording capacity of the DCT block recording area, the bitstream is first recorded in the DCT block recording area, and then the remaining bitstream is called MR (Macroblock Remainder) data. It is recorded in the margin of another DCT block recording area.

The bitstream which is left in the margin of another DCT block recording area belonging to the same macroblock recording area is recorded in the margin of another macro block recording area belonging to the same segment recording area, referred to as VR (Video Segment Remainder) data.

The remaining bit stream is discarded even if recorded in the margin of another macro block recording area belonging to the same segment recording area. This is because segments always have a fixed length in order to be processed in an independent form during encoding.

In decoding the recorded bitstream, the DCT block is first decoded, and then the macro block and the segment block are decoded in this order.

The conventional decoding apparatus first decodes a portion of the recording area except for the residual bitstream, and then decodes the residual bit strip. That is, the portion of the bitstream recorded in the recording area except for the remaining bitstream is first decoded, and then the MR data and the VR data are decoded with reference to the decoded result.

To this end, once the bitstream read in the segment recording area is written to the segment memory, it is determined whether the bitstream is an intact bitstream in units of DCT blocks, and the residual bitstream is supplemented in units of DCT blocks with reference to the bitstream. After decoding is completed in units of DCT blocks, it is determined whether the bit streams are intact in units of macro blocks, and the residual bit streams are supplemented in units of macro blocks with reference to the same. After decoding is completed in macro block units, it is determined whether the bit stream is an intact bit stream, and the residual bit stream is supplemented by segment by referring to the bit stream.

To this end, a conventional decoding apparatus includes a first segment memory for recording a bitstream read in a segment recording area of a tape, a relocation processing means for relocating a built-in stream stored in the first segment memory to a bitstream before recording, and a rearranged bitstream. A second segment memory for storing the data, a bit streamer sequentially reading the bit streams recorded in the second segment memory in a predetermined unit and providing the same to the variable length decoder, and variable length decoding the bit stream provided from the bit streamer. It consists of a long decoder.

Here, the relocation processing means requires a predetermined delay time to decode the bitstream before being recorded through the DCT data decoding step, the MR data decoding step, and the VR data decompression step, and thus the conventional decoding apparatus uses the bits read from the tape. There is a problem that the strip cannot be decoded in real time.

SUMMARY OF THE INVENTION An object of the present invention is to provide a decoding apparatus capable of decoding in real time a bit strip read from a tape, which has been created to solve the above problems.

The decoding apparatus according to the present invention to achieve the above object

Variable-length-encoded region-divided image data is recorded in a fixed bit size block, but the remaining data exceeding the limited bit size in each area is recorded in the margin of another block, and distinguishing the unique data from the residual data in each block. In the decoding apparatus for decoding the video compressed data recorded by using the EOB signal,

A memory for storing data to be decoded in units of blocks and sequentially reading the stored data;

A variable length decoder which connects the data read out from the memory, binds the data into predetermined bits, decodes them sequentially, and outputs run lengths, coefficients, and symbol lengths;

An index generator which accumulates the length of symbols generated in the variable length decoder and generates a head address of remaining data, a flag indicating whether data remains or not, and a flag indicating whether data ends, with reference to a start address provided to the memory; ;

A residual data index memory for storing a head address of the residual data generated by the index generator;

A flag memory for storing a flag indicating the presence or absence of residual data generated by the index generator and a flag indicating the presence or absence of data termination; And

And an address generator for generating a start address provided to the memory with reference to a flag indicating a head position of the residual data stored in the residual data index memory and the presence or absence of residual data stored in the flag memory, and a flag indicating the presence or absence of data termination. It is characterized by.

The decoding apparatus of the present invention reads the bitstream stored in the segment memory and provides the variable length decoder to decode the bitstream read from the tape in real time by controlling the read address of the segment memory with reference to the decoding result of the variable length decoder. To be able. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing the configuration of a decoding apparatus according to the present invention, showing an example applied to DVTR. The apparatus shown in FIG. 1 includes a segment memory 10, a bit streamer 12, a variable length decoder 14, an index generator 16, a residual data index memory 18, a flag memory 20, and an address. A generator 22 is provided.

The segment memory 10 is composed of two bank memories each capable of storing segment data. While the segment data stored in one memory is decoded, the segment data to be processed next, which is provided from an error correction unit (not shown), is stored in the other memory.

The bit streamer 12 inputs codes having irregular bit sizes provided from the memory 10, and connects them to output a code having a bit size of 16 bits. This is to fit the bit size of the barrel shifter (not shown) set inside the variable length decoder 14.

The variable length decoder 14 inputs a code having a bit size of 16 bits provided from the bit streamer 12, and variable length decodes the output length RUN, its coefficient AMP, and the length LEN of the symbol.

The index generator 16 accumulates the length LEN of the symbols output from the variable length decoder 14, and refers to the start address START ADDRESS provided by the address generator 22, and the head address of the remaining data for each DCT block. RESIDUAL ADDRESS, a flag indicating the presence or absence of residual data, and an end of byte FLAG (EOB FLAG) are generated. The RESIDUAL ADDRESS generated by the index generator 16 is stored in the remaining data index memory 18, and the RESIDUAL FLAG and EOB FLAG are stored in the flag memory 20.

Shown in FIG. 2 is the contents of the segment data stored in the memory bank of the segment memory 10. As shown in FIG. 2, segment data is composed of five macro blocks (MBO-MB4). In addition, each macro block is composed of six DCT blocks. The first to fourth DCT blocks of each row are configured for 7BYTE as luminance signals. The fifth to sixth DCT blocks are configured for 5BYTE as a color difference signal. Thus, each macro block consists of 38BYTE, and the segment consists of 190BYTE.

In each DCT block, the white portion represents data of the DCT block itself, the portion represents MR data, and the portion represents VR data. In addition, the portion denoted by E in each notation is a flag (EOB FLAG) indicating the end of data in each data, and the number indicates the original DCT block to which the data belongs.

For example, the upper left DCT block denoted by 0 has its own data and MR data. In particular, the MR data is data belonging to the DCT block denoted by 1 on the right side. In addition, the DCT block denoted by 0 does not have an EOB flag of VR data denoted by 1, which means that another DCT block has data connected thereto.

In fact, there are its residual data (in this case MR data) and its EOB flag, which are marked as 1 in the third DCT block from the left of the first row, labeled 2.

Therefore, the DCT block denoted by 1 must connect its own data with the MR data present in the DCT block denoted by 1 and the DCT block denoted by 2 to obtain complete data.

Likewise, the DCT block denoted by 3 is concatenated with its own data and the MR data of the DCT block denoted by 2 and the DCT block denoted by 3 to obtain complete data.

This shows an example in which data left in the DCT block belonging to each macro block is written in the margin of another DCT block in which no data is filled in the same macro block.

In contrast, since the DCT block denoted by 10 has an EOB flag at the end thereof, it can be seen that the complete DCT data is restored by itself.

On the other hand, the DCT block denoted 20 is MB2, but its residual data (in this case, VR data) is stored in the DCT block denoted 11, 12, 13 belonging to another macro block MB1.

The DCT block denoted by 22 is MB2, but its residual data (in this case, VR data) is stored in the DCT block belonging to another macro block MB4.

This shows an example in which the remaining data in each macro block is recorded in the margin of another macro block which is not full of data.

Segment data having the contents shown in FIG. 2 are first decoded from the area fixed in units of DCT blocks, and then decoded in the order of the area fixed in units of macro blocks and finally the area fixed in units of segments. In the present invention, this is referred to as fixed processing, macro residual processing, and VR (video segment residual processing), respectively.

3 is a block diagram showing a detailed configuration of the index generator shown in FIG. The apparatus shown in FIG. 3 includes a delay 30, a symbol length accumulator 32, a residual data calculator 34, a residual data accumulator 36, and a comparator 38.

The symbol length accumulator 32 accumulates the symbol length LEN through the delay t30.

The residual data calculator 34 inputs the address generated by the address generator 22, that is, the MB of the macro block currently being processed, the DB of the DCT block, and the WD, which is a pointer of the head data processed in the DCT block. The remaining number of bits (number of MR data and VR data) for each DCT block is calculated.

The residual data accumulator 36 accumulates the residual number of bits calculated by the residual data calculator 34.

The comparator 38 compares the acid accumulated in the symbol length accumulator 32 with the acid accumulated in the residual data accumulator 34 to generate an EOB. The comparator 38 stops the variable length decoder 14 within a range in which the value accumulated in the symbol length accumulator 32 does not exceed the value accumulated in the residual data accumulator 34.

At this time, the address decoded by the variable length decoder 14 is stored in the residual data index memory 18. If there is an EOB in the DCT block currently being processed, the EOB FLAG is set to 1, and if there is residual data, Set RESIDUAL FLAG to 1.

4 is a diagram showing contents stored in the residual data index memory after the fixing process. It can be seen that the residual data (MR data) of the first DCT block of the MBO starts at address 58H (hexadecimal).

5 shows the contents of the EOB FLAG table stored in the flag memory 20 after the fixing process. It can be seen that the first DCT block of the MBO has an EOB. In FIG. 5, EOB_MB is a flag indicating the presence or absence of an EOB in a macro block.

FIG. 6 shows the contents of the RESIDUAL FLAG table stored in the flag memory 20 after the fixing process. It can be seen that there is residual data (MR data) in the first macro block of the MBO. In FIG. 5, RES_MB is a flag indicating the presence or absence of residual data (VR data) at the macroblock level.

7 is a block diagram showing a detailed configuration of the address generator 22 shown in FIG. The apparatus shown in FIG. 7 has a start address register 70, an address register 72, a lookup table 74, a controller 76, and D-flip flops 78, 80.

In the case of the fixed processing, the value of the address register 72 is sequentially increased by the control of the controller 82.

MB, DB, and WD which are contents of the address register 72 are provided as addresses for reading the contents in the segment memory 10. In this case, since the addresses designated by MB, DB, and WD are different from the physical addresses of the segment memory 10, they are converted into the physical addresses of the segment memory 10 through the lookup table 80.

The address of the segment memory 10 output from the lookup table 74 is output via the D-flip flop 78.

The BIT stored in the address register 72 indicates the number of valid bits corresponding to the address currently output. The BIT stored in the address register 72 is provided to the bit streamer 12. The bit streamer 12 refers to the BIT output from the address register 72 and cuts the data output from the segment memory 10 into a bit size of 16 bits and provides the variable length decoder 14.

As described above, the decoding apparatus according to the present invention reads the bitstream stored in the segment memory and provides the variable length decoder to the bitstream read from the tape by controlling the read address of the segment memory with reference to the decoding result of the variable length decoder. Has the effect of being able to decode in real time.

In addition, unlike the conventional decoding apparatus, the decoding apparatus according to the present invention has an effect of saving processing time by not referring back to already processed data.

Moreover, the decoding apparatus according to the present invention has an advantage that the configuration thereof is simple and the cost of the product can be reduced.

Claims (3)

Variable-length coding of segmented image data is recorded in fixed bit sizes and blocks, but residual data exceeding the limited bit size in each area is recorded in the margins of other blocks, and distinct data and residual data unique to each block are distinguished. In the decoding apparatus for decoding the video compressed data recorded by using the EOB signal, A memory for storing data to be decoded in units of blocks and sequentially reading the stored data; A variable length decoder which connects the data read out from the memory, binds the data into predetermined bits, decodes them sequentially, and outputs run lengths, coefficients, and symbol lengths; Accumulate the length of the symbol generated in the variable length decoder, refer to the address provided to the memory and the EOB signal generated in the variable length decoder, the first address of the remaining data, a flag indicating the presence or absence of the remaining data, An index generator for generating a flag indicating presence or absence; A residual data index memory for storing a head address of the residual data generated by the index generator; A flag memory for storing a flag indicating the presence or absence of residual data generated by the index generator and a flag indicating the presence or absence of data termination; And Including an address generator for generating a start address that is provided with reference to the flag indicating the presence or absence of the flag, the data end indicating the presence or absence of remaining data stored in the head position and the flag memory of the remaining data stored in the remaining data index memory in the memory , And a read address of the memory based on a decoding result of the variable length decoder. The method of claim 1, wherein the index generator A symbol length accumulator for accumulating the lengths of symbols generated in the variable length decoder; A residual bit number calculator that calculates the number of remaining bits to be read from the memory with reference to a start address generated by the address generator; A residual bit number accumulator for estimating a result to be calculated in the residual bit number calculator; And Input the value accumulated in the residual number accumulator and the EOB signal to output the generation position of the EOB, and the variable length within the range that the value accumulated in the symbol length accumulator does not exceed the value accumulated in the residual number accumulator And a comparator for stopping the decoder. The method of claim 1, wherein the address generator A start address generator for generating a start address of data to be retrieved from the memory by a flag indicating the presence or absence of an EOB and remaining bits in each block, An address register for generating an address that sequentially increases from a start address generated in the start address generator to an end address of the block; And And a controller which controls to generate the next start address at the end address of the block.