KR0152030B1 - Decode error exposure preventing apparatus - Google Patents

Abstract

In the present invention, when an error occurs when the encoded image data is decoded again, the decoding error exposure prevention prevents the user from feeling that an error has occurred at the reconstruction or receiving side by replacing the data of the error part with the data of the previous frame. Relates to a device. The present invention checks whether an error occurs by counting the number of EOBs in the variable length decoding unit, and the error exposure prevention unit controls the transmission of the image data according to the error signal of the variable length decoding unit so that the image data of the portion where the error occurs All are converted to forced inter mode by outputting all data as zero data. The decoding-inverse transform unit replaces the data of the error occurrence part with the image data of the previous frame and outputs the data. Therefore, there is an effect of preventing the user from feeling that an error has occurred on the receiving side.

Description

Decoding and Error Exposure Prevention Device

1 is a block diagram showing an example of a conventional digital receiving apparatus.

2 is a block diagram of a digital receiver of the present invention.

3 is a screen state diagram showing an example of a processing unit of image data defined in the present invention.

4 is a block diagram showing the detailed configuration of the error exposure prevention unit.

5 is a configuration diagram showing a first embodiment of the memory unit.

6 is a configuration diagram showing a second embodiment of the memory unit.

* Explanation of symbols for main parts of the drawings

10: variable length decoding unit 20: decoding-inverse transform unit

30: error exposure prevention unit 31: memory unit

31A, 31B: RAM 31C, 31D: Switching unit

31E, 31F: FIFO 32: Timing Control

33: data control unit

The present invention relates to the processing of video data when a decoding error occurs. In particular, when an error occurs when the encoded video data is decoded again, the data on the portion where the error occurred is replaced with the data of the previous frame. The present invention relates to a decoding error exposure prevention apparatus that prevents an error from occurring.

Recently, in systems such as HD-TV, HD-VTR, digital VTR, digital camcorder, multimedia, video phone, video conference, etc., video signals and audio signals are encoded and transmitted as digital signals or stored in recording media. In this case, a method of decoding and playing back the data is mainly used. While the digital signal processing and transmission method has a merit that the transmission power is less than that of the analog method, the digital signal processing and transmission method may have a fatal effect on the system when an error occurs in the data due to the noise imposed on the channel. In order to solve such a disadvantage, conventionally, an error correcting code is added to data at a recording or transmitting apparatus, and a trellis coded modulation technique is introduced.

FIG. 1 is a block diagram showing an example of a conventional digital receiving apparatus for decoding the encoded image data and restoring the original data. As shown in the figure, a decoding-inverse transform unit 20 is connected to a training stage of the variable length decoder 1 for variable length decoding the encoded image data to expand the image data. Decoding corresponding to the encoding of the transmitting apparatus is performed on the input image data, and inverse DCT conversion of the decoded data is performed.

When the encoded image data transmitted from the transmitting apparatus is input to the receiving apparatus configured as described above, the variable length decoding unit 10 performs variable length encoding on the variable length through the reverse process of variable length encoding of the transmitting apparatus, The image data output from the decoder 10 is applied to the decoder-inverse transform unit 20. At this time, the image data DATA including the head data is input to the decoding-inverse transform unit 20 in the form of a bit stream, and a status signal including various information about the image data is included. And a frame number signal indicating the number of frames of data, a synchronization signal Vsync, and the like are input. The decoding-inverse transform unit 20 decodes the encoded image data through the inverse process of protection to enhance the error correction function in the transmitter using the input signals, and inversely decodes the decoded data by inverse DCT conversion. It will be restored to video data of.

However, according to this conventional method, even if an error occurs during decoding by the variable length decoding unit 10, error recovery is not performed. Therefore, since the information of the portion where the error is generated is transmitted to the decoding-inverse transform unit 20 as it is, and reconstructed, and the error portion is exposed as it is, there is a problem that the user of the reproduction or receiving side feels that an error has occurred.

The present invention is to solve the above-mentioned conventional problems, an object of the present invention is to check the error occurrence in the process of decoding the image data, if an error occurs in the forced inter mode and the error occurs The present invention provides a decoding error exposure prevention apparatus in which data is replaced with data of a previous frame so that a user cannot feel that an error has occurred.

Decoding error exposure prevention apparatus of the present invention for achieving the above object is variable-decoding the received image data and outputs the variable length code, and the decoding-inverse conversion unit at the output terminal of the variable-length decoding section for outputting an error signal by checking whether or not a decoding error occurs Connected. The error exposure prevention unit connected between the variable length coder and the decoding-inverse converter controls the transmission of the image data according to the error signal of the variable length decoder, thereby forcing all of the image data of the portion where the error occurs to be outputted as zero data. You are called in inter mode. The decoding-inverse transform unit connected to the output of the variable length decoding unit and the error exposure prevention unit performs decoding and inverse DCT corresponding to the encoding of the transmitting apparatus on the image data applied from the error exposure prevention unit, and the error occurrence data is the image of the previous frame. Reconstruct by replacing with data.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 2 to 6 as follows.

2 is a block diagram of the digital receiving apparatus of the present invention for decoding video data and restoring the original data. As shown, a decoded-inverse transform unit 20 is connected to an output terminal of the variable length decoder 10 for variable length decoding and outputting encoded image data and checking whether a decoding error occurs and outputting an error signal. The decoding and inverse transform unit 20 performs decoding corresponding to the encoding of the transmitting apparatus on the input image data, and inversely transforms the decoded data. Here, the configuration as described above is the same as the configuration of the same code blocks in the conventional receiver shown in FIG.

A feature of the present invention is an error exposure prevention unit 30 connected between an output terminal of the variable length decoding unit 10 and an input terminal of the decoding-inverse transform unit 20. The error exposure prevention unit 30 is a variable length decoding unit. According to the error signal (ERROR) applied from (10), the transmission of the image data is controlled to switch to forced inter mode by outputting all the data of the occurrence of the error as zero data.

The operation of the receiving device of the present invention configured as described above will be described with reference to FIGS. 3 to 6 as follows.

ZigZag-scanned image data in the encoder of the transmission device is not shown and classified into Run and Amplitude, applied to the variable length encoder, and then variable length coded to the receiver through the channel. Is sent. At this time, the image data of a predetermined size block unit is encoded with a code corresponding to an end of block (EOB) when there is no amplitude in the process of zigzag scanning and only the run continues and reaches the end of the block. That is, the image data encoded in every block unit is supposed to end with EOB. Therefore, if the data data does not end with EOB, the encoding of the data should be regarded as wrong. The image data transmitted from the transmitting apparatus is input to the variable length decoding unit 10 and is subjected to variable length decoding through a reverse process of variable length encoding of the transmitting apparatus.

In order to perform encoding and decoding of the image data, the screen is divided into blocks having a predetermined size. An example of the processing unit of the image data defined in the present invention is shown in FIG. 3 shows a block of image data of one frame, and a block indicated by hatching is composed of one macro block (MB) and m × n blocks. If one slice in a horizontal line is 11MB, 1MMB (Mass of Macro Block), which is an image data processing unit of the present invention, is 4 slices and is composed of 4 × 11 × (m × n) blocks. .

The variable length decoder 10 detects a start code from image data in MMB units by using a clock signal synchronized with a synchronization signal Vsync, decodes the number of bits of variable length coded image data in MMB units, The number of EOBs is counted using a built-in counter not shown. As described above, since the encoding of one block data is completed, one EOB must be included. Therefore, one slice containing 11 macroblocks (m × n) × 11 EOBs must be included. Therefore, the variable length decoding unit 10 counts the number of EOBs in 1 MMB units, and if the number of EOBs is not 4 × 11 × (m × n), determines that an error has occurred in 1MMB units, and generates an error signal (ERROR). Is generated and output to the error exposure prevention unit 30. Of course, if the number of EOB count is 4x11x (mxn), no error signal is generated. In addition, the variable length decoding unit 10 outputs the image data DATA in the form of a variable length decoded bit and a status signal STATE including various information about the image data to the error exposure prevention unit 30. .

In addition, the variable length decoder 10 outputs a frame number signal (Frame-number) indicating the number of frames of data and a synchronization signal (Vsync) to the decoding-inverse transformer (20). When decoding, video data is processed in units of 1 MMB, so if an error occurs when the number of EOBs is checked during decoding, the MMB data being processed is incorrectly decoded. It is broken. In the present invention, it is not possible to recover data on an error that has already occurred, but the error exposure prevention unit 30 has been added so that an error does not occur when received.

4 is a block diagram showing the detailed configuration of the error exposure prevention unit 30 in FIG. As shown, the error exposure prevention unit of the present invention stores a data amount of 1MMB from the variable length decoding unit 10 input through the data control unit 33 and outputs the stored data to the data control unit 33 (31) is provided. A timing controller 32 is connected to the memory unit 31 to supply various signals necessary for controlling a write / read operation of the memory unit 31 according to an error signal ERROR applied from the variable length decoder 10. And output to the memory unit 31 and the data control unit 33. The data controller 33 connected to the memory unit 31 via an input / output bus I / O is input from the variable length decoder 10 according to an error control signal ERROR output from the timing controller 32. The data and the data output to the decoding-inverse transform unit 20 are controlled.

When the image data is input in the MMB unit from the variable length decoding unit 10, the error exposure prevention unit 30 configured as described above receives 1 MMB of data from the data control unit 33 through the input / output bus. 31) and read it out again, and send it out to the decoding-inverse transform unit 20 at the rear stage. At this time, the timing controller 32 generates various signals necessary for controlling the write / read operation of the memory 31, for example, an address signal ADDR, a read / write control signal R / W, and the like. ) In addition, when an error signal ERROR occurs in the variable length decoding unit 10, the error signal is transmitted to the timing controller 32, and the timing controller 32 checks an error occurrence time in the state of the error signal ERROR. The error control signal ERR-CON is output to the data control unit 33.

When the data control unit 33 receives the error control signal ERR-CON, the data control unit 33 processes all of the 1MMB data currently being processed as zero data and outputs them to the decoding-inverse transform unit 20. In more detail, 1MMB data includes image data and head data. The head data is transmitted in the 0 state in the inter-mode and in the 1 state in the intra-mode. do. Therefore, if all 1MMB data is made into zero data, the transmission mode is forcibly switched to the inter mode indicating that there is almost no movement.

The decoding-inverse transform unit 20 uses a status signal STATE applied from the data controller 33, a frame number signal, a sync signal Vsync, etc. applied from the variable length decoder 10. The video data encoded by the transmitting apparatus is decoded through an inverse process of encoding, and the decoded data is changed by inverse DCT to restore the image data before encoding. At this time, if the 1MMB image data is input as the zero data from the data control unit 33, the decoding-inverse transform unit 20 does not use the data in which the current error occurs when reconstructing the image data. Read the video data once again to replace the part where the error occurred.

In FIG. 4, the memory unit 31 may be configured using RAM as shown in FIG. 5, or may be configured using FIFO (First In First Out) as shown in FIG. 6.

FIG. 5 is a configuration diagram showing the first embodiment of the memory unit 31, in which two image data of at least 1 MMB can be alternately recorded / read in accordance with the address signal ADDR applied from the timing controller 32. As shown in FIG. RAM 31A and 31B are provided. A first switching unit 31C is connected to an input terminal of the RAM 31A and 31B, and the first switching unit 31C is in accordance with the enable signal W-EN, which is a write applied from the timing controller 32. The connection terminals a and b are alternately switched to transfer image data transmitted from the data control unit 33 to the RAM 31A and 31B. The second switching portion 31D is connected to the axial end of the rams 31A and 31B. The second switching unit 31D switches the connection terminal b when the first switching unit 31C is switching the connection terminal a according to the enable signal R-EN applied from the timing controller 32. When the first switching unit 31C is switching the connection terminal b, the connection terminal a is switched so that the image data read out from the RAMs 31A and 31B are alternately output to the data controller 33.

The memory unit 31 configured as described above is transferred from the data control unit 33 when the first switching unit 31C first switches a by the enable signal W-EN, which is a crossover from the timing control unit 32. The image data is recorded at a predetermined position of the first RAM 31A through the a terminal of the first switching unit 31C by the address signal ADDR supplied from the timing controller 32. At the same time, the second switching unit 31D switches the b terminal by the enable signal R-EN which is a read from the timing controller 32, and the image data stored in the second RAM 31B is controlled by the timing controller 32. It is read out by the address signal ADDR from and output to the data control unit 33 via the b terminal of the second switching unit 31D.

Next, the first switching unit 31C switches the b terminal by the enable signal W-EN, which is a recording from the timing controller 32, and the image data transmitted from the data controller 33 is the timing controller 32. The address signal ADDR is written to the RAM 31B via the b terminal of the first switching unit 31C. At the same time, the second switching unit 31D switches terminal a by the enable signal R-EN which is a read from the timing controller 32, and the first RAM by the address signal ADDR of the timing controller 32. The video data read out at 31A is outputted to the data control unit 33 via the a terminal of the second switching unit 31D. Here, in consideration of the number of services actually input and output, the RAMs 31A and 31B must be configured using two RAMs, respectively, and thus four RAMs having an 8-bit data bus are actually required.

FIG. 6 is a block diagram showing the second embodiment of the memory unit 31, and operates in accordance with the enable signal W-EN and the read enable signal R-EN applied from the timing controller 32. As shown in FIG. It consists of two FIFOs 31E and 31F which alternately store video data of 1 MMB or more transmitted from the data control unit 33 and output the data data to the data control unit 33.

The memory unit 310 configured as described above has two FIFOs 31E in accordance with the enable signal (W-EN) and the read enable signal (R-EN), which are applied from the timing controller 32, as in the first embodiment. ) 31F alternately performs recording / reading operation, i.e., while image data transmitted from the data control unit 33 is recorded in the FIFO 31E, image data read out from another FIFO 31F is stored in the data. The video data transmitted from the data controller 33 is recorded in another FIFO 31F while the video data output to the control unit 33 and the video data read out from the FIFO 31E are output to the data control unit 33.

As described above, the present invention checks the occurrence of an error in the process of decoding the image data, and when an error occurs, switches to the forced inter mode and replaces the data of the portion where the error has occurred with the data of the previous frame and outputs the received side. Has the effect of preventing the user from feeling that an error has occurred.

Claims (6)

A digital receiving apparatus for decoding image data encoded in units of blocks of a predetermined size by a transmitting apparatus, wherein the variable length decoding unit outputs an error signal by variable length decoding the received image data and checks whether a decoding error occurs. Wow; An error exposure prevention unit for controlling the transmission of the image data according to the error signal of the variable length decoding unit and converting the image data of the portion where the error occurs to zero data into a forced inter mode; And a decoding-inverse transform unit which performs decoding corresponding to the encoding of the transmitting apparatus and inverse DCT on the image data applied from the error exposure prevention unit, and replaces the error occurrence data with the image data of the previous frame. Decryption error exposure prevention device. The variable length decoder of claim 1, wherein the variable length decoder checks whether an error has occurred and outputs an error signal. After counting the number of EOBs included in the end of the block, if the count value is the same as the number of blocks in the block unit of the predetermined size, it is determined that no error is issued and no error signal is generated, and the count value is the predetermined value. And determining that an error has occurred if it is not the same as the number of blocks in a block unit of size, and generating the error signal. 2. The apparatus of claim 1, wherein the error exposure prevention unit comprises: a memory unit for storing 1 MMB of data from the variable length decoding unit input through the data control unit and outputting the stored data to the data control unit; A timing controller which generates various signals necessary for controlling the write / read operation of the memory unit according to the error signal applied from the variable length decoder, and outputs them to the memory unit and the data controller; Decoding error exposure prevention device characterized in that it comprises a data control unit for interfacing the data with the memory unit in accordance with the error control signal output from the timing control unit to control the data input from the variable-length decoding unit and the data output to the decoding-inverse transform unit . The memory device of claim 3, wherein the memory unit comprises: two RAMs configured to alternately write / read image data of at least 1 MMB according to an address signal applied from a timing controller; First switching means for alternately transferring image data transmitted from the data controller to the RAM in accordance with an enable signal applied from a timing controller at an input of the RAMs; While the image data is being recorded in the first RAM according to the read enable signal applied from the timing controller, an output terminal is selected in the second RAM to output the image data recorded in the second RAM to the data controller. Decoding error exposure prevention device characterized in that it comprises a second switching means for selecting the output terminal of the first RAM while the image data is recorded in the second RAM to output the image data recorded in the first RAM to the data control unit. . 4. The memory unit of claim 3, wherein the memory unit operates in accordance with a write enable signal and a read enable signal applied from a timing controller, and stores two or more image data transmitted from the data controller in ancient times and outputs the data to the data controller. Decryption error exposure prevention device characterized in that the configuration. The inter mode of claim 3, wherein the data controller processes image data and head data included in 1MMB data currently being processed as zero data when an error control signal is input from a timing controller to indicate that the image is an arcless image with almost no movement. Decryption error exposure prevention device, characterized in that forcibly switched to.