KR0139163B1 - Sync adapting apparatus applicating in a vlc process - Google Patents

Abstract

The present invention detects a start code (information code in which data is located at the head to indicate that data starts) because the following data are decoded incorrectly as an unexpected error occurs during the decoding of the image data. The present invention relates to a synchronizing device capable of smoothly decoding original video data by reading timely data.

Description

Synchronization device applied to variable length decoding (VLD) process

1 is a block diagram of a general video data encoding apparatus,

2 is a block diagram of a general video data decoding apparatus;

3 is an exemplary diagram illustrating a macroblock forming one frame of image data;

4 is a variable length format including bit stuffing,

5 is a block diagram showing the internal data processing relationship of the synchronization device according to the present invention;

6 is an internal configuration diagram of an interface unit according to the present invention.

* Description of the symbols for the main parts of the drawings *

10: FIFO memory 20: interface unit

21: transmission unit 22: code detection unit

23: latch portion 24: status determination

25: counter unit 26: transmission control unit

30: variable length decoding unit 40: timing control unit

The present invention relates to a synchronization device that can smoothly decode original video data by timely reading data waiting for input as a means of minimizing wrong duplication by an unexpected error.

In general, video signal coding methods can be roughly classified into signal coding (souce coding) and entropy coding. The entropy coding method compresses the data compressed by the signal source coding method again according to the statistical occurrence probability, and has a high transmission efficiency. As such a representative example, variable length coding (VLC) is widely used. It is used. In the variable length coding scheme, a short length code is assigned to a high frequency symbol, while a long length code is assigned to a low frequency symbol to further increase the transmission efficiency by further compressing the total amount of data.

For example, in high-definition television (HDTV) using digital signal processing, a combination of signal source coding and variable length coding (VLC) using DCT (Discret Cosine Transform) or DPCM (Differential Pulse Code Modula-tion) is used. In addition, due to the enormous amount of data processing, image data corresponding to one screen is divided into several windows and processed. As described above, the processing of each window is shown in FIGS. 1 and 2. FIG. 1 is an image data encoding system, and FIG. 2 is an image data decoding system. When divided into windows, processing speed of a window can be reduced.

The video data to be processed in FIG. 1 is divided into four channel data by the channel splitter 1 and input to the first to fourth signal source encoders 2A-2D, respectively. Firstly compressed image data in the first to fourth signal source encoders 3A-3D are respectively applied to the first to fourth variable length encoders 3A-3D and compressed again. That is, the image data is reconstructed into a symbol of [run, level] form, and then a variable length code corresponding to the symbol is selected, and various headers and other data are added to the encoding. The data of each window coded by the first to fourth variable length coding units 3A-3D are applied to the multiplexing unit 4, and the multiplexing unit 4 mixes the input data in order to form one bit string. After creating, this bit string is divided into a certain size (usually 24 bits) and written to FIFO memory.

On the other hand, in the decoding system of FIG. 2, the bit strings encoded by the above-described encoding system are read back from the FIFO memory and restored to the image data before encoding. In this case, the bit strings are divided and processed into four windows. . That is, the input bit stream is divided into four channel data by the demultiplexer 5, and the first to fourth variable length decoders 6A-6D variably decode this data to extend the image data. . In this case, since the amount of data decoded at each instant in the first to fourth variable length decoding units 6A-6D is variable, a function is required to read data from the FIFO memory whenever necessary. This is the feedback loop function, and the reason for this function is that the boundary between codes is not known, so the length or code of the current codes is not known until the previous codes are decoded.

The data output from the first to fourth variable length decoding sections 6A-6D are applied to the first to fourth signal source decoding sections 7A-7D, respectively. The first to fourth signal source decoding units 7A to 7D perform decoding corresponding to the signal source encoding of FIG. 1 on the input image data, and here, when run length decoding is performed, The functions of the first to fourth variable length decoding sections 6A-6D should stop until the number of "0" is generated. Data of each window decoded by the first to fourth signal source decoders 7A-7D are applied to the multiplexer 8, and the multiplexer 8 mixes the input image data and outputs one bit string. Done.

However, when image data corresponding to one screen is divided into several windows and processed, the bits generated in each window change in time, and thus, it is necessary to indicate the boundary between each window upon restoration. In the variable length coded bit string, since codes of variable length are continuously connected, if an error occurs during transmission, the variable length decoding operation continuously decodes wrong codes after the error occurrence part. As a result, an error occurs in the decoded data, and in serious cases, there is a problem such as an error in the read operation of the FIFO memory due to the feedback loop and the synchronization after that.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a synchronization device for correcting synchronization so that a decoding process is normally performed by detecting a start code indicating a boundary of codes.

An object of the present invention as described above is provided with a FIFO memory and a variable long decoding unit for recovering image data before encoding, wherein the variable long decoding unit is connected between the FIFO memory and the variable long decoding unit. The interface unit outputs the image data whenever the data request signal is applied from the unit and outputs the data read signal to the FIFO memory, and the timing of outputting the initial signal and the start signal to the interface unit such that the data read signal is output in a timely manner. Achieved by the control unit.

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a block diagram of image data of one frame, which is divided into four windows. Each window is composed of four MMB (Mass of Macro Block) units. Each window is processed by MMB unit and the processing result is multiplexed by MMB unit. In FIG. 3, the first window has 1, 5, 9... Arranged in the left vertical column. It is composed of MMB units of (number assigned), and the second to fourth windows are similarly composed of MMB units of the corresponding column.

On the other hand, since the amount of data generation is not constant and variable for each window, bit stuffing is performed at the end of the MMB to be a multiple of the number of bits recorded in each MMB unit (for example, a multiple of 24) when recorded in the FIFO memory. . In addition, when the amount of data generated is small and bit stuffing in which constant data is added to prevent underflow is required, it is also necessary. In the embodiment, a certain number of zero bits are inserted.

A variable length code format including such bit stuffing is shown in FIG. In FIG. 4, the unit of recording / reading in the FIFO memory is 24 bits, and 1 to 23 bit sputtering data is added to the end of the MMB data as necessary. A 32-bit Frame Start Code (hereinafter referred to as FSC) is followed by a 4-bit frame number (FN) followed by a 20-bit buffer status information (BSI). The 24-bit MMB Start Code (hereinafter referred to as MSC) is followed by the 8-bit MMB number (MN), quantization level (qlevel), macroblock information (MB info), and MB data.

The macroblock degree (MB info) includes field / frame determination information (field / frame), quantization level (mquant) of the macroblock, inter / intra determination information (inter / intra), horizontal motion vector (x MV), and vertical motion. Vector (y MB) and the like. Each block also includes a DCT coefficient dct_coeff and a sign EOB indicating the end of the block. Here, the FSC, MSC, and MMB numbers (MN) use fixed codes, but the other codes vary depending on the case, and thus lack bit stuffing data (“0”) when the MMB data is not a multiple of 24 bits. Add by the number of bits.

5 is a block diagram showing the internal data processing relationship of the synchronization device according to the present invention. As shown in the drawing, the present invention includes a FIFO memory 10 which stores encoded video data in the input order and outputs the first input data whenever the data read signal READ of the interface unit 20 is received. do. The interface unit 20 connected to the output terminal of the FIFO memory 10 removes the bit sputtered data filled at the end of the MMB according to the initial signal INIT and the frame start signal FSTRT of the timing controller 40, and changes the variable. The video data is output whenever the data request signal RQST is applied from the long decoding decoder 30. The variable length decoding unit 30 connected to the output terminal of the interface unit 20 variably decodes the encoded image data and the additional information according to the control signal of the timing controller 40. In this case, the timing controller 40 is connected to the interface unit 20 and the variable length decoding unit 30 to generate control signals necessary for bit stuffing removal and decoding.

In the synchronization matching device configured as described above, the decoding period is divided into two types. The MSC / FSC decoding period is a period for finding the MSC and the FSC, and the MMB decoding period is divided into a period for decoding various other header data and video data in the MMB. . These two periods are controlled by the frame start signal FSTRT and the initial signal INIT applied from the timing controller 40. The MMB decoding period variable length decoding unit 30 sends a data request signal (RQST) to the interface unit 20 according to a predetermined algorithm, and performs normal image data decoding. In other words, run / level-encoded video data and additional information data are variably decoded, and a data request signal RQST is sent only when data necessary for decoding is needed. In addition, when all the data is not used for decoding, the variable length decoding unit 30 stops itself when there is a run including continuous zeros, for example, without sending out a data request signal (RQST). do.

6 is an internal configuration diagram of an interface unit according to the present invention. As shown, the interface unit 20 of the present invention transmits the transmission unit 21 for transmitting the data output from the FIFO memory 10 to the variable length decoding unit 30 in accordance with the control signal of the transmission control unit 26 Equipped. The code detector 22 is connected to an output terminal of the FIFO memory 10 and detects a code (FSC or MSC) included in the output data and outputs a detection signal to the latch unit 23 depending on whether the code is detected. The latch unit 23 is composed of an FN latch 23a for receiving one end of the output data of the transmission unit 22 and latching the frame number FN, and an MN latch 23b for latching the MMB number MN. The state determination unit 24 connected to the latch unit 23 receives the frame number FN and the MMB number MN, respectively, and compares the measured values applied from the counter unit 25 to determine whether they are in a normal state. do. The transmission control unit 26 outputs the data read signal READ to the FIFO memory 10 and transmits the data read signal READ to the transmission unit 21 when the data request signal RQST is received in accordance with the determination result of the status determination unit 24. Outputs the transmission signal SEND or the hold signal HOLD. The counter unit 25 includes a frame counter 25a and an MMB counter 25b, and the frame counter 25a receives one end of the frame number FN output from the FN latch 23a and is also a timing controller. The frame start signal FSTRT is periodically input from 40. The MMB counter 25b receives an initial signal INIT from the timing controller 40.

An operation of the interface unit having the above configuration will be described in detail with reference to FIG.

First, in the normal decoding process, the transmission control unit 26 receives the data request signal RQST from the variable length decoding unit 30 and transmits the data to the variable length decoding unit 30 to transmit the data to the transmission unit 21. At the same time as (SEND) is output, the data read signal READ is output to the FIFO memory 10, data is read, and the data is filled in the transfer unit 22. The code detection unit 22 outputs an FSC detection signal or an MSC detection signal when an FSC or MSC is detected while reading data from the FIFO memory 10. At this time, the transmission unit 22 holds the data until the next decoding period. On the other hand, if an error occurs while decoding data, the transmission control unit 26 receives an error signal, recognizes the error occurrence, outputs a data read signal READ until the FSC or MSC of the next frame is detected, and then outputs the FIFO memory. Read data unconditionally at (10). The frame counter 25a receives a load signal from the state determiner 24 and starts a counting operation. That is, the frame counter 25a receives the frame number latched when the power is “on” and is counted by the frame start signal FSTRT output by the timing controller 40 every frame. The status judging unit 24 compares the detected frame number with the counted frame number over several frames and determines a normal state if it is correct. Thereafter, the status determination unit 24 replaces the count value by the frame start signal FSTRT periodically output from the timing controller 40 to output the frame number, so that even when an unstable data is latched due to an error, the count value is referred to. Synchronization takes place. The MMB counter 25b is also set as the reference count by counting by the initial signal INIT output from the timing controller 40 every MMB. That is, the MMB value is compared at every MMB starting point to determine whether the data is correct at the present time. The MMB counter 25b outputs an adjustment signal to the state determiner 24 so that the MMB counter 25 is correctly read from the FIFO memory 10 from the subsequent MMB time regardless of the decoding process performed if the data is later than the original time. If the data is faster than the reference, the MMB counter 25b outputs an adjustment signal to the status determiner 24 to stop the data read signal READ that the transmission control section 26 outputs to the FIFO memory 10, instead. The hold signal HOLD is output to the transmitter 22.

According to the present invention as described above, by checking whether the data to be decoded is processed at the correct time point every time the FSC or MSC included in the data is detected, synchronization can be prevented from being out of sync due to an unexpected error. If the data is damaged, it can be synchronized with the reference counter value, thereby improving the reliability of data processing.

Claims (5)

In the variable length decoding apparatus for reconstructing the image data before being encoded with a FIFO memory for storing the predetermined data and a variable length decoding unit for receiving and decoding the output data, Whenever the data request signal is input from the variable length decoding unit, the data read signal is output to the FIFO memory and the stored data are output. The storage data is determined according to the initial signal and the start signal output from the timing controller. An interface unit; And a timing controller for periodically outputting an initial signal and a start signal to an interface unit according to a predetermined time, and outputting control signals required by the variable length decoding unit. 2. The apparatus of claim 1, wherein the interface unit receives a data request signal and outputs a data read signal to a FIFO memory, and receives data from a previous FIFO memory and stores / outputs stored data according to control of the transmission controller. A code detector for detecting a start code by receiving an output data of a FIFO memory, a latch unit for latching necessary data among data output from the transmitter according to a detection signal of the code detector, and a timing controller. A counter unit for receiving a counting start signal or an initial signal and counting the state; and a state determining unit for receiving an output signal from the latch unit and the counter unit to determine a normal state. Device. The synchronization of claim 2, wherein the code detector detects an FSC or an MSC from data read from the FIFO memory and outputs a corresponding FSC detection signal or an MSC detection signal. Device. The LN latch of claim 2, wherein the latch unit receives an FSC detection signal from a code detector and latches a frame number among the output data of the transmitter; and an MN latch latches an MMB number among the output data of the transmitter by receiving an MSC detection signal. Synchronization device applied to the variable length decoding process, characterized in that consisting of. The frame counter of claim 2, wherein the counter unit receives one end of the frame number FN output from the FN latch and periodically receives the frame start signal FSTRT from the timing controller, and an initial signal from the timing controller. A synchronization matching device applied to a variable long decoding process, characterized in that the MMB counter receives an INIT).