KR0144975B1 - Sink code interleave method and apparatus thereof - Google Patents

Abstract

The sync code interleaving apparatus and method use an interleaving method to bundle a plurality of sync codes respectively corresponding to data of a predetermined unit into one sync block, record them on a recording medium, and reduce the error occurrence rate by lengthening the sync size occupied on the tape. To facilitate retrieval of the sync code during playback. To this end, an encoder is provided which comprises an encoder for data compression and two-dimensional Reed Solomon encoding applied for recording, and a decoder for two-dimensional Reed Solomon decoding on data picked up from the recording medium and decompressing the compressed data. When the image data of the error correcting coding unit output from the 2D Reed Solomon encoder is applied in the column direction, the interleaver for rearranging the n-byte row direction data in the error correcting coding unit by the interleaving method in k units and outputting it to the modulator Including; The decoder is configured to include an inverse interleaver for recovering a signal output from the demodulator in the form of an original error correcting coding unit in a state rearranged by an interleaver.

Description

Synccode Interleaved Device and Method

1 is a block diagram of an encoder of a digital signal processing system according to the present invention.

FIG. 2 shows an error correction coder (ECC) block diagram output from the two-dimensional Reed Solomon encoder shown in FIG.

3 is a detailed embodiment of the interleaver shown in FIG.

4 shows an input sequence of signals applied to the interleaver shown in FIG.

FIG. 5 shows a sequence of signals output from the interleaver shown in FIG.

6 is a data arrangement diagram on the tape when the sync code interleave according to the present invention is not performed.

7 is a data arrangement diagram on a tape when the sync cord interleaver according to the present invention is used.

8 is a block diagram of a decoder of a digital signal processing system according to the present invention.

* Explanation of symbols for main parts of the drawings

10: preprocessor 20: source encoder

30: sink and recognition signal generator 40: inserter

50: 2-D Reed Solomon Decoder 120: Extractor

130: source decoder 140: reverse processing unit

61: Demultiplex 63, 64: 1st, 2nd memory

62, 65, 66: multiplexer 67: control circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sync code interleave apparatus and method in a digital signal processing system. In particular, the present invention relates to a signal output in ECC (Error Correction Coder) block unit through two-dimensional Reed-Solomon coding for digital data to be applied. The present invention relates to a sync code interleaving apparatus and method for recording and reproducing a plurality of sync codes into one sync block by applying an interleaving scheme.

When data is transmitted to tape, which is a kind of recording medium, a sync code is sent to synchronize data at predetermined data intervals. This sync code is generally about 3 bikes, and is likely to be deteriorated by errors on the tape due to external or internal factors. The same is true for pure data. However, if the pure data is corrupted, the effect is partially shown, but if the sync code is corrupted, normal reproduction cannot be performed as is well known. There are many ways to prevent the synccodo from deteriorating, but the easiest way is to increase the size of the sync cord on the tape. The larger the area occupied by the sync code, the less damage from errors that occur and the easier it is to detect the sync code during playback. However, since tape capacity is limited, it is difficult to allocate large area of sync code because side information such as sync code should be sent as much as possible and pure data should be sent.

Accordingly, an object of the present invention is to reduce the error occurrence rate by enclosing a plurality of sync codes corresponding to data of a predetermined unit into one sync block through an interleaving method, recording them on a recording medium, and lengthening the sync size occupied on the tape. The present invention provides a sync code interleaving method and method for facilitating retrieval of sync code during playback.

In order to achieve the above object, a sync code interleaving apparatus according to the present invention corresponds to a source encoder for compressing applied image data according to a predetermined bit rate, and the image data output from the source decoder output from the source encoder. A 2D Reed Solomon encoder for encoding an error correction code (ECC) block unit code by adding a sync signal and a recognition signal (ID), and recording the signal output from the 2D Reed Solomon encoder on a recording medium A sync code interleaver of a digital signal processing system, comprising: a modulator for digitally modulating a predetermined digital modulation, wherein the m × n byte signal including an a byte sync code output from the two-dimensional Reed Solomon encoder is generated. First selection means for selectively outputting the first control signal by a second control signal; A first memory for storing and reading a signal output from the first selecting means by a fish signal, a second memory for storing and reading a signal output from the first selecting means by a third control signal, and a fourth control Second selection means for selectively outputting a signal read out from the first memory and the second memory by a signal to the modulator; and a read mode and a read mode in a storage mode for the first and second memories according to a fifth control signal. And a third control means for selectively thrusting different address data to be applied, and a first control signal for outputting data of the two-dimensional Reed Solomon encoder in m × k byte units, and the m × k byte units. Second and third control signals for alternately storing and reading data output from the first and second memories, and sequentially outputting data read from the first and second memories. And a control circuit for generating a fourth control signal for designating a fifth control signal for addressing the sync data in units of a × k bytes in a mode of reading data from the first and second memories. It is characterized by.

In order to achieve the above object, the sync code interleave method according to the present invention compresses the applied image data according to a predetermined bit rate, encodes two-dimensional Reed-Solomon encoding, and m × n bytes by the two-dimensional Reed-Solomon encoding. A storage process for storing m-byte data including a-byte sync code in a memory in a column direction when the image data of an error correction coding unit is configured, the n-byte row direction of the image data stored in the memory Read data to sequentially read data from column 1 to column m in a row direction of a predetermined k (2≤k <n) byte unit with respect to the data, and expand and output the sync data with a sync code of k × a bytes. And a modulation / recording process for recording the data read in the reading process on the recording medium by performing a predetermined modulation. It extends the length of the sync code than is characterized to describe the recording.

Next, with reference to the accompanying drawings will be described in detail with respect to the present invention.

FIG. 1 is a block diagram of an encoder of a digital signal processing system according to the present invention. When image data is applied, FIG. 1 converts it into a digital signal, separates it into a luminance signal and a color signal, and transmits the data based on a CCIR 601 format. The source is controlled by a preprocessor 10 for processing, a source encoder 20 for compressing a signal output from the preprocessor 10 to a predetermined bit rate, and a control signal output from the source encoder 20. The sink and recognition signal generator 30 for generating the sync signal SYNC and the recognition signal ID corresponding to the signal compressed and output from the encoder 20 and the sync and recognition signal generator 30 are output. An inserter 40 for inserting the sync signal and the recognition signal SYNC + ID into the pure data signal output from the source coder 20, and a signal output from the inserter 40 with the 2D Reed Solomon Co. After parity is added by RS CODING, the 2D Reed Solomon encoder 50 and the 2D Reed Solomon encoder 50 for outputting the data in ECC block units are interleaved according to a predetermined rule. Interleaver (60) for outputting the rearrangement, and a modulator (70) for modulating and outputting the signal output from the interleaver (60) in a predetermined manner so that the signal output from the interleaver (60) can be recorded. . In this case, the modulation performed by the modulator 70 may be, for example, 8-14 modulation (EFM).

As a specific embodiment of the interleaver 60 shown in FIG. 2, the demultiplexer 61 and the demultiplexer 61 for selectively outputting the signal output from the two-dimensional Reed Solomon encoder 50 are applied. A first memory 63 connected with the write data input terminal W to one output terminal A of &lt; RTI ID = 0.0 &gt;) &lt; / RTI &gt; and a second connected with the write data input terminal W to the other output terminal B of the demultiplexer 61. The signals output through the memory 64 and the read data output terminal R of the first memory 63 and the read data output terminal R of the second memory 64 are connected to the respective input terminals A and B. FIG. A control circuit for outputting a selection control signal to the multiplexer 62 for selectively outputting the signal, and outputting a selection control signal to the multiplexer 62 and the demultiplexer 61 and controlling the write mode and the read mode of the first and second memories 63 and 64 ( 67 and the address data at the time of writing and reading by the selection control signal output from the control circuit 67 (ADD1, A). The multiplexer 65 for selectively outputting the DD2 to the first memory 63 and the address data ADD1 and ADD2 at the time of writing and reading by the selection control signal output from the control circuit 67 are stored in the second memory. And a multiplexer 66 for selectively outputting to 64.

4 illustrates a sequence of reading data from the 2D Reed Solomon encoder 50 by the interleaver 60.

FIG. 5 shows an order in which the interleaver 60 interleaves and outputs n-byte row direction data in k units.

6 shows a layout of data on a tape when the present invention is not applied.

7 shows a layout of data on a tape when the present invention is applied.

8 is a block diagram of a decoder of a digital signal processing system according to the present invention. The demodulator 90 and the signal output from the demodulator 90 for demodulating the data picked up to the recording medium 80 are input signals. A reverse interleaver 100 for returning the signal rearranged in the interleaver 60 to the original arrangement state, and a two-dimensional reed solomon decoder 110 for decoding the signal output from the reverse interleaver 100 for two-dimensional Reed Solomon. And an extractor 120 for extracting the sync and recognition signals from the signal output from the decoder 110, and a source decoder for restoring the compressed data using the signal output from the extractor 120 as an input signal. 130 and a reverse preprocessing unit 140 for processing the signal output from the source decoder 130 in reverse to that processed by the preprocessor 10.

The operation of the present invention will now be described with reference to the accompanying drawings.

First, the encoder will be described, and the preprocessing unit 10 and the source encoder 20, the sync and recognition signal generator 30, the two-dimensional Reed Solomon encoder 50, the modulator 70, and the like have been previously described. Since it is the same as the method will be described schematically.

When the image data is applied, the preprocessing unit 10 performs low pass filtering to remove the high frequency component, separates the luminance signal from the color signal, and then performs an A / D conversion process on the 4: 2: 2 luminance signal based on the 'CCIR601' format. And the color signal form a macro block, and the window size is output to the required size. In this case, the windowing is to reduce the size of the video signal applied to one frame unit to 910 * 525 to 720 * 480.

The windowed data is applied to the source encoder 20 and compressed according to a predetermined bit rate. At this time, the compression method is based on JPEG (Joint Photographic Experts Group) or MPEG. In addition, the source encoder 20 outputs a control signal to the sink and recognition signal generator 30 to output a sync signal and a recognition signal corresponding to the pure data output in a predetermined block unit. Accordingly, the sync and recognition signal generators 30 and 30 output corresponding sync signals and recognition signals.

The inserter 40 inserts the sync signal and the recognition signal corresponding to the pure data signal output from the source encoder 20 and outputs the sync signal to the 2D Reed Solomon encoder 50. The two-dimensional Reed Solomon encoder 50 outputs one integer number of frames or one group of pitctures in the form of an ECC block as shown in FIG. One ECC block shown in FIG. 2 has a sync code a byte and an ID code b mite appended to the compressed pure data C bytes and “e for column (ne) bytes in compressed data. The external code of bytes is added, and the internal code d bytes are added to ID + data in the column direction (ROW).

This ECC block is applied to the interleaver 60 and stored in the column direction as shown in FIG. 4, and k sync codes in the row direction are bundled into one unit for n-byte data divided as shown in FIG. Output it.

The content processed by the interleaver 60 will be described in more detail with reference to FIG. 3 as follows.

First, as shown in FIGS. 4 and 5, the input order (or storage order) and the output order (reading order) for signals output from the 2D Reed Solomon encoder 50 are different from each other. The address data for is different. Therefore, the control circuit 67 separately outputs address data for reading and storing.

When ECC block data as shown in FIG. 2 is applied for the first time, the control circuit 67 applies a control circuit to the selection terminal S1 of the demultiplexer 61 to output a signal from the 2D Reed Solomon encoder 50. Is transmitted to the write signal input terminal (W) of the first memory (63), and at the same time, the control circuit 67 controls the mulkyplexer so that ADD1, which is address data corresponding to the write mode, is applied to the first memory (63). 66 is controlled to be in a disabled state and therefore is not transmitted to the second memory even if the address data ADD1 is applied. Accordingly, the first memory 63 stores data in the order shown in FIG.

In order to read the stored data in this order as shown in FIG. 5, the control circuit 67 allows the address ADD2 corresponding to the read mode to be applied to the first memory 63 through the multiplexer 65 and at the same time the first memory. Reference numeral 63 controls the reading board so that the data stored through the R port is output in the order as shown in FIG. The signal output in this manner is applied to the A input terminal of the multiplexer 62. The multiplexer 62 selects the signal applied to the A input terminal to the modulator 70 by the signal output from the control circuit 67.

In the period during which the read operation of the first memory 63 proceeds, data of the ECC block unit corresponding to the next time is stored in the second memory 64. To store in the second memory 64, the control circuit 67 outputs a control signal to connect the B output terminal and the input terminal of the demultiplexer 61, so that the signal output from the demultiplexer 61 is output to the second memory 64. Is applied to the recording data input terminal (W). At this time, the stored address data is provided through the multiplexer 66. The multiplexer 66 provides the ADD1 signal output from the control circuit 67 to the second memory 64. The order stored in the second memory 64 is the same as the order stored in the first memory 63, and the read time of the first memory 63 and the storage time of the second memory 64 are the same.

On the contrary, when the read and store operations are completed, the first memory 63 stores the ECC block data that is applied next, and the second memory 64 reads the stored ECC block data and outputs them to the modulator 70. The address to be read is output in the order as shown in FIG. 5. The number of addresses to be grouped into one block unit (in this case, k) is read in ① order, and k data are read in order ②. And so on. Where k must be at least 2.

The modulator 70 modulates the signals output in the order of FIG. 5 according to the characteristics of the recording medium 80 and outputs them to the recording medium 80.

When recorded by this process, the data on the recording medium is arranged in the form shown in FIG. That is, sync data of a * k bytes is recorded and the corresponding pure data is arranged to be recorded next.

In this case, the size of the sync signal is longer by k than in the case shown in FIG. Therefore, the probability of reducing the synchronization of the data transmitted by the sync code of a * k bytes is increased.

A decoder for reproducing the data recorded as described above will be described below.

Since the decoder is performed in the reverse order of the encoder, it will be described schematically.

When data recorded in the arrangement as shown in FIG. 7 is picked up from the recording medium 80, the demodulator 90 demodulates by the modulation and inverse method made in the modulator 70. For example, if the modulation is 8-14 modulation, the demodulator 90 outputs 14-8 demodulation. The reverse interleaver 100 controls the data to be output in the order shown in FIG. 4 since the data demodulated in this way is applied in the order shown in FIG. The reverse interleaver 100 controls the data to be output in the order shown in FIG. In other words, the relocated data is returned to its original position. The 2D Reed Solomon decoder 110 decodes the data output in the order shown in FIG. 4 and decodes only the sync code, ID code, and pure data. The signal output from the 2D Reed Solomon decoder 110 is output to the extractor 120 so that only a pure data signal excluding the SYNC and ID signals is output to the source decoder 130 in the normal playback mode. However, during trick play, the pure data signal, which is an ID signal, is output together to the source decoder 130. The source decoder 130 restores and outputs the data compressed by the source decoder 20. The inverse processor 140 processes the signal output from the source decoder 130 as opposed to that performed by the preprocessor 10 and outputs 910 * 525 size image data in an analog form.

As described above, in the digital signal processing system, in the digital signal processing system, the sync code is arranged on the recording medium by changing the transfer order by the interleaving method before the signal output in the ECC block unit is modulated. By increasing the width of time, there is an advantage of facilitating synchronous detection at the time of reproduction, and an advantage of reducing the frequency of occurrence of data collapse due to the influence on errors caused by external or internal factors.

Claims (4)

An error correcting code by adding a source encoder for compressing the applied image data according to a predetermined bit rate, and a sync signal and a recognition signal ID corresponding to the image data output from the source decoder output from the source encoder (ECC) a digital device having a two-dimensional Reed Solomon encoder for coding and outputting in block units, and a modulator for predetermined digital modulation to record a signal output from the two-dimensional Reed Solomon encoder on a recording medium. A sync code interleaver of a signal processing system, comprising: first selecting means for selectively outputting an m × n byte signal including a byte sync code output from the two-dimensional Reed Solomon encoder by a first control signal; A first memory for storing and reading a signal output from the first selecting means by a second control signal; A second memory for storing and reading the signal output from the first selecting means by the third control signal; Second selecting means for selectively outputting a signal read out from said first memory and said second memory to said modulator by a fourth control signal; Third selecting means for selectively outputting different address data to the first and second memories in a storage mode and a read mode by a fifth control signal; And alternately storing and reading a first control signal for outputting data of the 2D Reed Solomon encoder in units of m × k bytes and data output in units of m × k bytes in the first and second memories. Second and third control signals, fourth control signals for sequentially outputting data read from the first and second memories, and axk bytes in a mode for reading data from the first and second memories. And a control circuit for generating a fifth control signal specifying an address so that unit sync data is configured. The 2D Reed-Solomon encoder of claim 1, wherein the address data output from the control circuit when the first and second memories are in a storage mode is arranged in a column direction of sync code, identification code, pure data, and internal code. Is generated so as to store a signal output from the data, and in the read mode, address data output from the control circuit is generated such that data stored in the first and second memos is read out in k units in a column direction. Synccord interleaving device. The sync code interleaving apparatus according to claim 1, wherein the k value is smaller than the n value and is at least two. An encoding process for compressing the applied image data according to a predetermined bit rate and encoding two-dimensional Reed Solomon; A storage process for storing m-byte data including a-byte sync code in a memory in a column direction when image data of an error correction coding unit composed of m × n bytes by the 2D Reed Solomon encoding is applied; The data of n-byte row direction data stored in the memory is sequentially read from column 1 to column m in a predetermined k (where 2 ≦ k <n) bytes in a row direction, and k × a bytes are read. A read process for expanding and outputting sync data with a sync code of; And a modulation / recording process for recording the data read in the reading process on the recording medium by performing a predetermined modulation to record the extended code length of the sync code.