KR100271446B1 - Variable length encoding and deformatting device of a dvcr - Google Patents

Abstract

PURPOSE: A VLC(Variable Length Coding) and deformatting device of a digital VCR(Video Cassette Recorder), is provided to simultaneously perform VLC and deformatting when restoring a bit string of variable length coded and compressed video data, so as to restore a run-amp of a DCT(Discrete Cosine Transform) coefficient. CONSTITUTION: A split unit(200) divides segment unit of data supplied from an ECC(Error Correcting Coding) processor into an AC coefficient, a DC coefficient, a state number and a quantization number, for outputting. An AC storage unit(210) stores the AC coefficient by the unit of segment. A packing unit(220) performs packing for an output of the AC storage unit(210) to the 16-bit unit of data through each pass step. A variable length decoding unit(230) receives segment data packed every pass step, to output a run-amp value for restoration to bit string data having an original length. A run-amp memory(240) receives the run-amp value and the DC coefficient, for storing. Segment memories(250,260) having a ping-pong structure store an output of the run-amp memory(240) by the unit of segment. A buffer(270) receives the state number and the quantization number, for temporary storing. And a controller(280) controls a packing step of the packing unit(220), stores a present state of the pass step and each state flag in a state register, and controls an input/output of the buffer(270) and the segment memories(250,260).

Description

Variable Length Decoding and Deformatting Apparatus for a Digital VCR

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable length decoding and deformatting apparatus of a digital VRL. In particular, the variable length of a digital VRL to decode the variable length code during the decoding of the compressed data of the digital video cassette. The present invention relates to a decoding and deformatting apparatus.

In general, three quantization vectors, that is, a class number, an area number, and a quantization number QNO, are required to quantize data of a DCT block.

The class number (Class No.) is determined by the coefficient of each pixel of the DCT block, the area number (Area No.) is determined in units of DCT blocks, and the quantization number (QNO) is determined in units of macro blocks.

Subsequently, the quantized data generates RLC (Run-Length-Coding), that is, a value of (RUN, AMP) representing the number of consecutive zeros and the magnitude of the AC coefficient in each DCT block unit. VLC (Variable-Length-Coding) is performed.

The data performed up to the VLC, that is, the AC data of the variable length coded DCT block, has a ping-pong structure as shown in FIG. 1. Are stored in segments.

That is, when the N-th segment block is written to the first segment memory 100 and then started to be read into the formatter 120, the second segment memory 110 receives and writes the N + 1-th segment block.

In addition, when the N + 1th segment block is written to the second segment memory 110 and then read to the packer unit 120, the first segment memory 100 receives the N + 2th segment block and receives the N + 2th segment block. Will be written.

Therefore, the first segment memory 100 and the second segment memory 110 are memories having the same size, and should have a capacity capable of storing the size of one segment.

In other words, since the deformatting of digital VR is processed by segment, it should be a capacity to store 1 segment unit. For reference, 1 segment (1920 byte) is composed of 5 macro blocks (384 bytes), and 1 macro is used. The block consists of six DCT blocks, and one DCT block consists of 64 bytes.

Therefore, the first segment memory 100 and the second segment memory 110 should always have a space of 64 words per DCT block so that each DCT block can be stored.

The stored data is received from the packer unit 120 and packed in units of 16 bits. The DCT block currently stored in the first segment memory 100 is passed through pass 1 and pass 2. ), The result is stored in the first ECC memory 130 having a ping-pong structure, and the result is a result of packing the DCT block stored in the second segment memory 110 if the packing is performed by a pass 3 process. Is stored in the second ECC memory 140.

Here, the pass 1 process is a formatting process in units of DCT blocks. That is, the variable length coded code is packed and stored in an area allocated to each block unit, and when stored, the variable length coding code is stored in the first auxiliary memory 150.

The pass 2 process is a formatting process in macro block units. That is, the magnetic macroblock data stored in the first auxiliary memory 150 after the pass 1 process is packed and stored in an empty area after the pass 1 process among the 77-byte areas allocated in units of macro blocks.

Valid bits that are not stored in this process are also stored in the second auxiliary memory 160, which is an extra memory as in the pass 1 process.

A pass 3 process is a process of repacking valid bits not stored in the pass 2 process for all 30 DCT blocks in a segment without distinguishing the DCT block and the macro block and storing them in an empty place.

This process also discards valid bits that were not stored.

The variable length coded data packed by the above operation is stored in the first ECC memory 130 and the second ECC memory 140 having a ping-pong structure, and then outputted to an Error Correcting Coding (ECC) unit to correct an error. Will be compressed.

In order to restore such compressed image data, a variable length decoding and deformatting apparatus by the above inverse process should be provided.

According to the present invention, variable length decoding is performed to recover run-amp pairs of DCT coefficients by simultaneously performing variable length decoding and deformatting when restoring a bit string of compressed data having variable length coding. And a deformatting apparatus.

1 is a block diagram showing a conventional digital VR formatting device.

Figure 2 is a block diagram showing a variable length decoding and deformatting apparatus of a digital VR according to the present invention.

<Explanation of symbols for the main parts of the drawings>

200: split portion 210: AC storage portion

220: packing unit 230: variable length decoding unit

240: run-amp memory 250, 260: segment memory

270: buffer unit 280: control unit

290: State register 290: Address memory

In order to achieve the above object, the variable length decoding and deformatting apparatus of the digital VR according to the present invention uses the AC coefficients and the DC coefficients as shown in FIG. A split unit 200 which outputs the DC, the state number STA, and the quantization number QNO separately; An AC storage unit 210 for storing AC coefficients from the split unit 200 in units of segments; A packing unit 220 for packing the output of the AC storage unit 210 with data in units of 16 bits through each pass process; A variable length decoder 230 for receiving the segment data packed for each pass by the packing unit 220 and outputting a run-amp (RUN, AMP) value for restoring the bit string data having an original length; A run-amp memory 240 for receiving and storing the run-amplifier value output from the variable length decoder 230 and the DC coefficient DC output from the split unit 200; A segment memory (250, 260) having a ping-pong structure and storing the output of the run-amp memory (240) in units of segments; A buffer unit 270 that receives the state number STA and the quantization number QNO output from the split unit 200 and temporarily stores them; A control unit for controlling the packing process of the packing unit 220 to store the current state and each state flag of the control and pass process in the state register 290, and controls the input and output of the buffer 270 and the segment memory (250, 260) ( 280).

The variable length decoding and deformatting apparatus of the present invention configured as described above will be described in detail as follows.

One segment data of 385 bytes, which are applied in 8-bit units from the ECC, is received by the split unit 200, and is divided into an AC number AC, a DC coefficient DC, a state number STA, and a quantization number QNO. .

The AC coefficient AC separated by the split unit 200 is stored in the AC storage unit 210 in units of segments, and the state number STA and the quantization number QNO are applied to and stored in the buffer unit 270. The DC coefficient DC is provided to the run-amp memory 240.

The output of the AC storage unit 210 is applied to the packing unit 220 and packed into 16-bit unit data, and the data compressed by the variable length decoder 230 is restored to output (RUN, AMP) values. do.

At this time, when the packing and decoding is performed by the packing unit 220 and the variable length decoding unit 230, each pass process is performed, which will be described in more detail.

If the variable length decoding unit 230 generates an end of block (EOB) or an end of DCT (EOD) during variable length decoding by the pass 1 process, the controller 280 may indicate an address and flags of EOB and EOD. And is stored in the state register 270.

On the other hand, the packing unit 220 has two packing states, since 32 bits of data are initially input when the variable length decoder 230 is input, and then 16 bits of data are input.

The controller 280 ends the pass 1 process when the number of EOB and EOD flags stored in the state register 290 and the number of flags detected by the current variable length decoder 230 match during the pass 1 process. Course and pass 3 course.

Therefore, first, a block that has not completed packing in the first pass is loaded by the packing unit 220, and the packing is performed by sequentially loading the last data of the EOD block and the remaining data of the EOB block in order to pack in 16-bit units.

Like the pass 1 process, the EOB and EOD flags generated by the pass 2 process and the pass 3 process are stored in the state register 290 by the controller 280.

At this time, the pass 2 process and the pass 3 process are not significantly different in the basic operation, but in the case of the pass 2 process during packing, the flag in the macro block is referred to, but the pass 3 process refers to the entire flag of the segment.

When the packing is completed in this way, that is, when there is no EOB flag to be packed or no EOD flag to be processed, the variable length decoding process is terminated. This is because it is decoded by 230.

Therefore, the (RUN, AMP) value restored by the variable length decoder 230 is applied to the run-amp memory 240 and stored together with the DC coefficient DC output from the split unit 200.

The stored (RUN, AMP) values are applied to the first and second segment memories 250 and 260 of the ping-pong structure, and are stored and output in units of segments.

In other words, the decoded result is written to one segment memory, and the other segment memory outputs the stored data to the dequantizer.

In this case, the controller 280 controls the input / output of the first and second segment memories 250 and 260 by the address stored in the address memory 300.

Meanwhile, the buffer unit 270 also receives the state number STA and the quantization number QNO applied from the split unit 200 under the control of the controller 280, and buffers the state number STA and outputs the same to the dequantizer.

As described in detail above, the variable length decoding and deformatting apparatus of the digital VR according to the present invention has an effect of providing an apparatus for restoring the original data by the variable length decoding and deformatting of the formatted and variable length encoded data. have.

Claims (1)

A split unit for dividing data in segment units applied from the error correction code processor into AC coefficients, DC coefficients, state numbers, and quantization numbers; An AC storage unit for storing the AC coefficient in the segment unit from the split unit; A packing unit for packing the output of the AC storage unit with data of 16 bit units through each pass process; A variable length decoder for receiving segment data packed for each pass by the packing unit and outputting a run-amplifier value for restoring bit string data having an original length; A run-amp memory configured to receive and store a run-amplifier value output from the variable length decoder and a DC coefficient output from the split unit; A segment memory having a ping-pong structure and storing the output of the run-amp memory in units of segments; A buffer unit receiving the state number and the quantization number output from the split unit and temporarily storing the state numbers and quantization numbers; And a control unit for controlling the packing process of the packing unit, storing a current state and each state flag of the packing process in a state register, and controlling the input / output of the buffer and the segment memory. Deformatting device.

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