KR100246639B1 - Digital vcr formatter - Google Patents

Abstract

The present invention relates to a format of a digital VR, in which a size of a memory composed of a ping-pong structure for storing data in units of segments and a processing time during a formatting process can be reduced. Formatting) device.

An object of the present invention is to increase the processing speed by first packing the data of the unit of variable length coded segment in 16-bit unit and then formatting it, and also to reduce the size of the memory by reformatting the segment memory to 385 bytes It is an object of the present invention to provide a formatting device of a digital VR.

Therefore, since the variable length coded variable length data is packed in 16-bit units in advance, the data of the segment unit is packed into data having a size of 385 bytes in advance and stored in the memory. Since the process of packing unit 1 performs the pass 1 process, only the pass 2 process and the pass 3 process need to be performed, thereby increasing the processing speed.

Description

Formatting Apparatus for a Digital VCR

The present invention relates to a format of a digital VR, in which a size of a memory having a ping-pong structure for storing data in units of segments and processing time during a formatting process can be reduced. ) Relates to the device.

In general, three quantization vectors, that is, a class number, an area number, and a quantization number QNO, are required to quantize data of a DCT block.

The class number (Class No.) is determined by the coefficient of each pixel of the DCT block, the area number (Area No.) is determined in units of DCT blocks, and the quantization number (QNO) is determined in units of macro blocks.

Subsequently, the quantized data generates RLC (Run-Length-Coding), that is, (RUN, AMP) value representing the number of ?? 0 ?? and the magnitude of the AC coefficient in succession for each DCT block. VLC (Variable-Length-Coding) is performed by the prescribed code table.

The data performed up to the VLC, that is, the AC data of the variable length coded DCT block, has a ping-pong structure as shown in FIG. 1. Are stored in segments.

That is, when the N-th segment block is written to the first segment memory 100 and then started to be read into the formatter 120, the second segment memory 110 receives and writes the N + 1-th segment block.

In addition, when the N + 1 th segment block is written to the second segment memory 110 and then read to the formatter 120, the first segment memory 100 receives the N + 2 th segment block and writes it to the second segment memory 110. Done.

Therefore, the first segment memory 100 and the second segment memory 110 are the memory having the same size, and should be a capacity capable of storing the size of one segment (1920 words).

In other words, since the deformatting of digital VR is processed by segment, it should be a capacity to store 1 segment unit. For reference, 1 segment (1920 byte) is composed of 5 macro blocks (384 bytes), and 1 macro is used. The block consists of six DCT blocks, and one DCT block consists of 64 bytes.

Therefore, as shown in FIG. 3, the first segment memory 100 and the second segment memory 110 should always have a space of 64 words per DCT block so that each DCT block can be stored.

The stored data is received from the packer unit 120 and packed in units of 16 bits. If the DCT block stored in the first segment memory 100 is currently formatted by pass 1, the result is If the DCT block stored in the first ECC memory 130 and the second segment memory 110 is being formatted by the pass 1 process, the result is stored in the second ECC memory 140.

In this case, the overflowed result is stored in the first auxiliary memory 150.

In addition, the result of the overflow during the pass 2 process (pass 2) is stored in the second auxiliary memory 160.

Here, the pass 1 process is a formatting process in units of DCT blocks. That is, the variable length coded code is packed and stored in an area allocated to each block unit, and when stored, the variable length coding code is stored in the first auxiliary memory 150.

The pass 2 process is a formatting process in macro block units. That is, the magnetic macroblock data stored in the first auxiliary memory 150 after the pass 1 process is packed and stored in an empty area after the pass 1 process among the 77-byte areas allocated in units of macro blocks.

Valid bits that are not stored in this process are also stored in the second auxiliary memory 160, which is an extra memory as in the pass 1 process.

A pass 3 process is a process of repacking valid bits not stored in the pass 2 process for all 30 DCT blocks in a segment without distinguishing the DCT block and the macro block and storing them in an empty place.

This process also discards valid bits that were not stored.

The result of formatting the ping-pong structure in this manner is output to the error correction encoder, thereby formatting is performed.

However, in this case, since the size of one variable-length coded DCT block has a maximum size of 64 words, 64 words of space for the worst case should be secured at all times. The size of each memory having a structure should be the capacity to store a size of 1920 words.

That is, there is a problem that the size of the memory increases by securing the memory capacity in consideration of only the worst state.

Accordingly, in view of such a problem, the present invention packs the data of a variable-length coded segment unit first into 16-bit units and then formats the memory to increase the processing speed, and rearranges the segmented data into 385 bytes in the segment memory to perform formatting. It is an object of the present invention to provide a formatting device of a digital VR to reduce the size of.

1 is a block diagram showing a conventional digital VR formatting device.

Figure 2 is a block diagram showing a digital VR formatting apparatus according to the present invention.

FIG. 3 illustrates an address structure stored in the segment flag memory according to FIG. 2.

To do.

FIG. 4 calculates an actual address from the position of each DCT block based on FIG.

Figure to illustrate the process.

FIG. 5 is a diagram for explaining an address structure stored in the auxiliary memory according to FIG. 2; FIG.

* Explanation of symbols for the main parts of the drawings

200: first packer section 210, 220: first segment memory

230: second packer 240, 250: ECC memory

260, 270: auxiliary memory 280: control unit

290, 300: segment flag memory 310, 320: auxiliary flag memory

In order to achieve the above object, a digital VRL formatting apparatus according to the present invention includes a first packer unit that receives data of a variable length coded segment unit and packs it into 16-bit unit data as shown in FIG. 200); A segment memory (200, 210) configured of a ping-pong structure to rearrange and store 16-bit segment data output from the first packer unit into segment data of 385 bytes; A second packing unit 230 which receives the output of the segment memories 200 and 210 and packs them by each pass process based on the information stored in the segment flag memories 260 and 270 and rearranges them into 385 bytes; An ECC memory (240, 250) having a ping-pong structure and outputting segment data packed by the second packer unit (230) to the ECC in units of 8 bits; An auxiliary memory (260, 270) for storing the overflowed data during each pass of the variable length coded segment unit data stored in the segment memories (210, 220); Segment flag memory (260, 270) for storing the end address of the variable-length coded segment unit data stored in the segment memory (210, 220), the information of the length and the flag information for each pass process ; An auxiliary flag memory (310, 320) stores the start address, the length, the end address, the length, and the flag information of the overflowed data stored in the auxiliary memory (260, 270).

The formatting apparatus of the digital VR of the present invention configured as described above will be described in detail as follows.

One segment data of variable length coded DCT block units, that is, (RUN, AMP) values are applied to the first packer unit 200 to be packed in units of 16 bits. Generally, in order to increase processing speed during the formatting process, Since 16-bit data is used, the 16-bit data is packed in advance.

That is, a pass 1 process is performed. Since data having a variable length coded segment has a value ranging from at least 3 bits to at most 16, values of 16 bits or less are packed in units of 16 bits by the pass 1 process. For reference, this process is conventionally performed in the segment memory.

The data in units of segments packed in units of 16 bits is stored in the first segment memory 210 and the second segment memory 220 having a ping-pong structure, and the stored data is stored in the path 2 under the control of the controller 280. Packed by and pass 3 process, it is rearranged in 385 byte units and stored in advance.

The overflowed data generated during the packing by the pass 2 and the pass 3 is stored in the first auxiliary memory 260 and the second auxiliary memory 270. A flag and a start address stored in the first segment memory 290 and the second segment memory 300 to determine whether overflowed data of each segment block unit is stored in the auxiliary memories 260 and 270. And the length, the end address, and the length are stored in the auxiliary flag memories 310 and 320.

At this time, the information stored in the segment flag memory (290, 300), as shown in Figure 3, a total of 1 bit of flag information, the end address (EA) of 3 bits and its length (EL) of 4 bits It consists of 8 bits.

An example of a method of calculating the actual address from the position of each DCT block thereof will be described with reference to FIG. 4. If the end address EA is set to '100' and the length is set to '01110, the EOB is detected. Since the end address data ends at the fourth position excluding the EOB, its end position can be known, and the end address also has a total length of 7 bits including the end data including the EOB.

In addition, when the flag is set to '0', it indicates that the EOB is detected in the DCT block.

Since this information is divided into DCT block units, a total of 30 pieces of information, that is, 240 bits, are included for one segment data.

On the other hand, the start address, the length and the end address, the information of the length, and the flag information about the pass process stored in the auxiliary flag memory (310, 320) by the control unit 250, the auxiliary flag memory (310, 320) The memory structure thereof is shown in FIG. 5.

Its structure consists of 23 bits for each DCT block, including a flag having a size of 1 bit from the most significant bit (MSB), a 7-bit start address (SA), and a 4-bit start data length (SL). And an end address (EA) of 7 bits and a length (EL) of end data of 4 bits.

That is, it has a size of 690 bits for one segment data, which should be composed of 30 × 23 bits because one segment is composed of 30 DCT blocks.

If the control unit 250 detects an end of block (OBB) of one DCT block in a DCT block of 16-bit packed units, the DCT block means that the packing is completed, and thus the auxiliary flag memories 310 and 320 may be used. The flag stored in will be set to ?? 0 ??, otherwise it will be set to ?? 1 ??.

The segment data rearranged into 385 byte 3 units by each pass process is stored in the ECC memories 240 and 250 of the ping-pong structure and output to the ECC unit in 8-bit units.

As described in detail above, the digital VR formatting apparatus according to the present invention packs the variable length encoded 8-bit unit data in 16-bit units in advance, and then pre-segments the data in segment units into data having a size of 385 bytes. Since the size of the memory is reduced because it is packed and stored in the memory, and the pass 1 process is performed in the process of packing in 16-bit units, only the pass 2 process and the pass 3 process are performed, so the processing speed increases accordingly. have.

Claims (14)

A first packer unit receiving the variable length coded segment unit data and packing the segment data in 16 bit unit; A segment memory configured of a ping-pong structure to rearrange and store 16-bit segment data output from the first packer into 385-byte segment data; A second packing part which receives the output of the segment memory and packs it by each pass process based on the information stored in the segment flag memory and rearranges it to 385 bytes; An ECC memory having a ping-pong structure and outputting segment data packed by the second packer to an ECC in units of 8 bits; An auxiliary memory for storing the overflowed data during each pass of the variable length coded segment unit data stored in the segment memory; A segment flag memory configured to store an end address of variable length coded segment unit data stored in the segment memory, information on the length of the segment unit data, and flag information about a pass process for each pass process; And an auxiliary flag memory for storing a start address, a length, an end address, a length, and flag information of overflowed data stored in the auxiliary memory. 2. The apparatus of claim 1, wherein the second packing unit performs a pass 2 process and a pass 3 process. 2. The apparatus of claim 1, wherein the information stored in the segment flag memory is information about an end address of variable length coded segment unit data stored in the segment memory, information about its length, and flag information about a pass process. . 4. The apparatus of claim 3, wherein the flag information is one bit. 4. The apparatus of claim 3, wherein the end address is 3 bits. 4. The apparatus of claim 3, wherein the end address is 4 bits long. 4. The format of claim 3, wherein the flag is set to ?? 0 ?? if an EOB is detected in the data in each DCT block during the pass process, otherwise it is set to ?? 1 ??. Device. 2. The digital VRL formatting according to claim 1, wherein the information stored in the auxiliary flag memory is information of a start address and a length of overflow data by each pass process, an end address and information of a length and flag information. Device. 9. The apparatus of claim 8, wherein the flag information is one bit. 9. The apparatus of claim 8, wherein the start address is 7 bits. 9. The apparatus of claim 8, wherein the start address is 4 bits long. 9. The apparatus of claim 8, wherein the end address is 7 bits. 9. The apparatus of claim 8, wherein the end address is 4 bits long. 9. The apparatus of claim 8, wherein the flag is set to ?? 0 ?? if the EOB is detected in the overflowed data, otherwise it is set to ?? 1 ??.

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