KR100246641B1 - Digital vcr formatter - Google Patents

Abstract

The present invention relates to a device for formatting a digital VR, and to reduce the size and processing time of a segment memory by first packing the data of a variable length coded segment unit in 16 bit units and then storing the data in macro block units. It is also an object of the present invention to provide a digital VRL formatting apparatus that allows storage and formatting of segment data and transmission to ECC during one segment period, that is, 2048 clocks. A first packer unit receiving the data in segment units and packing the segment data in 16 bit units; A segment memory having a ping-pong structure and storing segment data of 16-bit units output from the first packer unit in macroblock units; A second packer unit receiving the output of the segment memory and packing it by each pass process based on information stored in the segment flag memory; An ECC memory for rearranging the segment data packed by the second packer unit in predetermined bit units and outputting the segment data; The segment flag memory stores address information of variable length coded segment unit data stored in the segment memory for each pass process.

Description

Formatting Apparatus for a Digital VCR

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a formatting apparatus for digital BCs, which can reduce the size of a memory having a ping-pong structure for storing data in segments.

In general, three quantization vectors, that is, a class number, an area number, and a quantization number QNO, are required to quantize data of a DCT block.

The class number (Class No.) is determined by the coefficient of each pixel of the DCT block, the area number (Area No.) is determined in units of DCT blocks, and the quantization number (QNO) is determined in units of macro blocks.

Subsequently, the quantized data generates RLC (Run-Length-Coding), that is, (RUN, AMP) value representing the number of ?? 0 ?? and the magnitude of the AC coefficient in succession for each DCT block. VLC (Variable-Length-Coding) is performed by the prescribed code table.

The data performed up to the VLC, that is, the AC data of the variable length coded DCT block, has a ping-pong structure as shown in FIG. 1. Are stored in segments.

That is, when the N-th segment block is written to the first segment memory 100 and then started to be read into the formatter 120, the second segment memory 110 receives and writes the N + 1-th segment block.

In addition, when the N + 1th segment block is written to the second segment memory 110 and then read to the packer unit 120, the first segment memory 100 receives the N + 2th segment block and receives the N + 2th segment block. Will be written.

Therefore, the first segment memory 100 and the second segment memory 110 are the memory having the same size, and should be a capacity capable of storing the size of one segment (1920 words).

In other words, since the deformatting of digital VR is processed by segment, it should be a capacity to store 1 segment unit. For reference, 1 segment (1920 byte) is composed of 5 macro blocks (384 bytes), and 1 macro is used. The block consists of six DCT blocks, and one DCT block consists of 64 bytes.

Therefore, the first segment memory 100 and the second segment memory 110 should always have a space of 64 words per DCT block so that each DCT block can be stored.

The stored data is received from the packer unit 120 and packed in units of 16 bits. The DCT block currently stored in the first segment memory 100 is passed through pass 1 and pass 2. ), The result is stored in the first ECC memory 130 having a ping-pong structure, and the result is a result of packing the DCT block stored in the second segment memory 110 if the packing is performed by a pass 3 process. Is stored in the second ECC memory 140.

Here, the pass 1 process is a formatting process in units of DCT blocks. That is, the variable length coded code is packed and stored in an area allocated to each block unit, and when stored, the variable length coding code is stored in the first auxiliary memory 150.

The pass 2 process is a formatting process in macro block units. That is, the magnetic macroblock data stored in the first auxiliary memory 150 after the pass 1 process is packed and stored in an empty area after the pass 1 process among the 77-byte areas allocated in units of macro blocks.

Valid bits that are not stored in this process are also stored in the second auxiliary memory 160, which is an extra memory as in the pass 1 process.

A pass 3 process is a process of repacking valid bits not stored in the pass 2 process for all 30 DCT blocks in a segment without distinguishing the DCT block and the macro block and storing them in an empty place.

This process also discards valid bits that were not stored.

The variable length coded data packed by the above operation is stored in the first ECC memory 130 and the second ECC memory 140 having a ping-pong structure, and then output to the error correcting coding (ECC) unit. It is explained with reference to.

Usually, when storing or formatting one segment data, its operation is performed for 2048 clocks. First, data of a variable length coded segment unit currently applied for the first 2048 clocks is stored in the first segment memory 100, and then During the 2048 clock, data of a variable length coded segment unit applied second is stored in the second segment memory 110.

In this case, the data of the segment unit stored in the first segment memory 100 is formatted by the packer unit 120 and stored in the first ECC memory 130.

During the third 2048 clock, the data of the third variable length coded segment unit is stored in the first segment memory 100, and the data stored in the second segment memory 110 is packed by the packer unit 120. The first variable length encoded segment data stored in the ECC memory 130 is transmitted to the ECC unit.

This operation is repeated until the last variable length coded segment unit data is transmitted to the ECC unit.

However, in this case, since the size of one variable-length coded DCT block has a maximum size of 64 words, 64 words of space for the worst case should be secured at all times. A segmented memory having a structure must be capable of storing a size of 1920 words each.

In addition, since the storage, packing, and transmission to ECC are performed for each 2048 clocks, segment processing of the data requires a high-speed processing device, which causes cost increase.

Therefore, in view of the above problem, the present invention packs the data of the variable-length coded segment unit first in 16-bit units and stores it in the macro block unit, thereby reducing the size of the segment memory, and also for one segment period, that is, 2048 clocks. It is an object of the present invention to provide a formatting device of digital BCs that allows storage and formatting of segment data and transmission to ECC.

1 is a block diagram showing a conventional digital VR formatting device.

2 is a view showing a processing flow of variable length coded data according to FIG. 1;

3 is a block diagram showing a device for formatting a digital VR according to the present invention;

4 is a diagram illustrating flag information stored in a segment flag memory of FIG. 3;

5 is a view showing a processing flow of variable length coded data according to FIG. 3;

* Explanation of symbols for main parts of the drawings

200: first packer section 210, 220: first segment memory

230: second packer unit 240: ECC memory

250: control unit 260, 270: segment flag memory

In order to achieve the above object, a digital VRL formatting apparatus according to the present invention includes a first packer unit which receives data of a variable length coded segment unit and packs it into 16-bit unit data as shown in FIG. 200); A segment memory (200, 210) configured to have a ping-pong structure and storing segment data of 16-bit units output from the first packer unit (200) in macroblock units; A second packer unit 230 receiving the outputs of the segment memories 200 and 210 and packing them by each pass process based on information stored in the segment flag memories 260 and 270; An ECC memory 240 for rearranging the segment data packed by the second packer unit 230 by a predetermined bit unit and outputting the segment data by ECC; A segment flag for storing a start address, a length and an end address of the variable length coded segment unit data stored in the segment memories 210 and 220, information about the length, and flag information about a pass process for each pass process. Memory 260 and 270.

The formatting apparatus of the digital VR of the present invention configured as described above will be described in detail as follows.

One segment data of variable length coded DCT block units, that is, (RUN, AMP) values are applied to the first packer unit 200 to be packed in units of 16 bits. Generally, in order to increase processing speed during a formatting process, Since 16-bit data is used, the 16-bit data is packed in advance.

That is, a pass 1 process is performed. Since data of a variable length coded segment unit has a value of at least 3 bits up to 16, a value of 16 bits or less is packed in 16 bit units by a pass 1 process. For reference, this process is conventionally performed in the segment memory.

In this case, the start address, the length and the end address of the variable length coded segment unit data generated during the packing by the first packer unit 200, the information of the length, and the flag information on the pass process may be controlled. Is stored in the segment flag memories 260 and 270, and the structure of the memory is shown in FIG.

Its structure consists of 23 bits for each DCT block, including a flag having a size of 1 bit from the most significant bit (MSB), a 7-bit start address (SA), and a 4-bit start data length (SL). And an end address (EA) of 7 bits and a length (EL) of end data of 4 bits.

That is, it has a size of 690 bits for one segment data, which should be composed of 30 × 23 bits because one segment is composed of 30 DCT blocks.

If the control unit 250 detects an end of block (EOB) of one DCT block in a DCT block of packed 16-bit units, the DCT block indicates that packing is completed, and thus, the segment flag memories 260 and 270 may be used. The flag stored in will be set to ?? 0 ??, otherwise it will be set to ?? 1 ??.

Meanwhile, data of a variable length coded segment unit packed with 16 bits in the first packer unit 200 is stored in a ping pong form in the first segment memory 210 and the second segment memory 220 having a ping pong structure. Since the segment data is packed in units of 16 bits by the first packer unit 200, the size thereof is reduced.

In other words, instead of securing a space of 16 bytes for each DCT block at all times, the space of the memory can be significantly reduced because packing is performed in advance by pass 1 and stored in units of macro blocks.

The segment data of the DCT block unit stored in the segment memories 210 and 220 is applied to the second packer unit 230 to perform a pass 2 process and a pass 3 process. (SA) and end address (EA) are defined by the following equation (1).

[Equation 1]

는 매크로 블럭의 위치를 나타낸 것으로, 0부터 4까지의 값을 가지게 되는데, 이는 즉 한 매크로 블럭이 5개의 세그먼트 블럭으로 구성되기 때문이다.here,

Denotes the position of the macro block, which has a value from 0 to 4 because one macro block is composed of five segment blocks.

On the other hand, when the second packer unit 230 performs path 2 in units of macro blocks, packing is performed based on information stored in the segment flag memories 260 and 270. Even in this process, the EOB of the macro block is controlled by the controller ( If not detected at 250), the flag will be set to ?? 0 ??.

In addition, the second packer unit 230 performs the pass 3 process of the segment data unit after the pass 2 is performed. In this case, the second packer unit 230 does not have to refer to the information stored in the segment flag memories 260 and 270.

Segment data processed in units of 16 bits packed by the second packer unit 230 is transferred to the ECC memory 240. The segment data packed in units of 16 bits is rearranged to 385 bytes. Is set to 16 bits, but must be transmitted in units of 8 bits to be transferred to the ECC unit.

However, conventionally, all segments of data are formatted and transmitted to the ECC unit during 2048 clocks. In the related art, a pair of ping-pong structures are stored in memory, formatted, and transferred to the ECC unit during each 2048 clocks. In the present invention, since the formatting is performed in units of macro blocks in the present invention, the space of the segment memories 210 and 220 and the processing speed thereof are shortened, so that only one ECC memory 240 can be transferred to the ECC unit. Do.

That is, as shown in FIG. 5, processing time is reduced in the formatting process to enable formatting during 2048- (385+ ??) clocks, and also transfer to the ECC unit during 385+ ?? clocks, thereby providing a single ECC. Transfer is possible even with only the memory 240, so that the number and space of the memory is reduced.

As described in detail above, the digital VRL formatting apparatus according to the present invention packs the data of the variable length coded 8-bit unit in 16-bit units in advance and performs a pass process by a segment memory having a ping-pong structure in macro-block units. This reduces the amount of memory and processing time.

In addition, since the processing time is reduced, formatting and transmission to the ECC unit can be performed for one 2048 clock, thereby reducing the cost by using only one ECC memory.

Claims (9)

A first packer unit receiving the variable length coded segment unit data and packing the segment data in 16 bit units; A segment memory having a ping-pong structure and storing segment data of 16-bit units output from the first packer unit in macroblock units; A second packer unit receiving the output of the segment memory and packing it by each pass process based on information stored in the segment flag memory; An ECC memory for rearranging the segment data packed by the second packer unit in predetermined bit units and outputting the segment data; And a segment flag memory for storing address information of variable length coded segment unit data stored in the segment memory for each pass process. 2. The apparatus of claim 1, wherein the second packer unit performs a pass 2 process and a pass 3 process. The method of claim 1, wherein the information stored in the segment flag memory is a start address, a length and an end address of the variable length coded segment unit data stored in the segment memory, and information about the length and flag information about a pass process. Formatting device of digital VR. 4. The apparatus of claim 3, wherein the flag information is one bit. 4. The apparatus of claim 3, wherein the start address is 7 bits. 4. The apparatus of claim 3, wherein the length of the start address is 4 bits. 4. The apparatus of claim 3, wherein the end address is 7 bits. 4. The apparatus of claim 3, wherein the end address is 4 bits long. 5. The apparatus of claim 3 or 4, wherein the flag is set to ?? 0 ?? if the EOB is detected by each pass process, otherwise it is set to ?? 1 ??. .

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