KR940020826A - High Definition TV Header Detection Device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-definition television header detection device that separates the bit stream data in which the header and video data are mixed and outputs the video data to a variable length decoder. A data generator; It consists of an address generator that generates an address in accordance with the timing of the video data and writes it to the memory, and generates a read address when reading the memory so that the data required in the next stage can be read from the memory. Applicable in the case of a video phone being delivered.

Description

High Definition TV Header Detection Device

Since this is an open matter, no full text was included.

1 is an exemplary input format of a bit stream,

2 is a block diagram of a header detection apparatus for a high definition television of the present invention.

Claims (3)

A device for separating video streams by mixing a header and video data and outputting the video data to a variable length decoder, wherein the 32-bit image start code and the 16-bit buffer delay code are detected by receiving the input serial input data. A data generator 10 for converting the video data after the sign into a parallel signal by 24 bits and outputting the parallel signal; In synchronization with the 24-bit data output from the data generator 10, a write address of the memory is generated, and when this address is equal to the buffer delay code BCD, the read address of the memory is read. An apparatus for detecting high definition television headers, comprising: an address generator (20) for generating. The data generation unit (10) of claim 1, further comprising: a serial / parallel converter (11) for converting the input serial data into 32-bit parallel data in synchronization with a falling edge of a clock; An image start code checker 12 that checks the 32-bit data of the serial / parallel converter 11 and outputs a square wave control signal when it is an image start code (PSC); The picture start code checker 12 receives the picture start code PSC and outputs 16 bits which are continued as a buffer delay code (BDC), and 1 clock only in the case of the buffer delay code (BDC) first inputted after system reset. A buffer delay code checker (13) for outputting a square wave control signal (BCODE) of; The control signal PSC of the low phase start code checker 12 and the control signal BCODE of the buffer delay code checker 13 are inputted to output data by 24 bits. And a data generator (14) for outputting a selection signal (SCON). The method of claim 1, wherein the address generator 20 is counted at each rising edge of the control signal SCON of the data generator 14 to generate a write address for every 24 bits of data and write the result in a memory. A recording counter 21; The buffer delay code when the clock is rising edge and the buffer delay code check signal (BDCC) is "high" by receiving the buffer delay code (BDC) and buffer delay code check (BDCC) signals generated by the buffer delay code checker (13). A register 22 for latching (BDC); A comparator (23) for comparing the write address of the write counter (21) with the buffer delay code (BDC) of the register (22) and outputting a read start (RDST) control signal when they become equal; A read controller 24 for reading data in the memory when the clock is a falling edge and the read start (RDST) signal or the slice start (SLST) signal is "high"; A read clock generator 25 which receives the read signal of the read controller 24 and outputs the read clock signal RCLK required by the slice divider and the variable length decoder and the chip enable signal CE2 for enabling the memory chip. Wow; A read counter 26 for counting the read address of the memory when the read clock signal RCLK generated by the read clock generator 25 rises; And a multiplexer (27) for receiving a write address and a read address and outputting a write address or read address by a selection signal (SCON). ※ Note: The disclosure is based on the initial application.