JP2913826B2 - Image data decoding circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoding circuit for image data that has been subjected to variable length coding.

Summary of the Invention

According to the present invention, in a decoding circuit for image data that has been subjected to variable length coding, it is detected whether or not image data stored in a reception buffer memory is one frame or more.
When there is more than the number of frames, the frame buffer memory can be omitted by reading out the image data in synchronization with the frame and decoding the image data at the same time.

[Prior art]

For example, in a video conference system according to CCITT Recommendation JT-H320, the terminal device is configured as shown in FIG. That is, 100 is the terminal device, 111 is the video input / output device, 112 is the video codec, 121 is the audio input / output device, 122 is the audio codec, 123 is the delay circuit, 131 is the telematic device, and these are multiplexers. / Demultiplexer 141 is connected to the network interface unit 142. Reference numeral 151 denotes a system control unit, 152 denotes an end / end signal control unit, and 153 denotes an end / network signal control unit. Further, the network interface unit 142 is connected to an external network 200, and an MCU (multipoint control unit) 300 is connected to the network 200. And, in this case, the video codec 112 has the recommendation J
Since the T-H261 is applied and the variable coding method (VLC) is used as the coding method of the image data, the data length of each frame of the image data is not constant. That is, in FIG. 2A, Dv indicates image data of each frame, which is encoded by a predetermined encoding method, and whose data length is different according to the content of the image. Further, a code called PSC is added to the head of the image data Dv so that the head of each frame can be detected or identified by the PSC. Therefore, in the video codec 112, a decoding circuit for decoding the received image data Dv is configured, for example, as shown in FIG. That is, the received image data D is temporarily stored in the reception buffer memory 41 according to the reception clock RXCK, and is sequentially read. Then, the read image data Dv is supplied to the variable-length code decoding circuit 42, and is also supplied to the PSC detection circuit 43 to detect the PSC. When the PSC is detected, the PSC is decoded by the detection output. The decoding of the circuit 42 is permitted, and the image data Dv is decoded into the original fixed-length image data. In this case, the received image data Dv has different data lengths as described above, and accordingly, the time until one frame of image data is decoded also varies, and the next stage (not shown) ) Frame synchronization with the following is not established. Therefore, the decoded image data is sequentially written to the frame buffer memory 44, and the written image data is sequentially read out in synchronization with the frame synchronization pulse from the next stage, and supplied to the next stage. Then, in the next and subsequent stages, while performing necessary processing on the image data read from the memory 44,
The image is supplied to the CRT display through the frame memory and displayed.

[Problems to be solved by the invention]

However, in the above-described decoding circuit, the frame buffer memory 44 is required to achieve frame synchronization with the next stage. The present invention intends to omit the frame buffer memory 44.

[Means for Solving the Problems]

For this reason, according to the present invention, in the decoding circuit which decodes the original fixed-length image data from the image data to which the code indicating the frame is added for each frame while being variable-length coded, A reception buffer memory in which the variable-length image data is written; a variable-length code decoding circuit that decodes the image data read from the reception buffer memory into the original fixed-length image data; A first detection circuit that detects a code indicating the frame from the written image data; a second detection circuit that detects a code indicating the frame from the image data read from the reception buffer memory; The detection output of the first and second detection circuits and the frame synchronization signal are supplied to the reception buffer memory. A reception buffer frame management circuit for controlling reading, wherein the reception buffer frame management circuit counts up one of the detection outputs of the first and second detection circuits and counts down the other, When the result indicates that there is one or more frames of the image data in the reception buffer frame memory, reading of the image data from the reception buffer memory is permitted in synchronization with the frame synchronization signal. This is a decoding circuit for the decoded image data.

[Action]

When one frame or more of image data is stored in the reception buffer memory 11, the image data is read out in synchronization with the frame synchronization signal, and the read out image data is decoded.

【Example】

In FIG. 1, received image data Dv is accumulated in a reception buffer memory 11 according to a reception clock RXCK, and is supplied to a first PSC detection circuit 12,
As shown in FIGS. 2A and 2B, the received image data Dv
The detection pulse Pb is extracted for each PSC, and the pulse Pb is supplied to the reception buffer frame management circuit 13. The management circuit 13 counts the pulse Pb supplied thereto and counts a PSC detection pulse Pe from a second PSC detection circuit 14 to be described later, so that the image data Dv stored in the buffer memory 11 is counted. To manage the number of frames. Then, when one frame or more of image data is accumulated in the buffer memory 11, as shown in FIG.
The frame synchronization pulse Pf is sent from the next stage (not shown) to the management circuit.
When supplied to the buffer 13, the read permission signal Pr is supplied from the management circuit 13 to the buffer memory 11 at the time of the frame synchronization pulse Pf. Therefore, as shown in FIG. 2D, reading of the image data Dv from the buffer memory 11 is started from the point of the frame synchronization pulse Pf. Then, the read image data Dv is supplied to the variable-length code decoding circuit 15, and a signal for permitting the start of decoding is supplied from the management circuit 13 to the decoding circuit 15, and the read image data Dv Dv is decoded into the original fixed-length image data, and the decoded image data is supplied to the next stage. At this time, the image data Dv read from the buffer memory 11 is supplied to the second PSC detection circuit 14, and the PSC of the read image data Dv is supplied as shown in FIG.
Each time, the detection pulse Pe is taken out, and this pulse Pe
Is supplied to the management circuit 13. Thus, the management circuit 13 manages the number of frames of the image data Dv stored in the buffer memory 11 by counting the pulses Pb and Pe. Note that the decoded image data from the decoding circuit 15 is converted into display image data by the frame memory when a predetermined process is performed in the subsequent circuits, and then the CRT is processed.
The image is supplied to the display and displayed. Further, in the above description, the management circuit 13
It can be constituted by a counter that counts up Pb and counts down the pulse Pe, and a logic circuit that takes the logic of the count output and the synchronization pulse Pf. Furthermore, when the received image data Dv is image data obtained by blocking the original image data and then performing variable-length coding, the image data from the decoding circuit is blocked, so this is used as the original image data. Should be decoded.

【The invention's effect】

Thus, according to the present invention, decoding of the variable-length encoded image data Dv can be performed. In this case, in particular, according to the present invention, the PSC detection circuit 12 is provided at the front and rear stages of the reception buffer memory 11. , 14 and their detection outputs Pb, Pe
Is processed by the management circuit 13 so that when one frame or more of the image data Dv is accumulated in the buffer memory 11, the image data Dv is read out in frame synchronization with the next stage and read out by the decoding circuit 15. Since the decoding is performed, the frame buffer memory 44 as shown in FIG. 4 is not required.

[Brief description of the drawings]

FIG. 1 is a system diagram showing one example of the present invention, FIG. 2 is a diagram showing the timing of the signals, and FIGS. 3 and 4 are system diagrams for explaining the present invention. 11; reception buffer memory 12; first PSC detection circuit 13; reception buffer frame management circuit 14; second PSC detection circuit 15; variable-length code decoding circuit

Claims (1)

(57) [Claims] 1. A decoding circuit for decoding original fixed-length image data from image data to which a code indicating a frame is added for each frame while being variable-length coded, A receiving buffer memory in which the image data of the above is written; a variable length code decoding circuit for decoding the image data read from the receiving buffer memory into the original fixed length image data; A first detection circuit for detecting a code indicating the frame from the image data; a second detection circuit for detecting a code indicating the frame from the image data read from the reception buffer memory; The detection output of the second detection circuit and the frame synchronization signal are supplied to control reading of the reception buffer memory. A reception buffer frame management circuit, wherein the reception buffer frame management circuit counts up one of the detection outputs of the first and second detection circuits and counts down the other, and the count result is: Image data which permits reading of the image data from the reception buffer memory in synchronization with the frame synchronization signal when the reception buffer frame memory indicates that there is one or more frames of the image data. Decoding circuit.