JPH098501A - High frequency switch - Google Patents

Abstract

PURPOSE: To realize the high frequency switch with high isolation and a low pass loss by connecting an inductor in parallel between a drain terminal and a source terminal of a field effect transistor (FET) so as to cancel the parasitic capacitance caused when the FET is nonconductive. CONSTITUTION: An inductor is connected in parallel between a drain terminal and a source terminal of a field effect transistor (FET) so as to cancel the parasitic capacitance caused when the FET is nonconductive. For example, an inductor L1(L2) is connected in parallel between a drain terminal and a source terminal of a FET2 (3) (each acting like a single pole double throw (SPDT) switch) through which a transmission (reception) signal passes to prevent increase in a passing loss and deterioration in the isolation due to parasitic capacitance. Although parasitic capacitance of FETs 1, 4 for grounding purpose causes increase in a passing loss at reception and transmission respectively, since the optimum gate width of the FETs 1, 4 is often narrower than the gate width of the FETs 2, 3, the parasitic capacitance caused when the FETs 1, 4 are nonconductive is negligibly small.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switch for switching between transmission and reception, which is used in a mobile communication device having both a transmission function and a reception function, and has a low passage loss and a high isolation characteristic. It realizes the high-frequency switch it has.

[0002]

2. Description of the Related Art SPDT (Single-Pole Double-Thro) for switching between transmission and reception using a compound semiconductor device whose main application is a cellular phone, a cordless phone, etc.
w) Many cases of switch development have been announced. Examples include "Small Resin Package High Frequency FET Switch" by Yoshikawa et al., 1993 IEICE Spring Conference, Lecture No. C-90. FIG. 2 shows this conventional SPDT switch. Each field effect transistor (hereinafter, referred to as "FET") forming the switch is a depletion type GaAs MESFET. The operation principle of the SPDT switch will be described with reference to FIG. The switch has three signal terminals and two control terminals VC1 and VC2. In the figure, the central signal terminal is connected to the antenna, the left signal terminal is connected to the receiver, and the right signal terminal is connected to the transmitter. The control bias is 0 complementary to the two control terminals VC1 and VC2.
V bias or negative bias V below the threshold voltage of FET
Apply con. When 0V is applied to VC1 and VconV is applied to VC2, FET2 and FET4 turn on, FET1 and FET3
Is turned off, the central signal terminal connected to the antenna and the left signal terminal connected to the receiver are connected, and the right signal terminal connected to the transmitter is grounded. Conversely, VC1
If VconV is added to V2 and 0V to VC2,
ET3 is turned on, FET2 and FET4 are turned off, the central signal terminal connected to the antenna and the right signal terminal connected to the transmitter are connected, and the left signal terminal connected to the receiver is grounded.

A small signal equivalent circuit of the FET is shown in FIG. The simplified equivalent circuit at the time of OFF can be represented by the parasitic capacitance between the drain and the source, and the equivalent circuit at the time of ON can be represented by the resistance between the drain and the source. Drain-source parasitic capacitance and O when OFF
The insertion loss of the switch is determined by the resistance between the drain and the source at the time of N. Drain when FET is ON-
In order to reduce the resistance value between the sources, it is necessary to widen the gate width of the FET, and widening the gate width increases the parasitic capacitance between the drain and the source in the OFF state. As described above, there is a trade-off relationship between the insertion loss at the time of ON and the isolation at the time of OFF with respect to the gate width of the FET.

FIG. 3B shows a small signal equivalent circuit of the SPDT switch when the antenna and the receiver are connected.

The FET2 through which the reception signal passes and the FET3 through which the transmission signal passes, have a wider gate width than the FET1 and FET4 in order to reduce the passage loss of each signal, and the resistance value between the drain and the source in the ON state. In many cases, the parasitic capacitance in the OFF state of FET2 and FET3 increases. At this time, in the receiving state in which 0V is applied to VC1 and VconV is applied to VC2, the large parasitic capacitance C3 of the FET3 on the transmission side causes the reception signal from the antenna to leak to the transmission side, increasing the transmission loss of the reception signal. . Further, the leakage of the transmission signal from the transmission side is transmitted through the parasitic capacitance C3, and the isolation characteristic deteriorates. In the transmission state, the passage loss of the transmission signal increases due to the influence of the large parasitic capacitance of FET2.

[0006]

SUMMARY OF THE INVENTION In the present invention, it is possible to realize an SPDT switch having low passage loss and high isolation by preventing an increase in passage loss and deterioration of isolation characteristics due to a parasitic capacitance in an OFF state of an FET. It is an issue.

[0007]

The above object is realized by connecting an inductor in parallel to an FET having a large gate width and a large parasitic capacitance when turned off to cancel the parasitic capacitance.

The above problem is that the inductor is connected in parallel between the drain terminal and the source terminal of the FET and the FET is turned off.
It is realized by canceling the parasitic capacitance at the time.

More specifically, one of a drain terminal or a source terminal is connected to the antenna and the other is connected to a transmitter, and a first field effect transistor is connected to the antenna. A second field effect transistor having the other connected to the receiver, and a third electric field having one of the drain terminal and the source terminal connected to the transmitter side terminal of the first field effect transistor and the other grounded An effect transistor, a fourth field effect transistor having one of a drain terminal and a source terminal connected to a receiver side terminal of the second field effect transistor and the other grounded, and a drain of the second FET. An SPDT switch is composed of a first inductor connected in parallel between the terminal and the source terminal. A second inductor connected in parallel between the drain terminal and the source terminal of the first field effect transistor, a third inductor connected in parallel between the drain terminal and the source terminal of the third field effect transistor, A fourth field effect transistor connected in parallel between the drain terminal and the source terminal of the fourth field effect transistor;
It also has an inductor. Further, a first capacitor connected in parallel between the drain terminal and the source terminal of the third field effect transistor, and a fourth capacitor connected in parallel between the drain terminal and the source terminal of the fourth field effect transistor. To provide.

Further, in the multi-stage SPDT switch, an input terminal connected to the transmitter, an input / output terminal connected to the antenna, an output terminal connected to the receiver, the input terminal and the input / output described above. M (m ≧ 1) FETs provided in series between the terminals, n (n ≧ 1) FETs provided in series between the output terminal and the input / output terminal, and the m FETs Of which F is directly connected to the input / output terminals
An SPDT switch is composed of a first inductor connected in parallel between the drain terminal and the source terminal of ET. The second inductor is also connected in parallel between the drain terminal and the source terminal of the field-effect transistor directly connected to the input / output terminal among the n field-effect transistors. Further, m + n inductors connected in parallel are provided between the drain terminal and the source terminal of each of the m + n field effect transistors.

Further, each of the inductors is formed of a spiral inductor formed on a semiconductor substrate on which each of the field effect transistors is integrated.

[0012]

FIG. 1 shows the structure of the basic circuit of the present invention in which an inductor is connected between the source electrode and the drain electrode of an FET. A signal leaking through the parasitic capacitances CDS, CGS, and CGD when turned off is suppressed by causing the parasitic capacitance to resonate with the inductor. At this time, the value of the inductor L is given by (Equation 1).

[0013]

[Equation 1]

Here, ^ indicates exponentiation. This inductor L
Is actually realized by a spiral inductor or the like in which wiring is spirally arranged on the IC.

FIG. 4 shows a circuit configuration of an SPDT switch to which the present invention is applied, and FIG. 5 shows a small signal equivalent circuit at the time of reception. The basic circuit shown in FIG.
Applied to 3. When receiving, FET1 is OFF, FET
2 is ON, FET3 is OFF, and FET4 is ON.

A simple equivalent circuit for both ON and OFF states of the FET can be represented by resistance and capacitance, respectively. FET3 parasitic capacitance C
3 and the inductor L2 resonate in parallel so that the parasitic capacitance C3
It is possible to prevent an increase in passage loss due to the noise, prevent deterioration of isolation, and block noise from the transmitter side during reception. During transmission, the parasitic capacitance when the FET2 is OFF causes an increase in transmission signal passage loss, so that the inductor L1 is connected in parallel with the FET2 to prevent an increase in transmission signal passage loss during transmission. The influence of the inductor L1 upon reception can be almost ignored because the FET2 is in the ON state and the source and drain are connected with an extremely low impedance R1.

[0017]

1 is a diagram showing a first embodiment of the present invention. In this embodiment, an inductor is connected between the drain electrode and the source electrode of the FET. An SPDT switch is configured by using the configuration of this embodiment as an element circuit. The capacitance C combined by the parasitic capacitances C _DS , C _GS , and C _GD is given by (Equation 2).

[0018]

[Equation 2]

In terms of direct current, the drain electrode and the source electrode are short-circuited by an inductor, but the inductor has a capacitance C
Resonates with and realizes high isolation characteristics when OFF. Since the source and drain are coupled with a low impedance when turned on, the presence of the inductor can be ignored. At this time, the value of the inductor L is given by (Equation 3).

[0020]

(Equation 3)

Here, ^ indicates exponentiation. This inductor L
Is actually realized by a spiral inductor or the like in which wiring is spirally arranged on an IC (Integrated Circuit).

FIG. 11 shows an FET and a spiral inductor realized on the IC. The same figure (a) is a top view (b)
Is a sectional view. The spiral inductor is formed by using the uppermost wiring layer, and the wiring is drawn outside from the center of the spiral inductor by a metal layer forming the gate of the FET. 1.9G, where mobile communication is widely used worldwide
Considering the application in the Hz band as an example, the size of the spiral inductor occupies almost the area of one FET as shown in FIG.

As described above, this embodiment can be easily implemented.

FIG. 4 is a diagram showing a second embodiment of the present invention. By connecting an inductor in parallel to the two FETs 2 and 3 through which a transmission signal or a reception signal of a transmission / reception symmetric SPDT switch passes, an increase in passage loss due to parasitic capacitance and an isolation deterioration are prevented. Can be done. The parasitic capacitances of the FETs 1 and 4 for grounding also increase the passage loss at the time of reception and at the time of transmission.
The optimum gate width of T1 and 4 is often narrower than the gate width of FETs 2 and 3, and the parasitic capacitance when OFF is small. A large inductor is required to obtain a small capacitance and parallel resonance, and connecting an inductor for parallel resonance to the FETs 1 and 4 causes an increase in chip area when integrated. Here, the inductors for the FETs 1 and 4 are positively omitted.

According to this embodiment, a SPDT switch with low loss and high isolation can be realized.

Here, the importance of the isolation characteristic will be described.

FIG. 12 shows the channel structure of the TDMA system with four receiving slots and four transmitting slots. In FIG. 12, reception slot first and fourth lines,
An example of using the first and fourth transmission slot lines is shown. When the receiving slot is active, only the receiver operates and the transmitter turns off to reduce power consumption. If the transmit slot is active, only the transmitter is active and the receiver is in the OFF state. Power on / off
If the ON / OFF operation is completed within the time set for switching between slots, the isolation characteristic is not required to be high. However, in reality, it often takes more than the set time to turn on and off. FIG. 12 shows the case where the rise time of the transmitter (from OFF to ON) is long and the ON operation starts in the receiving slot fourth line. In such a case, since the transmitter is powered on in the receiving state, the influence of thermal noise generated from the transmitter cannot be ignored. Therefore, high isolation characteristics are required, and the present invention is an effective means.

A prototype of the second embodiment of the present invention, 1.
The improvement of the isolation characteristic of 10 dB or more was realized at 9 GHz, and the effect of this example was confirmed.

FIG. 6 is a diagram showing a third embodiment of the present invention. It is an example in which the present invention is applied to a multi-stage SPDT switch. Only the FETs 21 and 31 in which the drain electrode or the source electrode is connected to the antenna are inductors L1,
By connecting L2 in parallel, it is possible to prevent an increase in passage loss due to connection of unused paths. In the present embodiment, the effect is increased with the minimum necessary inductor, paying particular attention to the factors that increase the passage loss. Here, a symmetrical SPDT switch is taken as an example, but it is also possible to apply it to an asymmetrical switch (n ≠ m) having a different number of stages.

FIG. 7 is a diagram showing a fourth embodiment of the present invention. Since the inductors are connected in parallel to all the FETs, the FET1, which is not taken as a countermeasure in the first embodiment,
The effect of the parasitic capacitance of No. 4 is suppressed, and a switch with less passage loss than that of the first embodiment is realized.

FIG. 8 is a diagram showing a fifth embodiment of the present invention. Although the fourth embodiment shown in FIG. 7 can realize low passage loss, it requires more and larger inductors. As described in the second embodiment, the FE for grounding
The gate widths of T1 and T4 are often smaller than those of the FETs 2 and 3. Therefore, the size of the inductor that resonates with the parasitic capacitance of the FETs 1 and 4 is larger than that of the inductors used in the FETs 2 and 3, and when the fourth embodiment is realized on the MMIC, the chip area is significantly increased. . In the present embodiment, the capacitance of the FETs 1 and 4 for grounding is connected in parallel with the inductor, thereby reducing the value of the inductor required for resonance when OFF.

Here, the description has been given by taking the symmetrical one-stage SPDT switch as an example, but the asymmetrical and multi-stage SPTs are used.
It is also applicable to the D switch.

FIG. 9 is a diagram showing a sixth embodiment of the present invention. An inductor is attached in parallel to all the FETs 21 to 2n and 31 to 3n through which the reception signal or the transmission signal of the multistage SPDT switch passes. Since the parasitic capacitances of all the FETs through which the reception signal or the transmission signal passes are canceled by the inductor, the isolation characteristic in the OFF state can be further improved in this embodiment.

FIG. 10 is a diagram showing a seventh embodiment of the present invention. Since the isolation characteristic is particularly strongly required for the signal from the transmission side during the reception mode operation, among the four FETs 1 to 4 constituting the SPDT switch, the inductor is connected in parallel only to the FET 3 that passes the transmission signal, The isolation characteristics are strengthened. By reducing the number of inductors to one, the chip area when integrated can be reduced.

[0035]

According to the present invention, the parasitic capacitance when the switch circuit composed of FETs is turned off is canceled by the inductor, and it is possible to realize a high-frequency switch with low passage loss and high isolation. Specifically, at least one of the FETs provided between the antenna and the transmitter
By connecting two inductors in parallel to each other, it is possible to suppress the leakage of the transmission signal from the transmitter at the time of reception and to strengthen the isolation characteristics, and at the same time, to prevent the leakage of the reception signal to the transmitter side. It is possible to suppress the congestion and reduce the passage loss of the received signal. In addition, by connecting an inductor in parallel to at least one of the FETs provided between the antenna and the receiver, the transmission signal is prevented from leaking to the receiver side during transmission, and the transmission loss of the transmission signal is reduced. can do. Furthermore, by providing a parallel resonant circuit composed of an inductor and a capacitance in each FET provided between the source terminal or drain terminal of the FET between the antenna and the transmitter or between the antenna and the receiver and the ground, it is possible It is possible to suppress the transmission signal or the reception signal from leaking to the ground and reduce the passage loss of each signal, and at the same time, to suppress the occupied area of the inductor at the time of integration and to make a maximization of the entire chip area.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a conventional SPDT switch.

FIG. 3 is a small signal equivalent circuit diagram of a FET and a conventional SPDT switch.

FIG. 4 is a diagram showing a second embodiment of the present invention.

FIG. 5 is a small signal equivalent circuit diagram of a second embodiment of the present invention.

FIG. 6 is a diagram showing a third embodiment of the present invention.

FIG. 7 is a diagram showing a fourth embodiment of the present invention.

FIG. 8 is a diagram showing a fifth embodiment of the present invention.

FIG. 9 is a diagram showing a sixth embodiment of the present invention.

FIG. 10 is a diagram showing a seventh embodiment of the present invention.

FIG. 11 is an implementation diagram on an IC of the first embodiment of the present invention.

FIG. 12 is a timing diagram of the TDMA method.

[Explanation of symbols]

FETs 1, 2, 3, 4, 1n, 2n, 3m, 4m ... Field effect transistors, VC1, VC2 ... Control bias terminals, L1, L2 ... Inductor, R1 ... ON resistance of FET1, C3 ... Parasitic capacitance when FET3 is OFF.

Claims (15)

[Claims] 1. An electronic circuit comprising an inductor connected in parallel between a drain terminal and a source terminal of a field effect transistor. 2. The electronic circuit according to claim 1, wherein an ON / OFF operation of the field effect transistor is performed by controlling a voltage applied to a gate terminal of the field effect transistor. 3. A first field effect transistor in which one of a drain terminal and a source terminal is connected to an antenna and the other is connected to a transmitter, and one of a drain terminal and a source terminal is connected to the antenna and the other is received. Second connected to the machine
Field effect transistor, and one of the drain terminal and the source terminal connected to the transmitter side terminal of the first field effect transistor, and the other grounded third field effect transistor, and the drain terminal or the source terminal A fourth field-effect transistor, one of which is connected to the receiver side terminal of the second field-effect transistor and the other of which is grounded, and at least one of the first to fourth field-effect transistors A high-frequency switch comprising at least one inductor connected in parallel between a drain terminal and a source terminal of an effect transistor. 4. A high-frequency switch comprising a first inductor connected in parallel between the drain terminal and the source terminal of the second field effect transistor. 5. The high frequency switch according to claim 4, further comprising a second inductor connected in parallel between the drain terminal and the source terminal of the first field effect transistor. 6. A third inductor connected in parallel between the drain terminal and the source terminal of the third field effect transistor, and a third inductor connected in parallel between the drain terminal and the source terminal of the fourth field effect transistor. The high frequency switch according to claim 5, further comprising an inductor of 4. 7. A first capacitor connected in parallel between a drain terminal and a source terminal of the third field effect transistor,
The high frequency switch according to claim 6, further comprising a fourth capacitor connected in parallel between the drain terminal and the source terminal of the fourth field effect transistor. 8. A first parallel resonance circuit including an inductor and a capacitor connected in parallel between the drain terminal and the source terminal of the third field effect transistor, and a drain terminal and a source of the fourth field effect transistor. The high frequency switch according to claim 5, further comprising a second parallel resonance circuit including an inductor and a capacitor connected in parallel between the terminals. 9. The first and fourth field effect transistors are controlled by controlling the voltage applied to the gate terminals of the first to fourth field effect transistors to perform ON / OFF operations of the field effect transistors. When the field effect transistor is in the ON state, the second and third field effect transistors are OF
In the F state, the high frequency transmission signal from the transmitter is transmitted through the antenna, and when the second and third field effect transistors are in the ON state, the first and fourth field effect transistors are in the OFF state. 9. The high frequency switch according to claim 3, wherein a high frequency reception signal received via said antenna is guided to said receiver. 10. An input terminal connected to a transmitter, an input / output terminal connected to an antenna, an output terminal connected to a receiver, and an output terminal connected in series between the input terminal and the input / output terminal. m (m ≧ 1) field effect transistors, n (n ≧ 1) field effect transistors provided in series between the output terminal and the input / output terminal, and the m field effect transistors A high-frequency switch comprising a first inductor connected in parallel between a drain terminal and a source terminal of a field effect transistor which is directly connected to the input / output terminal of the transistors. 11. A second inductor connected in parallel between a drain terminal and a source terminal of a field-effect transistor which is directly connected to the input / output terminal among the n field-effect transistors. Claim 10
The high frequency switch described. 12. An input terminal connected to a transmitter, an input / output terminal connected to an antenna, an output terminal connected to a receiver, and an output terminal connected in series between the input terminal and the input / output terminal. m (m ≧ 1) field effect transistors, n (n ≧ 1) field effect transistors provided in series between the output terminal and the input / output terminal, and the m field effect transistors It has m inductors connected in parallel between each drain terminal and source terminal of the transistor, and n inductors connected in parallel between each drain terminal and source terminal of the above n field effect transistors. A high-frequency switch characterized by that. 13. The ON / OFF operation of each field effect transistor is performed by controlling the voltage applied to the gate terminal of each of the m + n field effect transistors, and the m first and fourth field effect transistors are turned ON / OFF. When the field effect transistor is in the ON state, the n second and third field effect transistors are in the OFF state, and the high frequency transmission signal from the transmitter is transmitted through the antenna, and the n second field effect transistors are transmitted. And when the third field effect transistor is in the ON state, the above m
The high frequency reception signal received via the antenna is guided to the receiver by turning off the first and fourth field effect transistors.
The high frequency switch described in 2. 14. The high frequency wave according to claim 3, wherein each of the inductors is a spiral inductor formed on a semiconductor substrate on which each of the field effect transistors is integrated. switch. 15. A transmitter for converting transmission data into a high-frequency transmission signal, a receiver for converting a high-frequency reception signal into reception data, an antenna for both transmission and reception, and the transmitter and the antenna connected at the time of transmission. A mobile communication device having a transmission / reception changeover switch for connecting the antenna and the receiver at the time of reception, wherein the transmission / reception changeover switch is constituted by the high frequency switch according to any one of claims 3 to 14. Mobile communication device.