JPH07303001A - High frequency switch - Google Patents

Abstract

PURPOSE:To provide a switch by which transit loss due to parasitic capacitance is prevented from increased and isolation characteristic from being deteriorated and with low transit loss and high isolation by connecting an inductor in parallel with a FET with wide gate width and compensating the parasitic capacitance. CONSTITUTION:The transit loss due to the parasitic capacitance can be prevented from being increased by the parallel resonance of the parasitic capacitance of the FET3 and the inductor L2, and also, the isolation can be prevented from being deteriorated, and a noise from a transmission circuit side in reception can be blocked. In other words, since the parasitic capacitance when the FET2 is turned off causes the increment of the transit loss on a transmission side, the transit loss in a transmission mode can be prevented from being increased by connecting the inductor L1 in parallel with the FET2. In the reception, since the FET2 is turned on, the source of the FET can be connected to the drain with low impedance, which makes the inductor L1 give no influence on transit characteristic.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission / reception changeover switch for a mobile communication device, and to realize a high frequency switch having a low passage loss and a high isolation characteristic.

[0002]

2. Description of the Related Art Many cases have been announced in which an SPDT (Single-Pole Double-Throw) switch is used as a transmission / reception changeover switch for mobile communication. Examples include "Small Resin Package High Frequency FET Switch" by Yoshikawa et al., 1993 IEICE Spring Conference, Lecture No. C-90. FIG. 2 shows this conventional SPDT switch. In case of DFET, VC1 is 0V, VC2
Is -Vcon V, the reception state, VC1 is -Vcon
The transmission state is set when V and VC2 are set to 0V. Now, let us consider the pass characteristics of the reception state. FETs 2 and 3 that receive and transmit signals pass through to reduce the passage loss.
In many cases, the gate width is made wider than that of Nos. 1 and 4. At this time, in the reception state, the passage loss increases due to the influence of the parasitic capacitance of the FET 3 on the transmission side. Further, signal leakage from the transmission side is transmitted through the parasitic capacitance, degrading the isolation characteristic. In the transmitting state, the passage loss increases due to the influence of the parasitic capacitance of FET2.

[0003]

SUMMARY OF THE INVENTION An object of the present invention is to realize a switch with low passage loss and high isolation by preventing an increase in passage loss and deterioration of isolation characteristics due to the parasitic capacitance.

[0004]

The above object is realized by connecting an inductor in parallel with an FET having a wide gate width and canceling out parasitic capacitance.

[0005]

FIG. 3 shows the S to which the present invention is applied in the reception mode.
The equivalent circuit of a PDT switch is shown. F in this mode
ET1 is OFF, FET2 is ON, FET3 is OFF,
FET4 is in the ON state.

A simple equivalent circuit for both ON and OFF states of the FET can be represented by resistance and capacitance, respectively. FET3 parasitic capacitance C
3 and the inductor L2 resonate in parallel so that the parasitic capacitance C3
It is possible to prevent an increase in passage loss due to the above, prevent degradation of isolation, and block noise from the transmitting circuit side during reception. FE in transmission mode
Since the parasitic capacitance when T2 is OFF causes an increase in the transmission loss on the transmission side, the inductor L1 is connected in parallel with the FET2 to prevent an increase in the transmission loss in the transmission mode. At the time of reception, since the FET2 is in the ON state, the source and the drain are connected with an extremely low impedance R1, and the inductor L1 does not affect the pass characteristic.

Although the parasitic capacitance C1 of the FET1 also causes an increase in passage loss during reception, the optimum gate width of the FET1 is FET3.
Often narrower than the gate width. A large inductor is required to take parallel resonance with a small capacitance.
Connecting an inductor for parallel resonance to ET1 causes an increase in chip area when integrated. Here, the inductor for FET1 is positively omitted.

[0008]

EXAMPLE A first example of the present invention will be described with reference to FIG.
Transmit and receive symmetrical SPDT switch signals pass through 2
By connecting an inductor in parallel with one FET, it is possible to prevent an increase in passage loss due to parasitic capacitance and prevent deterioration of isolation. FET for ground
Although the parasitic capacitances of 1 and 4 also increase the passage loss during reception and transmission, the optimum gate widths of FETs 1 and 4 are
It is often narrower than the gate width of a few. A large inductor is required to obtain a small capacitance and parallel resonance, and connecting an inductor for parallel resonance to the FETs 1 and 4 causes an increase in chip area when integrated. Here, the inductors for the FETs 1 and 4 are positively omitted.

A second embodiment of the present invention will be described with reference to FIG. It is an example in which the present invention is applied to a multi-stage SPDT switch. By connecting the inductor in parallel only to the FET connected to the antenna terminal, it is possible to prevent an increase in passage loss due to connection of an unused path. In the present embodiment, the effect is increased with the minimum required inductor, paying particular attention to the factors that increase the passage loss. Here, a symmetrical SPDT switch is taken as an example, but it is also possible to apply it to an asymmetrical switch having a different number of stages.

A third embodiment of the present invention will be described with reference to FIG. By connecting the inductors in parallel to all the FETs, the effect of the parasitic capacitance of the FETs 1 and 4 which has not been dealt with in the first embodiment is suppressed, and a switch with less passage loss than in the first embodiment is realized. Is.

A fourth embodiment of the present invention will be described with reference to FIG. Although the third embodiment shown in FIG. 5 can realize a low passage loss, it requires more and larger inductors. As described in the first embodiment, the FET for grounding
Gate widths of 1 and 4 are often smaller than those of FETs 2 and 3. Therefore, the size of the inductor that resonates with the parasitic capacitances of the FETs 1 and 4 is larger than that of the inductors used in the FETs 2 and 3, and when this embodiment is realized on the MMIC, the chip area is significantly increased. In this embodiment, the value of the inductor necessary for resonance is reduced by connecting the capacitance in parallel with the grounding FET. Here, the symmetrical one-stage SPDT switch is described as an example, but it is also applicable to asymmetrical and multi-stage switches.

A fifth embodiment of the present invention will be described with reference to FIG. All FEs through which the signal of the multi-stage SPDT switch passes
An inductor is attached in parallel with T. Since the parasitic capacitances of all the FETs through which the signal passes are canceled by the inductor, in the present embodiment, it is possible to improve the isolation characteristic at the off time.

A sixth embodiment of the present invention will be described with reference to FIG. Since the isolation characteristic is particularly strongly required for the signal from the transmission side in the reception mode operation, S
Of the four FETs that make up the PDT switch, the inductor is connected in parallel only to the FET3 that passes the transmission signal,
The isolation characteristics are strengthened. By reducing the number of inductors to one, it is possible to reduce the chip area of the MMIC.

[0014]

The present invention realizes a switch with low passage loss and high isolation by canceling the parasitic capacitance of a switch circuit composed of an FET with an inductor. In addition, by limiting the number of inductors, we are trying to reduce the chip area during integration.

[Brief description of drawings]

FIG. 1 is a first embodiment of the present invention.

FIG. 2 is a conventional SPDT switch.

FIG. 3 is an equivalent circuit showing the operation of the present invention.

FIG. 4 is a second embodiment of the present invention.

FIG. 5 is a third embodiment of the present invention.

FIG. 6 is a fourth embodiment of the present invention.

FIG. 7 is a fifth embodiment of the present invention.

FIG. 8 is a sixth embodiment of the present invention.

[Explanation of symbols]

FETs 1, 2, 3, 4, 1n, 2n, 3m, 4m ... Field effect transistors, VC1, VC2 ... Control bias terminals, L1, L2 ... Inductor, R1 ... ON resistance of FET1, C3 ... Parasitic capacitance when FET3 is OFF.

Claims (10)

[Claims] 1. In a switch circuit having a plurality of input / output terminals composed of a plurality of FETs, parallel to at least one FET of FET transistors which is a path from a first input / output terminal to another input / output terminal. A high-frequency switch characterized in that an inductor element is connected to the. 2. The switch circuit according to claim 1, which is composed of a plurality of FETs and an inductor, wherein the inductor is composed of a spiral inductor on a semiconductor crystal, and all elements composing the switch are the same crystal substrate. A high-frequency switch circuit characterized by being integrated on top. 3. A high frequency switch comprising a plurality of FETs and an inductor, wherein the inductors are connected in parallel with all the FET elements in the switch circuit according to claim 1. circuit. 4. The switch circuit according to claim 1, which is composed of a plurality of FETs and an inductor, wherein a parallel resonant circuit composed of an inductor and a capacitor is connected in parallel with at least one FET. High frequency switch circuit. 5. A first electrode (source or drain) of the first FET is grounded, a second electrode (drain or source) of the same FET is connected to a first input / output terminal, and a second FE is connected.
The first electrode (source or drain) of T is connected to the first input / output terminal, and the second electrode (drain or source) of the second FET is connected to the second input / output terminal. FE
The high frequency switch circuit according to claim 1, further comprising an inductor connected between the source and the drain of T. 6. A switch circuit according to claim 5, wherein two switch circuits are used, a first input / output terminal of the first switch circuit is a first input / output terminal, and a first switch circuit of the second switch circuit. And a second input / output terminal of each of the first and second switch circuits is connected to form a third input / output terminal. The high frequency switch circuit according to the item. 7. A switch circuit according to claim 6, wherein one or more switch circuits according to claim 5 are cascade-connected between the first terminal and the third terminal, and a second circuit is provided. Claim 5 between the terminal and the third terminal
The high frequency switch circuit according to claim 1, wherein one or more switch circuits according to claim 1 are cascade-connected. 8. A switch circuit according to claim 6, wherein one or more switch circuits according to claim 5 are cascade-connected between the first terminal and the third terminal, and a second circuit is provided. Claim 5 between the terminal and the third terminal
One or more switch circuits described in claim 1 are cascade-connected, and the inductors included in the circuits other than the two switch circuits described in claim 5 that are directly connected to the third terminal are removed. The high frequency switch circuit according to claim 1. 9. A first electrode (source or drain) of the first FET is grounded, a second electrode (drain or source) of the same FET is connected to a first input / output terminal, and a second FE is connected.
The first electrode (source or drain) of T is connected to the first input / output terminal, and the second electrode (drain or source) of the second FET is connected to the second input / output terminal. FE
Connect an inductor between the source and drain of T
The high-frequency switch circuit according to claim 1, wherein a parallel resonant circuit is connected between the source and the drain of the FET. 10. The high frequency switch circuit according to claim 1, wherein the inductor of the first switch circuit is removed from the switch circuit according to claim 6.