JPH098438A - Wire bonding terminal, manufacture thereof and manufacture of semiconductor mounting substrate using that wire bonding terminal - Google Patents
Wire bonding terminal, manufacture thereof and manufacture of semiconductor mounting substrate using that wire bonding terminalInfo
- Publication number
- JPH098438A JPH098438A JP15313995A JP15313995A JPH098438A JP H098438 A JPH098438 A JP H098438A JP 15313995 A JP15313995 A JP 15313995A JP 15313995 A JP15313995 A JP 15313995A JP H098438 A JPH098438 A JP H098438A
- Authority
- JP
- Japan
- Prior art keywords
- plating film
- wire bonding
- electroless
- terminal
- minutes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
- H01L2224/10125—Reinforcing structures
- H01L2224/10126—Bump collar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemically Coating (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ワイヤボンディング用
端子とその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wire bonding terminal and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】プリント配線板は、近年、高密度化が進
んでおり、配線板に直接半導体チップを搭載する半導体
搭載用パッケージであるチップオンボード（以下、ＣＯ
Ｂという。）やマルチチップモジュール（以下、ＭＣＭ
という。）等の需要が伸びている。これらのパッケージ
と半導体チップとの電気的接続は、通常、ワイヤボンデ
ィングが用いられる。このパッケージにおけるワイヤボ
ンディング用端子としては、例えば、社団法人プリント
回路学会誌「サーキットテクノロジー」（１９９３年Ｖ
ｏｌ．８ Ｎｏ．５ ３６８〜３７２頁）に掲載されて
いるように、端子部分の銅箔表面に、ニッケルめっき皮
膜／置換金めっき皮膜／無電解金めっき皮膜を形成する
ことが知られている。また、特開平５−５５７２７号公
報には、端子部分の回路銅の表面に、ニッケルめっき皮
膜／パラジウムめっき皮膜を形成することが記載されて
いる。2. Description of the Related Art In recent years, the density of printed wiring boards has increased, and chip-on-board (hereinafter referred to as CO
It is called B. ) And multi-chip module (hereinafter MCM
Say. ) Is increasing. Wire bonding is generally used for electrical connection between these packages and the semiconductor chip. Examples of wire bonding terminals in this package include, for example, "Circuit Technology" of the Japan Printed Circuit Society (1993 V
ol. 8 No. 5 368-372), it is known to form a nickel plating film / a displacement gold plating film / an electroless gold plating film on the surface of the copper foil of the terminal portion. Further, JP-A-5-55727 describes that a nickel plating film / palladium plating film is formed on the surface of the circuit copper in the terminal portion.
【０００３】また、配線板の端部にコネクタへ挿入する
端子部として、金めっきを行なうことは、古くから知ら
れており、例えば、特開平１−１８０９８５号公報に
は、銅箔の表面に、ニッケルめっき皮膜／パラジウムの
めっき核の形成／無電解金めっき皮膜を形成することが
記載され、特開平５−３２７１８７号公報には、銅箔の
表面に、パラジウムめっき皮膜／金めっき皮膜あるいは
パラジウムめっき皮膜を形成することが記載され、特開
平６−２２８７６２号公報には、銅箔の表面に、ニッケ
ルめっき皮膜／パラジウムストライクめっき皮膜／置換
金めっき皮膜を形成することが記載されている。It has long been known to perform gold plating as a terminal portion to be inserted into a connector at an end portion of a wiring board. For example, in Japanese Patent Laid-Open No. 1-180985, the surface of a copper foil is formed. , Nickel plating film / formation of palladium plating nucleus / formation of electroless gold plating film. JP-A-5-327187 discloses a palladium plating film / gold plating film or palladium on the surface of a copper foil. It is described that a plating film is formed, and JP-A-6-228762 describes that a nickel plating film / palladium strike plating film / displacement gold plating film is formed on the surface of a copper foil.
【０００４】[0004]
【発明が解決しようとする課題】ところで、上記した従
来の構造や方法においては、めっきを行なった後の加熱
処理によって、ワイヤボンディングの成功率が著しく低
下するという課題がある。このような加熱処理とは、例
えば、めっきを行なった後に、水分を除去するために乾
燥するときに加わる熱がある。By the way, in the above-mentioned conventional structure and method, there is a problem that the success rate of wire bonding is remarkably reduced by the heat treatment after plating. Such heat treatment includes, for example, heat applied during drying for removing moisture after performing plating.
【０００５】本発明は、加熱処理を行なってもワイヤボ
ンディングの成功を妨げない、ワイヤボンディング用端
子とその製造方法並びにそのワイヤボンディング端子を
用いた半導体搭載用基板の製造方法を提供することを目
的とする。It is an object of the present invention to provide a wire bonding terminal, a method for manufacturing the wire bonding terminal, and a method for manufacturing a semiconductor mounting substrate using the wire bonding terminal, which does not prevent successful wire bonding even if heat treatment is performed. And
【０００６】[0006]
【課題を解決するための手段】本発明のワイヤボンディ
ング用端子は、端子形状の銅の表面に、無電解ニッケル
めっき皮膜、置換パラジウムめっき皮膜または無電解パ
ラジウムめっき皮膜、置換金めっき皮膜、無電解金めっ
き皮膜を、この順序に形成したことを特徴とする。The terminal for wire bonding of the present invention comprises an electroless nickel plating film, a substitution palladium plating film or an electroless palladium plating film, a substitution gold plating film, and an electroless film on the surface of a terminal-shaped copper. The gold plating film is formed in this order.
【０００７】無電解ニッケルめっき皮膜の厚さは、１μ
ｍ以上であることが好ましく、１μｍ未満であると、加
熱処理後のワイヤボンディングの成功率が低下する。ま
た、上限は、ほとんど経済的な理由によってのみ制限さ
れ、通常は、１５μｍまでとするのが好ましい。The thickness of the electroless nickel plating film is 1 μm
It is preferably m or more, and when it is less than 1 μm, the success rate of wire bonding after heat treatment is reduced. Also, the upper limit is limited only for most economical reasons, and normally, it is preferable to set it to 15 μm.
【０００８】置換パラジウムめっき皮膜または無電解パ
ラジウムめっき皮膜の厚さは、０．１μｍ以上であるこ
とが好ましく、０．１μｍ未満であると、加熱処理後の
ワイヤボンディングの成功率が低下する。また、上限
は、ほとんど経済的な理由によってのみ制限され、通常
は、２μｍまでとするのが好ましい。The thickness of the substituted palladium plating film or the electroless palladium plating film is preferably 0.1 μm or more, and when it is less than 0.1 μm, the success rate of wire bonding after the heat treatment decreases. Further, the upper limit is limited only for almost economical reasons, and it is usually preferable to set it to 2 μm.
【０００９】置換金めっき皮膜と無電解金めっき皮膜の
厚さの和は、０．０４μｍ以上であることが好ましく、
０．０４μｍ未満であると、加熱処理後のワイヤボンデ
ィングの成功率が低下するまた、上限は、ほとんど経済
的な理由によってのみ制限され、通常は、２μｍまでと
するのが好ましい。The sum of the thicknesses of the displacement gold plating film and the electroless gold plating film is preferably 0.04 μm or more,
If it is less than 0.04 μm, the success rate of wire bonding after heat treatment is lowered, and the upper limit is limited only for almost economical reasons, and usually it is preferably 2 μm.
【００１０】このようなワイヤボンディング用端子を製
造するには、端子形状の銅の表面に、無電解ニッケルめ
っき皮膜を形成し、その表面に置換パラジウムめっき皮
膜または無電解パラジウムめっき皮膜を形成し、その表
面に置換金めっき皮膜を形成し、その表面に無電解金め
っき皮膜を形成することによって、得られる。To manufacture such a terminal for wire bonding, an electroless nickel plating film is formed on the surface of the terminal-shaped copper, and a substitution palladium plating film or an electroless palladium plating film is formed on the surface, It is obtained by forming a displacement gold plating film on the surface and forming an electroless gold plating film on the surface.
【００１１】このようなワイヤボンディング用端子を有
する半導体搭載用基板としては、ＣＯＢ，ＭＣＭの他、
ピングリッドアレイ（以下、ＰＧＡという。）、ボール
グリッドアレイ（以下、ＢＧＡという。）等、どのよう
な基板に用いることもでき、絶縁基材としては、セラミ
クス等無機質基板や、フェノール樹脂、エポキシ樹脂、
ポリイミド樹脂等の有機質基板等、どのような材料でも
用いることができる。As a semiconductor mounting substrate having such wire bonding terminals, in addition to COB and MCM,
It can be used for any substrate such as a pin grid array (hereinafter referred to as PGA) and a ball grid array (hereinafter referred to as BGA). As an insulating base material, an inorganic substrate such as ceramics, a phenol resin or an epoxy resin is used. ,
Any material such as an organic substrate such as a polyimide resin can be used.
【００１２】[0012]
実施例１ 銅張り積層板であるＭＣＬ−Ｅ−６７（日立化成工業株
式会社製、商品名）に孔をあけ、スルーホールめっきを
行ない、エッチングレジストを形成し、不要な銅をエッ
チング除去し、不要な箇所にめっきを析出させないよう
に、ソルダーレジストを兼ねためっきレジストを形成し
た後、以下の工程によりワイヤボンディング端子を形成
した。 工程１：（前処理） 上記基板を、脱脂液Ｚ−２００（株式会社ワールドメタ
ル製、商品名）に、５０℃で３分間浸漬し、２分間水洗
し、その後、１００ｇ／ｌの過硫酸アンモニウム溶液に
１分間浸漬し、２分間水洗し、１０％の硫酸で１分間浸
漬し、２分間水洗する。 工程２：（活性化） 続いて、めっき活性化処理液であるＳＡ−１００（日立
化成工業株式会社製、商品名）に、２５℃で５分間、浸
漬処理し、２分間水洗する。 工程３：（無電解ニッケルめっき） 続いて、無電解ニッケルめっき液であるＮＩＰＳ−１０
０（日立化成工業株式会社製、商品名）に、８５℃で２
０分間、浸漬処理する。 工程４：（無電解パラジウムめっき） 続いて、無電解パラジウムめっき液であるＡＰＰ（石原
薬品工業株式会社製、商品名）に、５０℃で２０分間、
浸漬処理する。 工程５：（置換金めっき） 続いて、置換金めっき液であるＨＧＳ−１００（日立化
成工業株式会社製、商品名）に、８５℃で１０分間、浸
漬処理する。 工程６：（無電解金めっき） 続いて、無電解金めっき液であるＨＧＳ−２０００（日
立化成工業株式会社製、商品名）に、６５℃で４０分
間、浸漬処理する。Example 1 A hole was formed in MCL-E-67 (Hitachi Chemical Co., Ltd., trade name), which is a copper-clad laminate, through-hole plating was performed, an etching resist was formed, and unnecessary copper was removed by etching. After forming a plating resist which also serves as a solder resist so as to prevent the plating from being deposited on an unnecessary portion, a wire bonding terminal was formed by the following steps. Step 1: (Pretreatment) The above substrate was immersed in a degreasing solution Z-200 (manufactured by World Metal Co., Ltd., trade name) at 50 ° C for 3 minutes, washed with water for 2 minutes, and then a 100 g / l ammonium persulfate solution. 1 minute, then rinsed with water for 2 minutes, dipped in 10% sulfuric acid for 1 minute, and rinsed with water for 2 minutes. Step 2: (Activation) Subsequently, a plating activation treatment liquid SA-100 (manufactured by Hitachi Chemical Co., Ltd., trade name) is immersed at 25 ° C. for 5 minutes and washed with water for 2 minutes. Step 3: (Electroless Nickel Plating) Subsequently, NIPS-10 which is an electroless nickel plating solution
0 (made by Hitachi Chemical Co., Ltd., trade name) at 2 ° C at 85 ° C
Immersion treatment for 0 minutes. Step 4: (Electroless Palladium Plating) Subsequently, the electroless palladium plating solution APP (trade name, manufactured by Ishihara Yakuhin Kogyo Co., Ltd.) was applied at 50 ° C. for 20 minutes.
Immerse. Step 5: (Substitution Gold Plating) Subsequently, immersion treatment is performed at 85 ° C. for 10 minutes in HGS-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.) which is a substitution gold plating solution. Step 6: (Electroless Gold Plating) Subsequently, an electroless gold plating solution HGS-2000 (manufactured by Hitachi Chemical Co., Ltd., trade name) is immersed at 65 ° C. for 40 minutes.
【００１３】実施例２ 銅張り積層板であるＭＣＬ−Ｅ−６７（日立化成工業株
式会社製、商品名）に孔をあけ、スルーホールめっきを
行ない、エッチングレジストを形成し、不要な銅をエッ
チング除去し、不要な箇所にめっきを析出させないよう
に、ソルダーレジストを兼ねためっきレジストを形成し
た後、以下の工程によりワイヤボンディング端子を形成
した。 工程１：（前処理） 上記基板を、脱脂液Ｚ−２００（株式会社ワールドメタ
ル製、商品名）に、５０℃で３分間浸漬し、２分間水洗
し、その後、１００ｇ／ｌの過硫酸アンモニウム溶液に
１分間浸漬し、２分間水洗し、１０％の硫酸で１分間浸
漬し、２分間水洗する。 工程２：（活性化） 続いて、めっき活性化処理液であるＳＡ−１００（日立
化成工業株式会社製、商品名）に、２５℃で５分間、浸
漬処理し、２分間水洗する。 工程３：（無電解ニッケルめっき） 続いて、無電解ニッケルめっき液であるＮＩＰＳ−１０
０（日立化成工業株式会社製、商品名）に、８５℃で２
０分間、浸漬処理する。 工程４：（置換パラジウムめっき） 続いて、置換パラジウムめっき液であるＭＣＡ（株式会
社ワールドメタル製、商品名）に、２５℃で２０分間、
浸漬処理する。 工程５：（置換金めっき） 続いて、置換金めっき液であるＨＧＳ−１００（日立化
成工業株式会社製、商品名）に、８５℃で１０分間、浸
漬処理する。 工程６：（無電解金めっき） 続いて、無電解金めっき液であるＨＧＳ−２０００（日
立化成工業株式会社製、商品名）に、６５℃で４０分
間、浸漬処理する。Example 2 MCL-E-67 (Hitachi Chemical Co., Ltd., trade name), which is a copper-clad laminate, was perforated, through-hole plated, an etching resist was formed, and unnecessary copper was etched. After removing and forming a plating resist which also serves as a solder resist so as to prevent plating from being deposited on unnecessary portions, wire bonding terminals were formed by the following steps. Step 1: (Pretreatment) The above substrate was immersed in a degreasing solution Z-200 (manufactured by World Metal Co., Ltd., trade name) at 50 ° C for 3 minutes, washed with water for 2 minutes, and then a 100 g / l ammonium persulfate solution. 1 minute, then rinsed with water for 2 minutes, dipped in 10% sulfuric acid for 1 minute, and rinsed with water for 2 minutes. Step 2: (Activation) Subsequently, a plating activation treatment liquid SA-100 (manufactured by Hitachi Chemical Co., Ltd., trade name) is immersed at 25 ° C. for 5 minutes and washed with water for 2 minutes. Step 3: (Electroless Nickel Plating) Subsequently, NIPS-10 which is an electroless nickel plating solution
0 (made by Hitachi Chemical Co., Ltd., trade name) at 2 ° C at 85 ° C
Immersion treatment for 0 minutes. Step 4: (Substitutional Palladium Plating) Subsequently, a substitutional palladium plating solution, MCA (manufactured by World Metal Co., Ltd., trade name), was added at 25 ° C. for 20 minutes.
Immerse. Step 5: (Substitution Gold Plating) Subsequently, immersion treatment is performed at 85 ° C. for 10 minutes in HGS-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.) which is a substitution gold plating solution. Step 6: (Electroless Gold Plating) Subsequently, an electroless gold plating solution HGS-2000 (manufactured by Hitachi Chemical Co., Ltd., trade name) is immersed at 65 ° C. for 40 minutes.
【００１４】比較例１ 銅張り積層板であるＭＣＬ−Ｅ−６７（日立化成工業株
式会社製、商品名）に孔をあけ、スルーホールめっきを
行ない、エッチングレジストを形成し、不要な銅をエッ
チング除去し、不要な箇所にめっきを析出させないよう
に、ソルダーレジストを兼ねためっきレジストを形成し
た後、以下の工程によりワイヤボンディング端子を形成
した。 工程１：（前処理） 上記基板を、脱脂液Ｚ−２００（株式会社ワールドメタ
ル製、商品名）に、５０℃で３分間浸漬し、２分間水洗
し、その後、１００ｇ／ｌの過硫酸アンモニウム溶液に
１分間浸漬し、２分間水洗し、１０％の硫酸で１分間浸
漬し、２分間水洗する。 工程２：（活性化） 続いて、めっき活性化処理液であるＳＡ−１００（日立
化成工業株式会社製、商品名）に、２５℃で５分間、浸
漬処理し、２分間水洗する。 工程３：（無電解ニッケルめっき） 続いて、無電解ニッケルめっき液であるＮＩＰＳ−１０
０（日立化成工業株式会社製、商品名）に、８５℃で２
０分間、浸漬処理する。 工程４：（置換金めっき） 続いて、置換金めっき液であるＨＧＳ−１００（日立化
成工業株式会社製、商品名）に、８５℃で１０分間、浸
漬処理する。 工程５：（無電解金めっき） 続いて、無電解金めっき液であるＨＧＳ−２０００（日
立化成工業株式会社製、商品名）に、６５℃で４０分
間、浸漬処理する。Comparative Example 1 MCL-E-67 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a copper-clad laminate, is perforated, through-hole plated, an etching resist is formed, and unnecessary copper is etched. After removing and forming a plating resist which also serves as a solder resist so as to prevent plating from being deposited on unnecessary portions, wire bonding terminals were formed by the following steps. Step 1: (Pretreatment) The above substrate was immersed in a degreasing solution Z-200 (manufactured by World Metal Co., Ltd., trade name) at 50 ° C for 3 minutes, washed with water for 2 minutes, and then a 100 g / l ammonium persulfate solution. 1 minute, then rinsed with water for 2 minutes, dipped in 10% sulfuric acid for 1 minute, and rinsed with water for 2 minutes. Step 2: (Activation) Subsequently, a plating activation treatment liquid SA-100 (manufactured by Hitachi Chemical Co., Ltd., trade name) is immersed at 25 ° C. for 5 minutes and washed with water for 2 minutes. Step 3: (Electroless Nickel Plating) Subsequently, NIPS-10 which is an electroless nickel plating solution
0 (made by Hitachi Chemical Co., Ltd., trade name) at 2 ° C at 85 ° C
Immersion treatment for 0 minutes. Step 4: (Substitution gold plating) Then, immersion treatment is performed at 85 ° C for 10 minutes in HGS-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.) which is a substitution gold plating solution. Step 5: (Electroless Gold Plating) Subsequently, an electroless gold plating solution HGS-2000 (manufactured by Hitachi Chemical Co., Ltd., trade name) is immersed at 65 ° C. for 40 minutes.
【００１５】比較例２ 銅張り積層板であるＭＣＬ−Ｅ−６７（日立化成工業株
式会社製、商品名）に孔をあけ、スルーホールめっきを
行ない、エッチングレジストを形成し、不要な銅をエッ
チング除去し、不要な箇所にめっきを析出させないよう
に、ソルダーレジストを兼ねためっきレジストを形成し
た後、以下の工程によりワイヤボンディング端子を形成
した。 工程１：（前処理） 上記基板を、脱脂液Ｚ−２００（株式会社ワールドメタ
ル製、商品名）に、５０℃で３分間浸漬し、２分間水洗
し、その後、１００ｇ／ｌの過硫酸アンモニウム溶液に
１分間浸漬し、２分間水洗し、１０％の硫酸で１分間浸
漬し、２分間水洗する。 工程２：（活性化） 続いて、めっき活性化処理液であるＳＡ−１００（日立
化成工業株式会社製、商品名）に、２５℃で５分間、浸
漬処理し、２分間水洗する。 工程３：（無電解ニッケルめっき） 続いて、無電解ニッケルめっき液であるＮＩＰＳ−１０
０（日立化成工業株式会社製、商品名）に、８５℃で２
０分間、浸漬処理する。 工程４：（無電解パラジウムめっき） 続いて、無電解パラジウムめっき液であるＡＰＰ（石原
薬品株式会社製、商品名）に、５０℃で２０分間、浸漬
処理する。Comparative Example 2 MCL-E-67 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a copper-clad laminate, is perforated, through-hole plated, etching resist is formed, and unnecessary copper is etched. After removing and forming a plating resist which also serves as a solder resist so as to prevent plating from being deposited on unnecessary portions, wire bonding terminals were formed by the following steps. Step 1: (Pretreatment) The above substrate was immersed in a degreasing solution Z-200 (manufactured by World Metal Co., Ltd., trade name) at 50 ° C for 3 minutes, washed with water for 2 minutes, and then a 100 g / l ammonium persulfate solution. 1 minute, then rinsed with water for 2 minutes, dipped in 10% sulfuric acid for 1 minute, and rinsed with water for 2 minutes. Step 2: (Activation) Subsequently, a plating activation treatment liquid SA-100 (manufactured by Hitachi Chemical Co., Ltd., trade name) is immersed at 25 ° C. for 5 minutes and washed with water for 2 minutes. Step 3: (Electroless Nickel Plating) Subsequently, NIPS-10 which is an electroless nickel plating solution
0 (made by Hitachi Chemical Co., Ltd., trade name) at 2 ° C at 85 ° C
Immersion treatment for 0 minutes. Step 4: (Electroless Palladium Plating) Subsequently, an electroless palladium plating solution, APP (trade name, manufactured by Ishihara Chemical Co., Ltd.), is immersed at 50 ° C. for 20 minutes.
【００１６】比較例３ 銅張り積層板であるＭＣＬ−Ｅ−６７（日立化成工業株
式会社製、商品名）に孔をあけ、スルーホールめっきを
行ない、エッチングレジストを形成し、不要な銅をエッ
チング除去し、不要な箇所にめっきを析出させないよう
に、ソルダーレジストを兼ねためっきレジストを形成し
た後、以下の工程によりワイヤボンディング端子を形成
した。 工程１：（前処理） 上記基板を、脱脂液Ｚ−２００（株式会社ワールドメタ
ル製、商品名）に、５０℃で３分間浸漬し、２分間水洗
し、その後、１００ｇ／ｌの過硫酸アンモニウム溶液に
１分間浸漬し、２分間水洗し、１０％の硫酸で１分間浸
漬し、２分間水洗する。 工程２：（活性化） 続いて、めっき活性化処理液であるＳＡ−１００（日立
化成工業株式会社製、商品名）に、２５℃で５分間、浸
漬処理し、２分間水洗する。 工程３：（無電解ニッケルめっき） 続いて、無電解ニッケルめっき液であるＮＩＰＳ−１０
０（日立化成工業株式会社製、商品名）に、８５℃で２
０分間、浸漬処理する。 工程４：（無電解パラジウムめっき） 続いて、無電解パラジウムめっき液であるＡＰＰ（石原
薬品株式会社製、商品名）に、５０℃で２０分間、浸漬
処理する。 工程５：（置換金めっき） 続いて、置換金めっき液であるＨＧＳ−１００（日立化
成工業株式会社製、商品名）に、８５℃で１０分間、浸
漬処理する。Comparative Example 3 A copper-clad laminate MCL-E-67 (trade name, manufactured by Hitachi Chemical Co., Ltd.) was perforated, plated with through holes to form an etching resist, and unnecessary copper was etched. After removing and forming a plating resist which also serves as a solder resist so as to prevent plating from being deposited on unnecessary portions, wire bonding terminals were formed by the following steps. Step 1: (Pretreatment) The above substrate was immersed in a degreasing solution Z-200 (manufactured by World Metal Co., Ltd., trade name) at 50 ° C for 3 minutes, washed with water for 2 minutes, and then a 100 g / l ammonium persulfate solution. 1 minute, then rinsed with water for 2 minutes, dipped in 10% sulfuric acid for 1 minute, and rinsed with water for 2 minutes. Step 2: (Activation) Subsequently, a plating activation treatment liquid SA-100 (manufactured by Hitachi Chemical Co., Ltd., trade name) is immersed at 25 ° C. for 5 minutes and washed with water for 2 minutes. Step 3: (Electroless Nickel Plating) Subsequently, NIPS-10 which is an electroless nickel plating solution
0 (made by Hitachi Chemical Co., Ltd., trade name) at 2 ° C at 85 ° C
Immersion treatment for 0 minutes. Step 4: (Electroless Palladium Plating) Subsequently, an electroless palladium plating solution, APP (trade name, manufactured by Ishihara Chemical Co., Ltd.), is immersed at 50 ° C. for 20 minutes. Step 5: (Substitution Gold Plating) Subsequently, immersion treatment is performed at 85 ° C. for 10 minutes in HGS-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.) which is a substitution gold plating solution.
【００１７】比較例４ 銅張り積層板であるＭＣＬ−Ｅ−６７（日立化成工業株
式会社製、商品名）に孔をあけ、スルーホールめっきを
行ない、エッチングレジストを形成し、不要な銅をエッ
チング除去し、不要な箇所にめっきを析出させないよう
に、ソルダーレジストを兼ねためっきレジストを形成し
た後、以下の工程によりワイヤボンディング端子を形成
した。 工程１：（前処理） 上記基板を、脱脂液Ｚ−２００（株式会社ワールドメタ
ル製、商品名）に、５０℃で３分間浸漬し、２分間水洗
し、その後、１００ｇ／ｌの過硫酸アンモニウム溶液に
１分間浸漬し、２分間水洗し、１０％の硫酸で１分間浸
漬し、２分間水洗する。 工程２：（活性化） 続いて、めっき活性化処理液であるＳＡ−１００（日立
化成工業株式会社製、商品名）に、２５℃で５分間、浸
漬処理し、２分間水洗する。 工程３：（無電解パラジウムめっき） 続いて、無電解パラジウムめっき液であるＡＰＰ（石原
薬品株式会社製、商品名）に、５０℃で２０分間、浸漬
処理する。 工程４：（置換金めっき） 続いて、置換金めっき液であるＨＧＳ−１００（日立化
成工業株式会社製、商品名）に、８５℃で１０分間、浸
漬処理する。 工程５：（無電解金めっき） 続いて、無電解金めっき液であるＨＧＳ−２０００（日
立化成工業株式会社製、商品名）に、６５℃で４０分
間、浸漬処理する。Comparative Example 4 Copper-clad laminate MCL-E-67 (trade name, manufactured by Hitachi Chemical Co., Ltd.) was perforated, through-hole plated, etching resist was formed, and unnecessary copper was etched. After removing and forming a plating resist which also serves as a solder resist so as to prevent plating from being deposited on unnecessary portions, wire bonding terminals were formed by the following steps. Step 1: (Pretreatment) The above substrate was immersed in a degreasing solution Z-200 (manufactured by World Metal Co., Ltd., trade name) at 50 ° C for 3 minutes, washed with water for 2 minutes, and then a 100 g / l ammonium persulfate solution. 1 minute, then rinsed with water for 2 minutes, dipped in 10% sulfuric acid for 1 minute, and rinsed with water for 2 minutes. Step 2: (Activation) Subsequently, a plating activation treatment liquid SA-100 (manufactured by Hitachi Chemical Co., Ltd., trade name) is immersed at 25 ° C. for 5 minutes and washed with water for 2 minutes. Step 3: (Electroless Palladium Plating) Subsequently, an electroless palladium plating solution, APP (trade name, manufactured by Ishihara Chemical Co., Ltd.), is immersed at 50 ° C. for 20 minutes. Step 4: (Substitution gold plating) Then, immersion treatment is performed at 85 ° C for 10 minutes in HGS-100 (trade name, manufactured by Hitachi Chemical Co., Ltd.) which is a substitution gold plating solution. Step 5: (Electroless Gold Plating) Subsequently, an electroless gold plating solution HGS-2000 (manufactured by Hitachi Chemical Co., Ltd., trade name) is immersed at 65 ° C. for 40 minutes.
【００１８】以上のようにして作成した配線板を、その
ままの状態のものと、１８０℃で２時間熱処理したもの
の両方に、ワイヤボンディングを行なった。このとき
に、１つの配線板に行なうワイヤボンディングの数を１
００本とし、ワイヤボンディングに成功したものの数を
付着率で表す。熱処理をしないものは、実施例１、２、
比較例１では、付着率は１００％であり、密着強度は９
〜１３ｇであったが、比較例２、３、４では付着しない
ものが発生し、密着強度も０〜１０ｇとばらついた。熱
処理を行なったものは、実施例１、２では１００％であ
り密着強度も９〜１３ｇであったが、比較例ではいずれ
も付着しないものが多く、密着強度も０〜１０ｇとばら
ついた。The wiring boards produced as described above were wire-bonded both to the wiring boards as they were and to those heat-treated at 180 ° C. for 2 hours. At this time, the number of wire bonds to be performed on one wiring board is 1
The number is 100, and the number of successful wire bonds is represented by the adhesion rate. Those that are not heat treated are those of Examples 1 and 2,
In Comparative Example 1, the adhesion rate is 100% and the adhesion strength is 9
Although the amount was up to 13 g, in Comparative Examples 2, 3 and 4, some did not adhere and the adhesion strength varied from 0 to 10 g. In Examples 1 and 2, the heat-treated product had 100% and the adhesion strength was 9 to 13 g, but in Comparative Examples, many did not adhere, and the adhesion strength varied from 0 to 10 g.
【００１９】[0019]
【発明の効果】以上に説明したように、本発明によっ
て、加熱処理によってもワイヤボンディングの成功を妨
げないワイヤボンディング用端子とその製造方法並びに
そのワイヤボンディング端子を用いた半導体搭載用基板
の製造方法を提供することができる。As described above, according to the present invention, a wire bonding terminal that does not prevent successful wire bonding even by heat treatment, a method for manufacturing the same, and a method for manufacturing a semiconductor mounting substrate using the wire bonding terminal. Can be provided.
Claims (6)
っき皮膜、置換パラジウムめっき皮膜または無電解パラ
ジウムめっき皮膜、置換金めっき皮膜、無電解金めっき
皮膜を、この順序に形成したことを特徴とするワイヤボ
ンディング用端子。1. An electroless nickel plating film, a substituted palladium plating film or an electroless palladium plating film, a displacement gold plating film, and an electroless gold plating film are formed in this order on the surface of terminal-shaped copper. Terminal for wire bonding.
であることを特徴とする請求項１に記載のワイヤボンデ
ィング用端子。2. The wire bonding terminal according to claim 1, wherein the electroless nickel film has a thickness of 1 μm or more.
ラジウムめっき皮膜の厚さが、０．１μｍ以上であるこ
とを特徴とする請求項１または２に記載のワイヤボンデ
ィング用端子。3. The wire bonding terminal according to claim 1, wherein the substituted palladium plating film or the electroless palladium plating film has a thickness of 0.1 μm or more.
厚さの和が、０．０４μｍ以上であることを特徴とする
請求項１〜３のうちいずれかに記載のワイヤボンディン
グ用端子。4. The wire bonding terminal according to claim 1, wherein the sum of the thicknesses of the displacement gold plating film and the electroless gold plating film is 0.04 μm or more.
っき皮膜を形成し、その表面に置換パラジウムめっき皮
膜または無電解パラジウムめっき皮膜を形成し、その表
面に置換金めっき皮膜を形成し、その表面に無電解金め
っき皮膜を形成したことを特徴とするワイヤボンディン
グ用端子の製造方法。5. An electroless nickel plating film is formed on the surface of terminal-shaped copper, a substitutional palladium plating film or an electroless palladium plating film is formed on the surface, and a substitutional gold plating film is formed on the surface. A method for manufacturing a terminal for wire bonding, characterized in that an electroless gold plating film is formed on the surface thereof.
子と、外部接続用端子と、前記ワイヤボンディング用端
子と外部接続用端子とを電気的に接続する導体回路と、
これらを支持する絶縁部からなる半導体搭載用基板の製
造方法において、端子形状の銅の表面に、無電解ニッケ
ルめっき皮膜を形成し、その表面に置換パラジウムめっ
き皮膜または無電解パラジウムめっき皮膜を形成し、そ
の表面に置換金めっき皮膜を形成し、その表面に無電解
金めっき皮膜を形成したことを特徴とするワイヤボンデ
ィング端子を用いた半導体搭載用基板の製造方法。6. A semiconductor mounting portion, a wire bonding terminal, an external connection terminal, and a conductor circuit for electrically connecting the wire bonding terminal and the external connection terminal.
In a method for manufacturing a semiconductor mounting substrate consisting of an insulating portion that supports these, an electroless nickel plating film is formed on the surface of terminal-shaped copper, and a displacement palladium plating film or an electroless palladium plating film is formed on the surface. A method for manufacturing a substrate for mounting a semiconductor using a wire bonding terminal, wherein a substitutional gold plating film is formed on the surface and an electroless gold plating film is formed on the surface.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15313995A JP3345529B2 (en) | 1995-06-20 | 1995-06-20 | Wire bonding terminal, method of manufacturing the same, and method of manufacturing semiconductor mounting substrate using the wire bonding terminal |
| JP5526099A JP3596335B2 (en) | 1995-06-20 | 1999-03-03 | Semiconductor mounting substrate using wire bonding terminals |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15313995A JP3345529B2 (en) | 1995-06-20 | 1995-06-20 | Wire bonding terminal, method of manufacturing the same, and method of manufacturing semiconductor mounting substrate using the wire bonding terminal |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5526099A Division JP3596335B2 (en) | 1995-06-20 | 1999-03-03 | Semiconductor mounting substrate using wire bonding terminals |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH098438A true JPH098438A (en) | 1997-01-10 |
| JP3345529B2 JP3345529B2 (en) | 2002-11-18 |
Family
ID=15555871
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15313995A Expired - Lifetime JP3345529B2 (en) | 1995-06-20 | 1995-06-20 | Wire bonding terminal, method of manufacturing the same, and method of manufacturing semiconductor mounting substrate using the wire bonding terminal |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3345529B2 (en) |
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| US6548898B2 (en) | 2000-12-28 | 2003-04-15 | Fujitsu Limited | External connection terminal and semiconductor device |
| WO2006112215A1 (en) * | 2005-04-01 | 2006-10-26 | Nippon Mining & Metals Co., Ltd. | Plated base material |
| JP2007009250A (en) * | 2005-06-29 | 2007-01-18 | Daiken Kagaku Kogyo Kk | Electronic component wiring method, and electronic component |
| JP2007031826A (en) * | 2005-06-23 | 2007-02-08 | Hitachi Chem Co Ltd | Connection terminal and substrate for mounting semiconductor having the same |
| JP2007031740A (en) * | 2005-07-22 | 2007-02-08 | Shinko Electric Ind Co Ltd | Electronic component, and its manufacturing method |
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| WO2008136327A1 (en) * | 2007-04-27 | 2008-11-13 | Hitachi Chemical Company, Ltd. | Connecting terminal, semiconductor package using connecting terminal and method for manufacturing semiconductor package |
| US7887692B2 (en) | 2006-03-03 | 2011-02-15 | Electroplating Engineers Of Japan Limited | Palladium plating solution |
| US8124174B2 (en) | 2007-04-16 | 2012-02-28 | C. Uyemura & Co., Ltd. | Electroless gold plating method and electronic parts |
| CN102597320A (en) * | 2010-08-27 | 2012-07-18 | 日本电镀工程股份有限公司 | Gold displacement plating solution, and method for formation of joint part |
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| US8787028B2 (en) | 2011-11-30 | 2014-07-22 | Tdk Corporation | Terminal structure, printed circuit board, module board, electronic device, and method for manufacturing terminal structure |
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- 1995-06-20 JP JP15313995A patent/JP3345529B2/en not_active Expired - Lifetime
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