JPH11140658A - Substrate for mounting semiconductor and its production - Google Patents

Substrate for mounting semiconductor and its production

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Publication number
JPH11140658A
JPH11140658A JP30235197A JP30235197A JPH11140658A JP H11140658 A JPH11140658 A JP H11140658A JP 30235197 A JP30235197 A JP 30235197A JP 30235197 A JP30235197 A JP 30235197A JP H11140658 A JPH11140658 A JP H11140658A
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JP
Japan
Prior art keywords
electroless
plating film
nickel
plating
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP30235197A
Other languages
Japanese (ja)
Inventor
Kiyoshi Hasegawa
Akishi Nakaso
Akio Takahashi
昭士 中祖
清 長谷川
昭男 高橋
Original Assignee
Hitachi Chem Co Ltd
日立化成工業株式会社
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Publication date
Application filed by Hitachi Chem Co Ltd, 日立化成工業株式会社 filed Critical Hitachi Chem Co Ltd
Priority to JP30235197A priority Critical patent/JPH11140658A/en
Publication of JPH11140658A publication Critical patent/JPH11140658A/en
Application status is Pending legal-status Critical

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Classifications

    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/02Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings only including layers of metallic material
    • C23C28/021Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings only including layers of metallic material including at least one metal alloy layer
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/02Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings only including layers of metallic material
    • C23C28/023Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings only including layers of metallic material only coatings of metal elements only
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern
    • H05K3/244Finish plating of conductors, especially of copper conductors, e.g. for pads or lands

Abstract

PROBLEM TO BE SOLVED: To provide a substrate for mounting semiconductors having high joining strength of solder ball terminals and solder balls and a process for producing the same.
SOLUTION: This substrate for mounting the semiconductors is constituted by forming an electroless nickel plating film on a circuit consisting of metals, forming an electroless palladium plating film on the electroless nickel plating film and forming an electroless gold plating film on the electroless palladium plating film. The electroless nickel plating film is a nickel-boron alloy film. This process for producing the substrate for mounting the semiconductors consists in successively forming the electroless nickel-boron alloy plating, the electroless palladium plating and the electroless gold plating film on circuits consisting of metals, such as copper.
COPYRIGHT: (C)1999,JPO

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は、半導体搭載用基板とその製造方法に関する。 The present invention relates to a substrate and its manufacturing method for semiconductor mounting.

【0002】 [0002]

【従来の技術】プリント配線板は、近年、高密度化が進んでおり、配線板に直接半導体チップを搭載するチップサイズパッケージ(以下、CSPという。)、ボールグリッドアレイ(以下、BGAという。)、マルチチップモジュール(以下、MCMという。)等の半導体搭載用基板の需要が伸びている。 BACKGROUND OF THE INVENTION printed wiring board, in recent years, and they have become densified, chip size package for mounting directly semiconductor chip on a wiring board (hereinafter. Referred CSP), ball grid array (hereinafter, referred to as BGA.) , multi-chip module is extended demand for semiconductor mounting substrate (hereinafter, referred to. MCM) or the like.

【0003】半導体搭載用基板と半導体チップの接続方法は、主にワイヤボンディングで接続し、半導体搭載用基板とこの基板を含んだCSP、BGA、MCM等の電子部品を実装するプリント配線板との接続方法は、主に半田ボールで行うので、これらのために半導体搭載用基板は、ワイヤボンディング端子と半田ボール端子を有している。 [0003] The connection method for a semiconductor mounting substrate and the semiconductor chip is mainly connected by wire bonding, a semiconductor mounting board including a substrate CSP, BGA, the printed wiring board for mounting electronic parts MCM etc. connection method, is performed mainly in the solder balls, a semiconductor substrate for mounting for these, has a wire bonding terminal and the solder ball terminals.

【0004】半導体搭載用基板のワイヤボンディング端子と半田ボール端子の従来の構造は、基板内に形成した銅端子上にニッケル、金の皮膜を順次形成したものであり、端子の製造方法には無電解ニッケルめっき、置換金めっきのめっき皮膜順次形成する方法と無電解ニッケルめっき、置換金めっき、無電解金めっきのめっき皮膜を順次形成する方法がある。 Conventional structure of a semiconductor mounting substrate wire bonding terminal and the solder ball terminals, which has nickel, a coating of gold are sequentially formed on the copper terminal formed in the substrate, the manufacturing method of the terminal nothingness electrolytic nickel plating, plating film are sequentially formed to a method and electroless nickel plating immersion gold plating, there is a method of sequentially forming a plating film of substitution gold plating, electroless gold plating.

【0005】また、加熱処理後のワイヤボンディング性を向上させた端子の構造として基板内に形成した銅端子上にニッケル、パラジウム、金の皮膜を順次形成したものがある。 Further, the nickel on the copper terminal formed in the substrate as a structure with improved wire bondability after heat treatment pins, palladium, there is obtained by sequentially forming a film of gold.

【0006】端子の製造方法には無電解ニッケルめっき、無電解パラジウム、置換金めっきのめっき皮膜を順次形成する方法と無電解ニッケルめっき、無電解パラジウム、置換金めっき、無電解金めっきのめっき皮膜を順次形成する方法等がある。 [0006] terminal of the manufacturing method electroless nickel plating, electroless palladium, a method and an electroless nickel plating of sequentially forming a plating film of substitution gold plating, electroless palladium, displacement gold plating, electroless gold plating plating film there is a method to sequentially form like.

【0007】以上の端子のニッケルの形成に用いられていた無電解ニッケルめっきは、還元剤が次亜燐酸ナトリウムであり、形成されたニッケル皮膜はニッケル−燐(Ni−P)合金である。 [0007] The above electroless nickel plating has been used in the formation of nickel terminal, the reducing agent is sodium hypophosphite, nickel coating formed nickel - phosphorus (Ni-P) alloy.

【0008】 [0008]

【発明が解決しようとする課題】従来の加熱処理後のワイヤボンディング性を向上させたニッケル−燐、パラジウム、金の多端子構造は加熱処理後のワイヤボンディング性は良好であるが、半田ボール端子と半田ボールの接続強度が劣化し易いことがわかった。 With improved wire bondability after conventional heat treatment [0005] Nickel - phosphorus, palladium, although a multi-terminal structure of the gold is good wire bonding property after the heat treatment, the solder ball terminals the connection strength of the solder ball has been found to be susceptible to degradation.

【0009】また、高密度化に伴い半田ボールの径が小さくなり、半田ボール端子の接続面積も小さくなり、半田ボール端子と半田ボールの接合強度が重要になってきている。 Further, the diameter of the solder ball increases in density is reduced, contact area of ​​the solder ball terminals is also small, the bonding strength of the solder ball terminal and the solder balls has become important.

【0010】本発明は、半田ボール端子と半田ボールの接続強度が大きい、半導体搭載用基板とその製造方法を提供することを目的とする。 The present invention, connection strength of the solder ball terminal and the solder balls is large, and an object thereof is to provide a substrate and a manufacturing method thereof for mounting semiconductor.

【0011】 [0011]

【課題を解決するための手段】本発明の半導体搭載用基板は、金属からなる回路上に無電解ニッケルめっき皮膜、無電解ニッケルめっき皮膜上に無電解パラジウムめっき皮膜、無電解パラジウムめっき皮膜上に無電解金めっき皮膜を形成した半導体搭載用基板において、無電解ニッケルめっき皮膜がニッケル−ホウ素合金皮膜であることを特徴とする。 Means for Solving the Problems A semiconductor mounting board of the present invention, electroless nickel plating film on a circuit composed of metallic, electroless palladium plating film on the electroless nickel plating film, on the electroless palladium plating film in the semiconductor mounting board to form an electroless gold plating film, an electroless nickel plating film of nickel - characterized in that it is a boron alloy coating.

【0012】この半導体搭載用基板の製造方法は、銅等の金属からなる回路上に無電解ニッケル−ホウ素合金めっき、無電解パラジウムめっき、無電解金めっきのめっき皮膜を順次形成することを特徴とする。 [0012] method of manufacturing a semiconductor mounting substrate, electroless nickel on a circuit made of a metal such as copper - and characterized by sequentially forming a plating film of boron alloy plating, electroless palladium plating, electroless gold plating to.

【0013】 [0013]

【発明の実施の形態】無電解ニッケルめっきは、めっき液中のニッケルイオンがニッケルイオンの水素化ホウ素ナトリウム、ジメチルアミンボラン等のホウ素系還元剤の働きによって、銅等の金属の活性化した表面にニッケル−ホウ素合金を析出させるものであればよく、特に限定しない。 [OF THE PREFERRED EMBODIMENTS OF THE INVENTION Electroless nickel plating, sodium borohydride nickel ions nickel ions in the plating solution, by the action of boron-based reducing agent of dimethylamine borane, and activated metal such as copper surfaces nickel - as long as to deposit a boron alloy is not particularly limited.

【0014】また、無電解パラジウムめっきは、置換パラジウムと還元型無電解パラジウムがある。 [0014] In addition, electroless palladium plating, there is a replacement palladium reduction type electroless palladium. 置換パラジウムめっきは、下地のニッケルとめっき液中のパラジウムイオンの置換反応によって、ニッケル表面にパラジウム皮膜を形成するものであればよく、特に限定しない。 Substituted palladium plating, the substitution reaction of palladium ion in the plating solution as a base of nickel, as long as it forms a palladium film on the nickel surface is not particularly limited.

【0015】また、還元型無電解パラジウムめっきは、 [0015] In addition, the reduction type electroless palladium plating,
めっき液中のパラジウムイオンの還元剤の働きによって、ニッケル表面にパラジウムを析出させるものであればよく、特に限定しない。 By the action of a reducing agent of palladium ions in the plating solution, as long as to deposit palladium nickel surface is not particularly limited.

【0016】無電解金めっきは、置換金めっきと還元型無電解金めっきがある。 [0016] The electroless gold plating, there is a reduction type electroless gold plating and immersion gold plating. 置換金めっきは下地のパラジウムと溶液中の金イオンとの置換反応によって、パラジウム表面に金皮膜を形成するものであり、還元型無電解金めっきはめっき液中の金イオンが金イオンの還元剤の働きによって金表面に金を析出させるものであればよく、 Substitution gold plating by substitution reaction with gold ions of palladium and a solution of the base, which forms a gold coating on the palladium surface, reducing type electroless gold plating is gold ions in the plating solution of gold ions reducing agent by the action of long as gold is to be deposited on the gold surface,
特に限定しない。 Not particularly limited. 無電解金めっき皮膜は、置換金めっきだけの皮膜、または置換金めっきと還元型無電解金めっきを順次形成した多層皮膜でもよい。 Electroless gold plating film, the film only displacement gold plating or displacement gold plating and the reducing type non or a multilayer film in which the electrolytic gold plating are sequentially formed.

【0017】基材の種類は、セラミック、半導体、樹脂基板等があるが、特に限定するものではない。 The type of substrate is a ceramic, semiconductor, there is a resin substrate, etc., is not particularly limited. 樹脂基板についてもフェノール、エポキシ、ポリイミド等のものがあるが特に限定するものではない。 Phenol, epoxy, there are those of polyimide is not particularly limited also the resin substrate.

【0018】 [0018]

【実施例】実施例 銅張りポリイミド積層板をエッチングレジスト形成、エッチング後の導体パターンの露出した銅端子上に以下の処理を行う。 EXAMPLES Example copper-clad polyimide laminate etching resist formation, the following process is performed on the exposed copper terminals of the conductive pattern after etching. −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− 工 程 溶 液 濃 度 液温 浸漬時間 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− ・脱脂 Z−200 60℃ 1分 ・水洗 室温 2分 ・ソフトエッチング 過硫酸アンモニウム 100g/l 室温 1分 ・水洗 室温 2分 ・酸洗 硫酸 10体積% 室温 1分 ・水洗 室温 2分 ・活性化 SA−100 室温 5分 ・水洗 室温 2分 ・無電解ニッケル−ホウ素合金めっき(厚さ:5μm) トップケミアロイ66 65℃ 30分 ・水洗 室温 2分 ・無電解パラジウムめっき(厚さ:05μm) パレット 70℃ 5分 ・水洗 室温 2分 ・置換金めっき(厚さ:0.02μm) HGS−100 85℃ 10分 ・水洗 室温 2分 ・無電解金めっき(厚 ------------------------------------ Engineering as soluble liquid concentration of liquid temperature dipping time ---- -------------------------------- degreasing Z-200 60 ℃ 1 minute, washed with water at room temperature for 2 minutes, soft etching over ammonium sulfate 100 g / l at room temperature for 1 minute, washed with water at room temperature for 2 minutes, pickled sulfate 10% by volume at room temperature for 1 minute, washed with water at room temperature for 2 minutes activatable SA-100 RT 5 minutes, washed with water at room temperature for 2 minutes, electroless nickel - boron alloy plating ( thickness: 5 [mu] m) Top Kemi alloy 66 65 ° C. 30 minutes, washed with water at room temperature for 2 minutes, electroless palladium plating (thickness: 05μm) pallet 70 ° C. 5 minutes, washed with water at room temperature for 2 minutes, immersion gold plating (thickness: 0.02 [mu] m ) HGS-100 85 ℃ 10 minutes, washed with water at room temperature for 2 minutes, electroless gold plating (thickness さ:0.5μm) HGS−2000 65℃ 19分 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− 注)Z−200(株式会社ワールドメタル製、商品名) SA−100(日立化成工業株式会社製、商品名) トップケミアロイ66(奥野薬品工業株式会社製、商品名) パレット(小島化学薬品株式会社製、商品名) HGS−100(日立化成工業株式会社製、商品名) HGS−2000(日立化成工業株式会社製、商品名) Is the: 0.5μm) HGS-2000 65 ℃ 19 minutes ------------------------------------ Note ) Z-200 (World Co., Ltd. metal, product name) SA-100 (manufactured by Hitachi chemical Co., Ltd., trade name) top chemi-alloy 66 (Okuno Pharmaceutical Industries Co., Ltd., trade name) palette (Kojima chemicals Co., Ltd. Ltd., trade name) HGS-100 (manufactured by Hitachi Chemical Co., Ltd., trade name) HGS-2000 (manufactured by Hitachi Chemical Co., Ltd., trade name)

【0019】比較例 銅張りポリイミド積層板をエッチングレジスト形成、エッチング後の導体パターンの露出した銅端子上に以下の処理を行う。 The etching resist forms a comparative example a copper-clad polyimide laminates, the following processing on the exposed copper terminals of the conductive pattern after the etching performed. −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− 工 程 溶 液 濃 度 液温 浸漬時間 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− ・脱脂 Z−200 60℃ 1分 ・水洗 室温 2分 ・ソフトエッチング 過硫酸アンモニウム 100g/l 室温 1分 ・水洗 室温 2分 ・酸洗 硫酸 10体積% 室温 1分 ・水洗 室温 2分 ・活性化 SA−100 室温 5分 ・水洗 室温 2分 ・無電解ニッケル−燐合金めっき(厚さ:5μm) NIPS−100 85℃ 20分 ・水洗 室温 2分 ・無電解パラジウムめっき(厚さ:0.5μm) パレット 70℃ 5分 ・水洗 室温 2分 ・置換金めっき(厚さ:0.02μm) HGS−100 85℃ 10分 ・水洗 室温 2分 ・無電解金めっき(厚さ:0 ------------------------------------ Engineering as soluble liquid concentration of liquid temperature dipping time ---- -------------------------------- degreasing Z-200 60 ℃ 1 minute, washed with water at room temperature for 2 minutes, soft etching over ammonium sulfate 100 g / l at room temperature for 1 minute, washed with water at room temperature for 2 minutes, pickled sulfate 10% by volume at room temperature for 1 minute, washed with water at room temperature for 2 minutes activatable SA-100 RT 5 minutes, washed with water at room temperature for 2 minutes, electroless nickel - phosphorus alloy plating ( thickness: 5μm) NIPS-100 85 ℃ 20 minutes, washed with water at room temperature for 2 minutes, electroless palladium plating (thickness: 0.5 [mu] m) pallet 70 ° C. 5 minutes, washed with water at room temperature for 2 minutes, immersion gold plating (thickness: 0. 02μm) HGS-100 85 ℃ 10 minutes, washed with water at room temperature for 2 minutes, electroless gold plating (thickness: 0 .5μm) HGS−2000 65℃ 40分 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− 注)Z−200(株式会社ワールドメタル製、商品名) SA−100(日立化成工業株式会社製、商品名) NIPS−100(日立化成工業株式会社製、商品名) パレット(小島化学薬品株式会社製、商品名) HGS−100(日立化成工業株式会社製、商品名) HGS−2000(日立化成工業株式会社製、商品名) .5μm) HGS-2000 65 ℃ 40 minutes ------------------------------------ Note) Z- 200 (World Co., Ltd. metal, product name) SA-100 (manufactured by Hitachi chemical Co., Ltd., trade name) NIPS-100 (manufactured by Hitachi chemical Co., Ltd., trade name) palette (Kojima chemicals Co., Ltd., trade name ) HGS-100 (manufactured by Hitachi Chemical Co., Ltd., trade name) HGS-2000 (manufactured by Hitachi Chemical Co., Ltd., trade name)

【0020】実施例と比較例で得た半導体搭載用基板の半田ボール端子に、半田ボールを接続して150℃、5 [0020] Solder balls terminal of the semiconductor mounting board obtained in Examples and Comparative Examples, 0.99 ° C. by connecting the solder balls, 5
0時間の加熱劣化試験を行った。 The heating deterioration test of 0 hours were carried out. 実施例のニッケル−ホウ素合金皮膜を形成したものは、半田ボール接続強度(シェア強度)の低下率が0%であった。 Nickel embodiment - those forming the boron alloy coating, rate of decrease in the solder ball connection strength (shear strength) was 0%. 比較例のニッケル−燐合金皮膜を形成したものは、半田ボール接続強度(シェア強度)の低下率が40%であった。 Comparative Example nickel - that form the phosphorus alloy coating, a reduction rate of the solder ball connection strength (shear strength) was 40%.

【0021】 [0021]

【発明の効果】このように本発明により、半田ボール接続性に優れた半導体搭載用基板とその製造方法を提供することができる。 Effect of the Invention By the present invention as described above, it is possible to provide an excellent semiconductor mounting substrate and a manufacturing method thereof in the solder ball connectivity.

Claims (2)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】金属からなる回路上に無電解ニッケルめっき皮膜が形成され、その無電解ニッケルめっき皮膜上に無電解パラジウムめっき皮膜が形成され、その無電解パラジウムめっき皮膜上に無電解金めっき皮膜が形成された半導体搭載用基板において、無電解ニッケルめっき皮膜がニッケル−ホウ素合金皮膜であることを特徴とする半導体搭載用基板。 1. A electroless nickel plating film on a circuit made of a metal is formed, the electroless nickel plating film electroless palladium plating film on are formed, an electroless gold plating film on the electroless palladium plating film in the semiconductor mounting board but formed, an electroless nickel plating film of nickel - semiconductor mounting substrate which is a boron alloy coating.
  2. 【請求項2】金属からなる回路上に、無電解ニッケル− Wherein on a circuit consisting of a metal, electroless nickel -
    ホウ素合金めっき皮膜、無電解パラジウムめっき皮膜、 Boron alloy plating film, an electroless palladium plating film,
    無電解金めっき皮膜を順次形成することを特徴とする半導体搭載用基板の製造方法。 The method of manufacturing a semiconductor mounting substrate, which comprises successively forming an electroless gold plating film.
JP30235197A 1997-11-05 1997-11-05 Substrate for mounting semiconductor and its production Pending JPH11140658A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30235197A JPH11140658A (en) 1997-11-05 1997-11-05 Substrate for mounting semiconductor and its production

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6800555B2 (en) 2000-03-24 2004-10-05 Texas Instruments Incorporated Wire bonding process for copper-metallized integrated circuits
JP2007031740A (en) * 2005-07-22 2007-02-08 Shinko Electric Ind Co Ltd Electronic component, and its manufacturing method
JPWO2011099597A1 (en) * 2010-02-15 2013-06-17 株式会社Jcu Method for manufacturing printed wiring board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6800555B2 (en) 2000-03-24 2004-10-05 Texas Instruments Incorporated Wire bonding process for copper-metallized integrated circuits
JP2007031740A (en) * 2005-07-22 2007-02-08 Shinko Electric Ind Co Ltd Electronic component, and its manufacturing method
JPWO2011099597A1 (en) * 2010-02-15 2013-06-17 株式会社Jcu Method for manufacturing printed wiring board

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