JPH1197568A - Cavity-down type bga package - Google Patents
Cavity-down type bga packageInfo
- Publication number
- JPH1197568A JPH1197568A JP9256954A JP25695497A JPH1197568A JP H1197568 A JPH1197568 A JP H1197568A JP 9256954 A JP9256954 A JP 9256954A JP 25695497 A JP25695497 A JP 25695497A JP H1197568 A JPH1197568 A JP H1197568A
- Authority
- JP
- Japan
- Prior art keywords
- cavity
- copper plating
- semiconductor chip
- needle
- metal plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、放熱スラグの下面
側に形成されたキャビティに半導体チップをダイボンデ
ィングしたキャビティダウン型ＢＧＡパッケージに関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cavity-down type BGA package in which a semiconductor chip is die-bonded to a cavity formed on a lower surface of a heat dissipation slag.
【０００２】[0002]
【従来の技術】近年、半導体パッケージに対する高密度
化、高速化、多ピン化の要求は益々強くなっており、そ
の要求を満たすために、ＢＧＡ（Ball Grid Array ）パ
ッケージの需要が急増している。このＢＧＡパッケージ
は、下面に接続電極として多数の半田ボールが配列され
た表面実装型のパッケージであり、最近の高性能化に伴
う発熱量増大の問題に対処するために、放熱スラグ（放
熱板）を有するキャビティダウン型のプラスチックＢＧ
Ａが開発されている。2. Description of the Related Art In recent years, demands for higher density, higher speed, and higher pin counts for semiconductor packages have been increasing, and the demand for BGA (Ball Grid Array) packages has been rapidly increasing to meet the demands. . This BGA package is a surface mount type package in which a large number of solder balls are arranged as connection electrodes on the lower surface. In order to cope with the problem of an increase in the amount of heat generated due to recent high performance, a heat dissipation slag (heat dissipation plate) is used. -Down type plastic BG having
A is being developed.
【０００３】このキャビティダウン型ＢＧＡパッケージ
は、例えば図６に示すように、２枚の銅板１１ａ，１１
ｂを積層して、下面側にキャビティ１２を有する放熱ス
ラグ１１を構成し、この放熱スラグ１１の下面にプラス
チック回路基板１３を接着すると共に、放熱スラグ１１
のキャビティ１２底面に半導体チップ１４をダイボンデ
ィングして封止樹脂１５で封止した構造となっている。This cavity-down type BGA package is, for example, as shown in FIG.
b to form a heat dissipating slag 11 having a cavity 12 on the lower surface side, a plastic circuit board 13 is adhered to the lower surface of the heat dissipating slag 11, and
The semiconductor chip 14 is die-bonded to the bottom surface of the cavity 12 and sealed with a sealing resin 15.
【０００４】このものでは、放熱スラグ１１のキャビテ
ィ１２底面と半導体チップ１４との接着強度を高めるた
めに、キャビティ１２底面（銅板１１ａの下面）を粗化
処理し、アンカー効果によって機械的な接着強度を高め
るようにしている。従来の粗化処理は、多層配線板の内
層銅箔処理に用いられているブラックオキサイドと呼ば
れる酸化処理法が採用され、亜塩素酸塩を主剤とするア
ルカリ水溶液に銅板１１ａを浸して、その表面に微細な
針状突起のある酸化第二銅被膜１６を形成するものであ
る。In this apparatus, the bottom surface of the cavity 12 (the lower surface of the copper plate 11a) is roughened in order to increase the bonding strength between the bottom surface of the cavity 12 of the heat radiation slag 11 and the semiconductor chip 14, and the mechanical bonding strength is provided by an anchor effect. To increase. The conventional roughening treatment employs an oxidation treatment method called black oxide used in the treatment of the inner layer copper foil of the multilayer wiring board. The copper plate 11a is immersed in an aqueous alkali solution mainly composed of chlorite, and its surface is roughened. To form a cupric oxide coating 16 having fine needle-like projections.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、酸化第
二銅被膜１６の表面の微細な針状突起は、脆く、折れや
すいため、十分なアンカー効果が得られず、半導体チッ
プ１４の接着強度が比較的弱く、半導体チップ１４の接
着信頼性が低いという欠点があった。However, the fine needle-like projections on the surface of the cupric oxide film 16 are brittle and easily broken, so that a sufficient anchor effect cannot be obtained, and the bonding strength of the semiconductor chip 14 is relatively small. There is a disadvantage that the bonding reliability of the semiconductor chip 14 is low.
【０００６】本発明はこのような事情を考慮してなされ
たものであり、従ってその目的は、放熱スラグのキャビ
ティ底面と半導体チップとの接着強度を十分に高めるこ
とができ、半導体チップの接着信頼性を向上することが
できるキャビティダウン型ＢＧＡパッケージを提供する
ことにある。SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and it is therefore an object of the present invention to sufficiently increase the bonding strength between the semiconductor chip and the bottom surface of the cavity of the heat dissipation slag. Another object of the present invention is to provide a cavity-down type BGA package which can improve the performance.
【０００７】[0007]
【課題を解決するための手段】上記目的を達成するため
に、本発明のキャビティダウン型ＢＧＡパッケージは、
放熱スラグのうちの少なくとも半導体チップをダイボン
ディングする部分に針状銅めっき被膜を形成したもので
ある（請求項１）。この針状銅めっき被膜は、従来の酸
化第二銅被膜と比較して、表面の針状突起の強度が大き
く、針状突起が折れにくいため、十分なアンカー効果が
得られ、半導体チップの接着強度が十分に高められる。In order to achieve the above object, a cavity-down type BGA package of the present invention comprises:
An acicular copper plating film is formed on at least a portion of the heat dissipation slag where the semiconductor chip is die-bonded (claim 1). This needle-like copper plating film has a greater strength of the needle-like protrusions on the surface and is less likely to be broken than the conventional cupric oxide film, so that a sufficient anchoring effect is obtained and the bonding of the semiconductor chip is achieved. Strength is sufficiently increased.
【０００８】この場合、針状銅めっき被膜は、次亜リン
酸塩を還元剤とする無電解銅めっきにより形成すると良
い（請求項２）。次亜リン酸塩を還元剤とする無電解銅
めっきの特徴は、めっき被膜の表面に、アンカー効果を
持たせるための針状の粗い結晶形態を形成しやすく、し
かも、ブラックオキサイド処理と比較して、大きな針状
突起を形成することができ、アンカー効果を発揮しやす
くなっている。また、従来のホルマリンを還元剤とする
無電解銅めっきと比較して、析出速度が速く、めっき工
程の時間を短くできる。更に、この無電解銅めっき溶液
には、ホルマリン等の環境を汚染する薬品は含まれず、
弱アルカリ性であり、安全性に優れている。In this case, the needle-like copper plating film is preferably formed by electroless copper plating using hypophosphite as a reducing agent. The feature of electroless copper plating using hypophosphite as a reducing agent is that it easily forms a needle-like coarse crystal morphology to give an anchor effect on the surface of the plating film, and it is more effective than black oxide treatment. As a result, a large needle-like projection can be formed, and the anchor effect is easily exhibited. Further, as compared with conventional electroless copper plating using formalin as a reducing agent, the deposition rate is faster and the time of the plating step can be shortened. Furthermore, this electroless copper plating solution does not contain chemicals that pollute the environment such as formalin.
It is weakly alkaline and has excellent safety.
【０００９】[0009]
【発明の実施の形態】以下、本発明の実施形態（１）を
図１及び図２に基づいて説明する。まず、キャビティダ
ウン型ＢＧＡパッケージの構造を図１に基づいて説明す
る。放熱スラグ２１を、四角形に打ち抜かれた平板状の
金属板２２と、中央部にキャビティ２４の開口が打ち抜
き形成された金属板２３とから構成し、これら２枚の金
属板２２，２３をＡｇＣｕろう等のろう材又は接着樹脂
（プリプレグ）で接合している。各金属板２２，２３
は、例えば銅板、銅合金板等により形成され、これをＡ
ｇＣｕろうでろう付けする場合には、還元性雰囲気中で
約８００℃にてろう付けする。更に、予め、上側の金属
板２２の下面には、後述する無電解銅めっきにより針状
銅めっき被膜２５が形成され、この針状銅めっき被膜２
５がキャビティ２４の底面に露出している。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment (1) of the present invention will be described below with reference to FIGS. First, the structure of the cavity-down type BGA package will be described with reference to FIG. The heat dissipating slag 21 is composed of a flat metal plate 22 punched in a square shape and a metal plate 23 formed by punching an opening of a cavity 24 in the center. These two metal plates 22 and 23 are made of AgCu solder. And the like or an adhesive resin (prepreg). Each metal plate 22, 23
Is formed of, for example, a copper plate, a copper alloy plate, etc.
When brazing with gCu brazing, brazing is performed at about 800 ° C. in a reducing atmosphere. Further, an acicular copper plating film 25 is formed on the lower surface of the upper metal plate 22 in advance by electroless copper plating described later.
5 is exposed on the bottom surface of the cavity 24.
【００１０】放熱スラグ２１の下面（下側の金属板２３
の下面）には、プラスチック回路基板２６が接着樹脂
（プリプレグ）で接着されている。このプラスチック回
路基板２６の接着は、約２００℃の真空中で３０〜４０
ｋｇｆ／ｃｍ2 の加圧力を加えて行われる。このプラス
チック回路基板２６は、例えばＢＴ（ビスマレイミド・
トリアジン）エポキシ樹脂等の高耐熱性、誘電特性、絶
縁特性、加工性に優れた樹脂を基材とする単層又は多層
のプリント基板であり、その中央部にキャビティ２４の
開口が形成されている。このプラスチック回路基板２６
の下面には、接続電極として多数の半田ボール２７が配
列されると共に、半田ボール２７以外の露出面には、半
田レジスト（図示せず）が塗布されている。The lower surface of the heat radiation slag 21 (the lower metal plate 23)
A plastic circuit board 26 is adhered to the lower surface of the substrate with an adhesive resin (prepreg). The bonding of the plastic circuit board 26 is performed in a vacuum of about 200 ° C. for 30 to 40 times.
This is performed by applying a pressing force of kgf / cm 2 . The plastic circuit board 26 is made of, for example, BT (bismaleimide.
Triazine) A single-layer or multi-layer printed board made of a resin having excellent heat resistance, dielectric properties, insulation properties, and workability such as epoxy resin as a base material, and an opening of a cavity 24 is formed in a central portion thereof. . This plastic circuit board 26
A large number of solder balls 27 are arranged as connection electrodes on the lower surface of the device, and a solder resist (not shown) is applied to an exposed surface other than the solder balls 27.
【００１１】一方、放熱スラグ２１のキャビティ２４底
面（金属板２２の下面）には、半導体チップ２８がエポ
キシ銀ペースト等の接着剤によりダイボンディングされ
ている。この場合、キャビティ２４底面（金属板２２の
下面）には、針状銅めっき被膜２５が形成され、その表
面に形成された無数の針状突起に半導体チップ２８の接
着剤が食い込むことでアンカー効果が生じて、キャビテ
ィ２４底面と半導体チップ２８との接着強度が高められ
る。On the other hand, a semiconductor chip 28 is die-bonded to the bottom surface of the cavity 24 (the lower surface of the metal plate 22) of the heat radiation slag 21 by an adhesive such as an epoxy silver paste. In this case, a needle-like copper plating film 25 is formed on the bottom surface of the cavity 24 (the lower surface of the metal plate 22), and the adhesive of the semiconductor chip 28 penetrates the countless needle-like protrusions formed on the surface thereof, thereby providing an anchor effect. Occurs, and the bonding strength between the bottom surface of the cavity 24 and the semiconductor chip 28 is increased.
【００１２】そして、半導体チップ２８とプラスチック
回路基板２６との間は、金線等のボンディングワイヤ２
９により電気的に接続されている。更に、キャビティ２
４内には、エポキシ樹脂等の封止樹脂３０が充填され、
半導体チップ２８やボンディングワイヤ２９が封止樹脂
３０で封止されている。A bonding wire 2 such as a gold wire is provided between the semiconductor chip 28 and the plastic circuit board 26.
9 are electrically connected. Further, cavity 2
4 is filled with a sealing resin 30 such as an epoxy resin,
The semiconductor chip 28 and the bonding wires 29 are sealed with a sealing resin 30.
【００１３】次に、放熱スラグ２１のキャビティ２４底
面（金属板２２の下面）に、無電解銅めっきにより針状
銅めっき被膜２５を形成する手順を図２を用いて説明す
る。まず、金属板２２の表面を脱脂剤で処理して、金属
板２２の表面に付着した油脂類を除去すると共に、該表
面の水濡れ性を良くする。この後、ソフトエッチング工
程に移り、濃硫酸と過酸化水素水との混合液に金属板２
２を浸し、金属板２２の表面を軽くエッチングして、該
表面に粒界を露出させる。続いて、酸活性工程に移り、
金属板２２を濃硫酸に浸して、該表面を活性化する。Next, a procedure for forming the acicular copper plating film 25 on the bottom surface of the cavity 24 (the lower surface of the metal plate 22) of the heat radiation slag 21 by electroless copper plating will be described with reference to FIG. First, the surface of the metal plate 22 is treated with a degreasing agent to remove fats and oils attached to the surface of the metal plate 22 and to improve the water wettability of the surface. Thereafter, the process proceeds to a soft etching step, in which a metal plate 2 is added to a mixed solution of concentrated sulfuric acid and hydrogen peroxide solution.
2, the surface of the metal plate 22 is lightly etched to expose grain boundaries on the surface. Then, it moves to the acid activation process,
The surface is activated by immersing the metal plate 22 in concentrated sulfuric acid.
【００１４】次いで、触媒付与工程に移り、金属板２２
を触媒付与液に浸漬し、金属銅とパラジウムイオンとの
置換反応によって、金属板２２の表面に金属パラジウム
（触媒）を析出させる。この後、促進化（アクセレータ
ー）工程に移り、金属板２２を促進化処理液に浸漬す
る。この促進化処理は、無電解銅めっきの初期反応を高
め、めっき析出性を向上させ、強固な下地を形成するの
に必要な処理である。Next, the process proceeds to a catalyst application step,
Is immersed in a catalyst application liquid, and metal palladium (catalyst) is deposited on the surface of the metal plate 22 by a substitution reaction between metal copper and palladium ions. Thereafter, the process proceeds to an accelerating (accelerator) step, and the metal plate 22 is immersed in the accelerating treatment liquid. This accelerating process is a process necessary for increasing the initial reaction of electroless copper plating, improving plating deposition properties, and forming a strong underlayer.
【００１５】この後、無電解銅めっき工程に移り、無電
解銅めっき溶液に金属板２２を浸漬し、金属板２２の表
面に銅の結晶を析出させて針状銅めっき被膜２５を形成
する。これにより、針状銅めっき被膜２５の表面には、
微細な針状突起が無数に形成される。ここで使用する無
電解銅めっき溶液は、還元剤として次亜リン酸ナトリウ
ム等の次亜リン酸塩が配合され、触媒金属として微量の
硫酸ニッケル等のニッケル塩が添加されたものを使用す
る。従って、析出した針状銅めっき被膜２５中には、微
量のニッケルとリンが共析する。Thereafter, the process proceeds to an electroless copper plating step, in which the metal plate 22 is immersed in an electroless copper plating solution, and copper crystals are deposited on the surface of the metal plate 22 to form an acicular copper plating film 25. Thereby, the surface of the acicular copper plating film 25 is
Innumerable fine needle-like projections are formed. The electroless copper plating solution used here is a solution in which a hypophosphite such as sodium hypophosphite is blended as a reducing agent and a trace amount of a nickel salt such as nickel sulfate is added as a catalyst metal. Therefore, trace amounts of nickel and phosphorus are eutectoid in the precipitated acicular copper plating film 25.
【００１６】ここで、次亜リン酸塩を還元剤とする無電
解銅めっきの特徴は、針状銅めっき被膜２５の表面に、
アンカー効果を持たせるための針状の粗い結晶形態を形
成しやすく、しかも、従来のブラックオキサイド処理と
比較して、大きな針状突起が形成され、アンカー効果が
出やすくなっている。また、従来のホルマリンを還元剤
とする無電解銅めっきと比較して、析出速度が速く、め
っき工程の時間を短くできる。更に、この無電解銅めっ
き溶液には、ホルマリン等の環境を汚染する薬品は含ま
れず、弱アルカリ性であり、近年の重要な技術的課題で
ある環境問題をクリアすることができ、人体に対する安
全性も高い。Here, the feature of the electroless copper plating using hypophosphite as a reducing agent is that the surface of the acicular copper plating film 25 is
A needle-like coarse crystal form for imparting an anchor effect is easily formed, and large needle-like projections are formed as compared with the conventional black oxide treatment, so that the anchor effect is easily obtained. Further, as compared with conventional electroless copper plating using formalin as a reducing agent, the deposition rate is faster and the time of the plating step can be shortened. Furthermore, this electroless copper plating solution does not contain chemicals that contaminate the environment such as formalin, is weakly alkaline, and can solve environmental problems, which is an important technical problem in recent years, and is safe for the human body. Is also expensive.
【００１７】無電解銅めっき工程終了後、酸洗浄工程に
移り、金属板２２の表面に付着した無電解銅めっき液の
残渣を稀硫酸等で中和した後、水洗して洗浄する。After the completion of the electroless copper plating step, the process proceeds to an acid cleaning step, where the residue of the electroless copper plating solution adhering to the surface of the metal plate 22 is neutralized with dilute sulfuric acid or the like, followed by washing with water and washing.
【００１８】以上のようなプロセスで形成された針状銅
めっき被膜２５は、キャビティ２４の底面に露出し、半
導体チップ２８の搭載面となる。この針状銅めっき被膜
２５は、従来の酸化第二銅被膜と比較して、表面の針状
突起の強度が大きく、針状突起が折れにくい。このた
め、針状突起による十分なアンカー効果を得ることがで
き、半導体チップ２８の接着強度を十分に高めることが
できて、半導体チップ２８の接着信頼性を向上すること
ができる。The needle-like copper plating film 25 formed by the above-described process is exposed on the bottom surface of the cavity 24 and becomes the mounting surface of the semiconductor chip 28. The needle-like copper plating film 25 has a greater strength of the needle-like protrusions on the surface and is less likely to be broken than the conventional cupric oxide film. Therefore, a sufficient anchor effect by the needle-like projections can be obtained, the bonding strength of the semiconductor chip 28 can be sufficiently increased, and the bonding reliability of the semiconductor chip 28 can be improved.
【００１９】尚、上記実施形態（１）では、金属板２２
の下面全体に針状銅めっき被膜２５を形成したが、キャ
ビティ２４の底面のみに部分的に針状銅めっき被膜を形
成するようにしても良く、要は、少なくとも半導体チッ
プ２８をダイボンディングする部分に針状銅めっき被膜
を形成すれば良い。In the embodiment (1), the metal plate 22
Although the needle-like copper plating film 25 is formed on the entire lower surface of the cavity 24, the needle-like copper plating film may be partially formed only on the bottom surface of the cavity 24, that is, at least the portion where the semiconductor chip 28 is die-bonded. A needle-shaped copper plating film may be formed on the substrate.
【００２０】以上説明した実施形態（１）では、放熱ス
ラグ２１を２枚の金属板２２，２３を積層して構成した
が、図３に示す本発明の実施形態（２）のように、１枚
の金属板から放熱スラグ３１を形成し、この放熱スラグ
３１の下面側中央部分にキャビティ３２を切削加工又は
鍛造により形成するようにしても良い。この場合も、放
熱スラグ３１のうちの少なくともキャビティ３２底面
に、次亜リン酸塩を還元剤とする無電解銅めっきにより
針状銅めっき被膜２５を形成すれば、前記実施形態
（１）と同じ効果を得ることができる。In the embodiment (1) described above, the heat dissipation slag 21 is formed by laminating two metal plates 22 and 23. However, as in the embodiment (2) of the present invention shown in FIG. The heat dissipating slag 31 may be formed from a single metal plate, and the cavity 32 may be formed in the central portion on the lower surface side of the heat dissipating slag 31 by cutting or forging. In this case as well, the needle-like copper plating film 25 is formed on at least the bottom surface of the cavity 32 of the heat-dissipating slag 31 by electroless copper plating using hypophosphite as a reducing agent. The effect can be obtained.
【００２１】また、図４に示す本発明の実施形態（３）
のように、１枚の金属板から形成した放熱スラグ３５の
中央部を凹状にプレス成形することで、キャビティ３６
を形成するようにしても良い。この場合も、放熱スラグ
３５のうちの少なくともキャビティ３６底面に、次亜リ
ン酸塩を還元剤とする無電解銅めっきにより針状銅めっ
き被膜３７を形成すれば、前記実施形態（１）と同じ効
果を得ることができる。更に、放熱スラグ３５の下面全
体に針状銅めっき被膜３７を形成すれば、放熱スラグ３
５とプラスチック回路基板２６との接合部にも針状銅め
っき被膜３７が存在し、そのアンカー効果によりプラス
チック回路基板２６の接着強度も高めることができる。The embodiment (3) of the present invention shown in FIG.
By pressing the central part of the heat radiation slag 35 formed of one metal plate into a concave shape as shown in FIG.
May be formed. Also in this case, the needle-like copper plating film 37 is formed on at least the bottom surface of the cavity 36 of the heat dissipating slag 35 by electroless copper plating using hypophosphite as a reducing agent. The effect can be obtained. Further, if the acicular copper plating film 37 is formed on the entire lower surface of the heat dissipation slag 35, the heat dissipation slag 3
A needle-shaped copper plating film 37 also exists at the joint between the plastic circuit board 5 and the plastic circuit board 26, and the adhesive strength of the plastic circuit board 26 can be increased by the anchor effect.
【００２２】また、図５に示す本発明の実施形態（４）
のように、１枚の金属平板から形成した放熱スラグ３８
の下面に、キャビティ３９の開口を有するプラスチック
回路基板２６を接着することで、キャビティ３９を形成
するようにしても良い。この場合も、放熱スラグ３８の
うちの少なくともキャビティ３９底面に、次亜リン酸塩
を還元剤とする無電解銅めっきにより針状銅めっき被膜
４０を形成すれば、前記実施形態（１）と同じ効果を得
ることができる。更に、上記実施形態（４）と同じく、
放熱スラグ３８の下面全体に針状銅めっき被膜４０を形
成すれば、放熱スラグ３８とプラスチック回路基板２６
との接合部にも針状銅めっき被膜４０が存在し、そのア
ンカー効果によりプラスチック回路基板２６の接着強度
も高めることができる。FIG. 5 shows an embodiment (4) of the present invention.
The heat dissipating slag 38 formed from one metal flat plate
The cavity 39 may be formed by bonding the plastic circuit board 26 having the opening of the cavity 39 to the lower surface of the substrate. Also in this case, the needle-like copper plating film 40 is formed on at least the bottom surface of the cavity 39 of the heat radiation slag 38 by electroless copper plating using hypophosphite as a reducing agent. The effect can be obtained. Further, as in the above embodiment (4),
If the acicular copper plating film 40 is formed on the entire lower surface of the heat dissipation slag 38, the heat dissipation slag 38 and the plastic circuit board 26
The needle-like copper plating film 40 is also present at the junction with the plastic circuit board 26, and the adhesive strength of the plastic circuit board 26 can be increased by the anchor effect.
【００２３】尚、上記実施形態（２）〜（４）におい
て、図１に示す実施形態（１）と実質的に同一の部分に
は、同一符号を付して説明を省略する。In the above embodiments (2) to (4), substantially the same parts as those in the embodiment (1) shown in FIG.
【００２４】[0024]
【発明の効果】以上の説明から明らかなように、本発明
の請求項１によれば、放熱スラグのうちの少なくとも半
導体チップをダイボンディングする部分に、表面に無数
の強靱な針状突起を有する針状銅めっき被膜を形成した
ので、放熱スラグのキャビティ底面と半導体チップとの
接着強度を十分に高めることができ、半導体チップの接
着信頼性を向上することができる。As is apparent from the above description, according to the first aspect of the present invention, at least the portion of the heat dissipation slag to which the semiconductor chip is die-bonded has numerous tough needle-like projections on the surface. Since the acicular copper plating film is formed, the adhesive strength between the cavity bottom of the heat dissipation slag and the semiconductor chip can be sufficiently increased, and the adhesive reliability of the semiconductor chip can be improved.
【００２５】更に、請求項２では、針状銅めっき被膜
を、次亜リン酸塩を還元剤とする無電解銅めっきにより
形成するようにしたので、良質の針状銅めっき被膜を比
較的短時間で形成でき、半導体チップの接着信頼性と共
に生産性も向上できる。しかも、ホルマリン等の環境を
汚染する薬品を含まないので、近年の重要な技術的課題
である環境問題をクリアすることができ、人体に対する
安全性も高い。Further, according to the present invention, the acicular copper plating film is formed by electroless copper plating using hypophosphite as a reducing agent. It can be formed in a short time, and the productivity as well as the bonding reliability of the semiconductor chip can be improved. Moreover, since it does not contain chemicals that contaminate the environment such as formalin, environmental problems, which are important technical problems in recent years, can be cleared, and the safety for the human body is high.
【図１】本発明の実施形態（１）を示すキャビティダウ
ン型ＢＧＡパッケージの縦断面図FIG. 1 is a longitudinal sectional view of a cavity-down type BGA package showing an embodiment (1) of the present invention.
【図２】無電解銅めっきのプロセスを示す工程図FIG. 2 is a process diagram showing a process of electroless copper plating.
【図３】本発明の実施形態（２）を示すキャビティダウ
ン型ＢＧＡパッケージの縦断面図FIG. 3 is a longitudinal sectional view of a cavity-down type BGA package showing an embodiment (2) of the present invention.
【図４】本発明の実施形態（３）を示すキャビティダウ
ン型ＢＧＡパッケージの縦断面図FIG. 4 is a longitudinal sectional view of a cavity-down type BGA package showing an embodiment (3) of the present invention.
【図５】本発明の実施形態（４）を示すキャビティダウ
ン型ＢＧＡパッケージの縦断面図FIG. 5 is a longitudinal sectional view of a cavity-down type BGA package showing an embodiment (4) of the present invention.
【図６】従来のキャビティダウン型ＢＧＡパッケージの
縦断面図FIG. 6 is a longitudinal sectional view of a conventional cavity-down type BGA package.
２１…放熱スラグ、２２，２３…金属板、２４…キャビ
ティ、２５…針状銅めっき被膜、２６…プラスチック回
路基板、２７…半田ボール、２８…半導体チップ、２９
…ボンディングワイヤ、３０…封止樹脂、３１…放熱ス
ラグ、３２…キャビティ、３３…針状銅めっき被膜、３
５…放熱スラグ、３６…キャビティ、３７…針状銅めっ
き被膜、３８…放熱スラグ、３９…キャビティ、４０…
針状銅めっき被膜。Reference numeral 21: heat dissipating slag, 22, 23: metal plate, 24: cavity, 25: acicular copper plating film, 26: plastic circuit board, 27: solder ball, 28: semiconductor chip, 29
... bonding wire, 30 ... sealing resin, 31 ... heat dissipation slag, 32 ... cavity, 33 ... acicular copper plating film, 3
5: heat dissipation slag, 36: cavity, 37: acicular copper plating film, 38: heat dissipation slag, 39: cavity, 40 ...
Needle-like copper plating film.
Claims (2)
ク回路基板を接着すると共に、前記放熱スラグの下面側
に形成されたキャビティに半導体チップをダイボンディ
ングして封止樹脂で封止し、前記プラスチック回路基板
の下面に多数の半田ボールを配列して成るキャビティダ
ウン型ＢＧＡパッケージにおいて、 前記放熱スラグのうちの少なくとも前記半導体チップを
ダイボンディングする部分に針状銅めっき被膜が形成さ
れていることを特徴とするキャビティダウン型ＢＧＡパ
ッケージ。1. A plastic circuit board is bonded to a lower surface of a metal heat dissipation slag, and a semiconductor chip is die-bonded to a cavity formed on a lower surface side of the heat dissipation slag and sealed with a sealing resin. In a cavity-down type BGA package having a large number of solder balls arranged on a lower surface of a circuit board, a needle-like copper plating film is formed on at least a portion of the heat dissipation slag where the semiconductor chip is die-bonded. Cavity down type BGA package.
を還元剤とする無電解銅めっきにより形成されているこ
とを特徴とする請求項１に記載のキャビティダウン型Ｂ
ＧＡパッケージ。2. The cavity-down mold B according to claim 1, wherein the acicular copper plating film is formed by electroless copper plating using hypophosphite as a reducing agent.
GA package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9256954A JPH1197568A (en) | 1997-09-22 | 1997-09-22 | Cavity-down type bga package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9256954A JPH1197568A (en) | 1997-09-22 | 1997-09-22 | Cavity-down type bga package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1197568A true JPH1197568A (en) | 1999-04-09 |
Family
ID=17299680
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9256954A Pending JPH1197568A (en) | 1997-09-22 | 1997-09-22 | Cavity-down type bga package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1197568A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100390453B1 (en) * | 1999-12-30 | 2003-07-04 | 앰코 테크놀로지 코리아 주식회사 | semiconductor package with such circuit board and method for fabricating the same |
| US6740959B2 (en) * | 2001-08-01 | 2004-05-25 | International Business Machines Corporation | EMI shielding for semiconductor chip carriers |
| TWI462194B (en) * | 2011-08-25 | 2014-11-21 | Chipmos Technologies Inc | Semiconductor package structure and manufacturing method thereof |
-
1997
- 1997-09-22 JP JP9256954A patent/JPH1197568A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100390453B1 (en) * | 1999-12-30 | 2003-07-04 | 앰코 테크놀로지 코리아 주식회사 | semiconductor package with such circuit board and method for fabricating the same |
| US6740959B2 (en) * | 2001-08-01 | 2004-05-25 | International Business Machines Corporation | EMI shielding for semiconductor chip carriers |
| TWI462194B (en) * | 2011-08-25 | 2014-11-21 | Chipmos Technologies Inc | Semiconductor package structure and manufacturing method thereof |
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