JPH0983831A - Synchronizing signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the missing of a synchronizing signal by generating a field synchronizing signal with a vertical synchronizing signal of a field when the number of lines of the field is decreased more than a standard line number. SOLUTION: A field synchronizing signal generating circuit 2 starts count at the edge of a vertical synchronizing signal from a synchronizing separator circuit for each field and generates a field synchronizing signal of a succeeding field after 259.5H and it is sent to a field synchronizing signal output circuit 5 via a field synchronizing signal selection circuit 4. Succeeding count is started at the edge of a vertical synchronizing signal of the field. A non-standard discrimination circuit 3 counts the number of input lines for a period from the edge of a vertical synchronizing signal till an edge of a succeeding vertical synchronizing signal and when the period is less than 259.9H, a signal representing non-standard is sent to the field synchronizing signal selection circuit 4. In this case. The field synchronizing signal selection circuit 4 sends the edge of the vertical synchronizing signal to the field synchronizing signal output circuit 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing signal processing device in a recording / reproducing device such as a video tape recorder.

[0002]

2. Description of the Related Art Conventionally, a horizontal sync signal and a vertical sync signal are separated from a composite sync signal included in an input video signal to generate a field sync signal, and a video signal synchronized with the field sync signal is output. There is a synchronous signal processing device having a configuration as shown in FIG. An example of a 525 line / 60 field system will be described below with reference to the timing chart of FIG. The timing chart of FIG. 8 shows the timing of each synchronization signal in the first and second fields when a standard type video signal having 262.5H lines per field is input. First, the sync separation circuit 1 extracts the horizontal sync signal (HSYNC1) and the vertical sync signal (VSYNC) from the composite sync signal (CSYNC1) included in the input video signal of the first field.
C1) is separated and these horizontal synchronization signals (HSYNC
1) and the vertical sync signal (VSYNC1) are output to the field sync signal generation circuit 2.

The field synchronization signal generation circuit 2 counts the number of clocks of the horizontal synchronization signals (HSYNC1 to 2) with the falling edge of the vertical synchronization signal (VSYNC1) as a base point, and thereby the vertical synchronization signal (VSYNC1).
259.5 H (H: 1 horizontal scanning period) from the falling edge of the field, the sync pulse of the field sync signal (FSYNC2) is generated (dashed line arrow in FIG. 8) and output to the sync signal output circuit 5. This field synchronization signal (FSY
The sync pulse of NC2) indicates the start of the second field. Similarly, the vertical synchronizing signal (VS) of the second field separated from the video signal of the second field.
259.5 from the falling edge of YNC2)
After H, a sync pulse of the field sync signal (FSYNC1) indicating the start of the first field of the subsequent frame is generated (dotted line arrow in FIG. 8). That is, the sync pulse of the field sync signal of each field is generated with the falling edge of the vertical sync signal of the previous field as the base point on the time axis.

The number of clocks of the horizontal synchronizing signal in the field synchronizing signal generating circuit 2 is counted by a counting circuit incorporated in the field synchronizing signal generating circuit 2. The counting number of this counting circuit is the vertical synchronizing of each field. It is reset by the falling edge of the signal. Therefore, this counting circuit counts up in accordance with the clock of the horizontal synchronizing signal with the falling edge of the vertical synchronizing signal as a base point, is reset by the vertical synchronizing signal of the subsequent field, and newly starts counting for each field. The field sync signal generation circuit 2 outputs a sync pulse of the field sync signal when the count number of the counting circuit reaches 259.5H. Therefore, since the falling edge of the vertical synchronizing signal is delayed by 3H from the beginning of the field, 2
As long as the standard type video signal having the number of lines of 62.5H is input, as shown in FIG. 8, the sync pulse of the field sync signal exists at the beginning of each field, and the ideal field sync signal is obtained. Can be obtained.

The field synchronization signal output circuit 5 sufficiently amplifies the input field synchronization signal by current and outputs it to the signal processing circuit in the subsequent stage without any discrepancies in signal timing and signal level. The video signal timing adjustment circuit 6 adjusts the timing of the input video signal so as to synchronize with the output field synchronization signal. The video signal output circuit 7, like the field synchronization signal output circuit 5,
The input video signal is sufficiently current-amplified and output to the signal processing circuit in the subsequent stage without discrepancies in signal timing and signal level.

[0006]

As described above, in the conventional synchronizing signal processing device, the vertical synchronizing signal is used as the base point on the time axis to be 259.5H, that is, the field synchronization of the succeeding field after one field. Due to the generation of the synchronizing pulse of the signal, the number of lines per field of the input video signal is the same as the number of standard signal lines (262.5H) as in the fast-forward reproduction of the VHS system VTR. On the other hand, if it is decreasing,
There is a problem that the sync pulse of the field sync signal indicating the start of the subsequent field is missing, and the operation of the sync signal system of the signal processing circuit at the subsequent stage for inputting this is broken.

The reason why the sync pulse of the field sync signal is missing is explained by taking the case where the field sync signal (FSYNC2) of the second field shown in FIG. 8 is generated based on the vertical sync signal (VSYNC1) of the first field. explain. As described above, the field sync signal generation circuit 2 can obtain the ideal field sync signal (FSYNC2) as long as the standard video signal having the number of lines of 262.5H is input.

However, when the number of lines per field is less than 259.5H, the count circuit built in the field synchronization signal generation circuit 2 has a count number of 25.
Vertical sync signal (VSYNC2) before reaching 9.5H
Will be reset by. Therefore, the sync pulse of the field sync signal (FSYNC2) is not output, and the sync pulse of the field sync signal (FSYNC2) is lost. Further, when the number of lines per field is equal to 259.5H, the counting circuit built in the field synchronization signal generation circuit 2 is 259.5H.
Are reset by the vertical synchronization signal (VSYNC2) at the same timing as the timing of counting. Therefore, in this case, there are cases where the sync pulse of the field sync signal (FSYNC2) is generated and a case where the sync pulse is missing depending on the context of these timings.

As described above, according to the conventional synchronizing signal processing device, when the number of lines per field is in a state of being reduced with respect to the number of lines (262.5H) included in the standard type video signal, There is a problem that the sync pulse of the field sync signal indicating the start of the subsequent field may be lost, and the operation of the signal processing circuit at the subsequent stage for inputting the field sync signal may be broken. The present invention has been made in view of the above problems, and it is possible to start a field even when the number of lines per field of an input video signal is smaller than the number of lines of a standard video signal. It is an object of the present invention to provide a synchronization signal processing device which does not cause a loss of the synchronization pulse of the field synchronization signal shown and does not cause a failure in the operation of the signal processing circuit in the subsequent stage.

[0010]

In order to solve the above-mentioned problems, the present invention has the following arrangement. According to another aspect of the present invention, there is provided a sync signal processing device, wherein a sync signal separating means for separating a horizontal sync signal and a vertical sync signal from a composite sync signal superimposed on an input video signal, and time based on the vertical sync signal. Field sync signal generating means for generating an axial reference field sync signal, and standard / non-standard for judging whether the input video signal is a standard type or a non-standard type based on the horizontal sync signal and the vertical sync signal. Signal discriminating means, field synchronizing signal selecting means for selecting either the field synchronizing signal or the vertical synchronizing signal based on the discrimination result in the standard / non-standard signal discriminating means, and selection by the field synchronizing signal generating means. A field synchronization signal output means for outputting either the field synchronization signal or the vertical synchronization signal thus generated, Timing of the signal to the input video signal so as to be time-synchronized with either the field synchronization signal or the vertical synchronization signal selected by the field synchronization signal generation means and output from the field synchronization signal output means. The video signal timing adjusting means for adjusting and the video signal outputting means for outputting the output video signal whose timing is adjusted by the timing adjusting means are provided.

According to a second aspect of the present invention, there is provided the synchronization signal processing device according to the first aspect, wherein the field synchronization signal selecting means determines that the standard / non-standard signal determining means determines the input video signal as a standard type. The field sync signal is selected, and the vertical / sync signal is selected when the standard / non-standard signal determining means determines that the input video signal is a non-standard type.

According to a third aspect of the present invention, in the synchronizing signal processing device, the standard / non-standard signal discriminating means according to the first aspect of the invention is such that the number of lines (n) per field of the input video signal is a standard line. When the inequality of n> N-3 is satisfied with respect to the number (N), the input video signal is determined to be the standard type, and when the inequality of n≤N-3 is satisfied, the input video signal is determined to be the non-standard type. Is configured to.

According to the sync signal processing device of the present invention, the field sync signal generating means separates the horizontal sync signal and the vertical sync signal from the input video signal, These sync signals are given to the field sync signal generating means and the standard / non-standard signal discriminating means. The field synchronization signal generation means generates a field synchronization signal serving as a reference on the time axis based on the input vertical synchronization signal, and supplies this to the field synchronization signal selection means together with the vertical synchronization signal. Further, the standard / non-standard signal discriminating means counts the number of lines (n) for each field of the input video signal based on the input horizontal synchronizing signal and vertical synchronizing signal, and n with respect to the standard number of lines (N). > N−3 inequality is satisfied, the input video signal is discriminated as a standard type, and n ≦
When the inequality N-3 is satisfied, the input video signal is discriminated as a non-standard type. The field synchronization signal selection means selects the field synchronization signal when the input video signal is the standard type, and when the input video signal is the non-standard type, based on the discrimination result of the standard / non-standard signal discrimination means. Selects the vertical sync signal. The field synchronization signal output means inputs and outputs the signal selected by the field synchronization signal selection means. On the other hand, the video signal timing adjusting means performs timing processing on the input video signal so that the output video signal is temporally synchronized with the signal (field sync signal or vertical sync signal) output from the field sync signal output means. The video signal output means outputs the input video signal subjected to the timing processing by the video signal timing adjusting means as an output video signal.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION A synchronizing signal processing apparatus according to the present invention determines whether an input video signal is a standard type or a non-standard type,
The process of generating the field sync signal is changed based on the result of this determination. Hereinafter, an embodiment of a synchronization signal processing device of the present invention will be described in detail with reference to FIGS. 1 to 6, taking a 525 line / 60 field system as an example. First, the operation when a video signal having 260.5 lines per field is input will be described with reference to FIGS. 1 and 2. FIG. 1 is a block diagram showing the structure of a synchronization signal processing device according to the present invention, and FIG. 2 shows the number of lines per field is 26.
It is a timing chart in case of 0.5. 1, the same components as those of the conventional synchronization signal processing device shown in FIG. 7 are designated by the same reference numerals, and detailed description thereof will be omitted. The difference from the conventional sync signal processing device shown in FIG. 7 is that either the field sync signal or the vertical sync signal input from the field sync signal generation circuit 2 under the control of a standard / non-standard signal discrimination circuit 3 described later. Field synchronization signal selection circuit 4 which selects and supplies to the field synchronization signal output circuit 5 and a standard for controlling the selection operation of the field synchronization signal selection circuit 4 based on the vertical synchronization signal and the horizontal synchronization signal input from the synchronization separation circuit 1. / A nonstandard signal discriminating circuit 3 is provided.

The field sync signal generation circuit 2 is based on the horizontal sync signal and the vertical sync signal input from the sync separation circuit 1 and is based on the vertical sync signal (VSYNC) of the first field.
25 with the falling edge of 1) as the base point on the time axis
After 9.5H, a sync pulse of the field sync signal (FSYNC2) indicating the start of the second field is generated (the one-dot chain line arrow in FIG. 2). Further, the field synchronization signal generation circuit 2 uses the vertical synchronization signal (VSYN) of the second field.
25 with the falling edge of C2) as the base point on the time axis
After 9.5H, the sync pulse of the field sync signal (FSYNC1) is generated (dotted line arrow in FIG. 2). The sync pulse generated with the falling edge of the vertical sync signal (VSYNC2) of the second field as the base point on the time axis becomes the sync pulse of the field sync signal indicating the start of the first field in the subsequent frame. Less than,
Similarly, the field sync signal pulse of the subsequent field is generated with the falling edge of the vertical sync signal in the previous field of each field as a reference on the time axis, and the field sync signal generation circuit 2 combines the vertical sync signal with the vertical sync signal. And outputs the field sync signal to the field sync signal selection circuit 4.

The standard / non-standard discriminating circuit 3 sets the counting period of the number of lines of one field from the falling edge of the vertical synchronizing signal to the falling edge of the next vertical synchronizing signal.
The number of clocks (the number of falling edges) of the horizontal synchronizing signal input during this period is counted, and whether the input video signal is the standard type or the non-standard type is determined based on the counting result. Here, assuming that the number of lines for each field of the input video signal is n and the number of standard lines is N, the standard / non-standard discriminating circuit 3 determines that the input video is input when the discriminant (1) is satisfied. Determine the signal as non-standard. That is, since the number of lines in one field of the standard type video signal is 262.5H, when the number of clocks of the horizontal synchronizing signal per field is reduced to 259.5H or less, the input video signal is nonstandard. Judge as a signal. On the contrary, 259.
If it exceeds 5H, it is determined to be a standard signal. In FIG. 2, the number of lines in the first field of the video signal is 260.
Since it is 5H, in this case, the standard / non-standard discrimination circuit 3
Determines that the video signal input by the discriminant equation (1) is a standard type.

N ≦ N-3 (1)

The field synchronization signal selection circuit 4 is standard /
If the input video signal is a standard type based on the discrimination result in the non-standard discrimination circuit 3, the field synchronization signal given from the field synchronization signal generation circuit 2 is selected, and the input video signal is selected. Is a non-standard type, a vertical sync signal is selected and this is output as a field sync signal. In the case of FIG. 2, as described above, the standard / non-standard discriminating circuit 3 discriminates the video signal of the first field inputted by the discriminant (1) as the standard type. Based on this determination result, the field synchronization signal selection circuit 4
Selects the field sync signal supplied from the field sync signal generation circuit 2.

Then, in the second field, the counting circuit built in the field synchronization signal generating circuit 2 is 259.
When 5H is counted, a sync pulse indicating the start of the second field is generated with a delay of 2H from the original start position of the second field. This counting circuit is 259.5.
After 1H after counting H, the vertical synchronization signal (VSYNC
It is reset by 2). In this case, the sync pulse of the field sync signal (FSYNC2) indicating the start of the field is generated with a delay of 2H from the original ideal position, but is lost due to the decrease in the number of lines per field. There is no. Similarly, in the same figure, since the number of lines in the second field is also 260.5H, the sync pulse of the field sync signal (FSYNC1) indicating the start of the first field of the subsequent frame is also generated without omission.

Next, the number of lines per field is 2
The operation when the video signals of 59.5H and 258.5H are input will be described with reference to FIGS. 3 and 4. 3 is a timing chart when the number of lines per field is 259.5, and FIG. 4 is a timing chart when the number of lines per field is 258.5. As shown in FIGS. 3 and 4, the number of lines per field is 259.5H and 258.5H.
When the video signal of 1 is input, the standard / non-standard discriminating circuit 3 discriminates the input video signal as a non-standard signal based on the discriminant (1). Then, the field synchronization signal selection circuit 4 uses the vertical synchronization signal (VSYNC1) as the field synchronization signals of the first and second fields, respectively.
And a vertical sync signal (VSYNC2) are selected and output as a field sync signal (FSYNC1) and a field sync signal (FSYNC2), respectively (thick arrows in FIGS. 3 and 4).

In this case, the field synchronization signal (FSYN
Since the sync pulse of (C1, FSYNC2) is generated from the vertical sync signals (VSYNC1, VSYNC2) in the same field, it is generated by 3H behind the original ideal position, but the field sync signal generation circuit 2
Irrespective of whether or not the counting circuit incorporated therein can count 259.5H, the sync pulse of the field sync signal can be generated and will not be lost due to the decrease in the number of lines per field.

By the way, as described above, the standard / non-standard signal discrimination circuit 3 is set so that the discrimination of the video signal is performed based on the discrimination formula (1). The reason for setting the discriminant in this way will be described below in an unreasonable manner with reference to FIGS. 5 and 6. First, the operation when the discriminant (2) of the video signal in the standard / non-standard discriminating circuit 3 is set and a video signal having 260.5 lines per field is input will be described with reference to FIG. To do. In FIG. 5, the number of lines per field is 260.
6 is a timing chart in the case of 5.

N≤N-2 (2)

The standard / non-standard discriminator circuit 3 has a discriminant equation (2).
Therefore, the number of horizontal sync signals per field is 26
When it is reduced to 0.5 or less, the input video signal is discriminated as a non-standard signal. On the contrary, when it exceeds 260.5, it is determined to be a standard signal. So, in this case,
The input video signal is 260.5 per field.
Since it has the number of lines, it is discriminated as a non-standard signal. Based on the determination result of the standard / non-standard determination circuit 3, the field synchronization signal selection circuit 4 selects the vertical synchronization signals (VSYNC1, VSYNC2) separated from the input video signal and selects the field synchronization signals (FSYNC1, FSYNC).
2) (the thick arrow in FIG. 5).

As described above, the waveform of the field synchronization signal when generated by using the discriminant (2) (FIG. 5) and the waveform of the field synchronization signal when generated by using the discriminant (1) (FIG. 2). Comparing with, the waveform of the field sync signal generated using the discriminant (2) is delayed by 1H with respect to the waveform of the field sync signal generated using the discriminant (1). The waveform of the field synchronization signal generated using this discriminant (1) (FIG. 2) itself is delayed by 2H from the original ideal start position of the field, but the discriminant (2) should be used. As a result, there is a problem that the delay is further increased. Then the standard /
The operation when the discriminant (3) of the video signal in the non-standard discrimination circuit 3 is set and the video signal in which the number of lines per field is 259.5 is input will be described with reference to FIG. FIG. 6 is a timing chart when the number of lines per field is 259.5.

N ≦ N-4 (3)

The standard / non-standard discriminating circuit 3 is a discriminant (3).
Therefore, the number of horizontal sync signals per field is 25
When it is reduced to 8.5 or less, the input video signal is discriminated as a non-standard signal. On the contrary, when it exceeds 258.5, it is determined to be a standard signal. So, in this case,
The input video signal is 259.5 per field.
Since it has the number of lines, the discriminant equation (3) is not satisfied and the signal is discriminated as a standard signal. Based on the discrimination result of the standard / non-standard discrimination circuit 3, the field synchronization signal selection circuit 4 tries to select and output the field synchronization signal output from the field synchronization signal generation circuit 2.

However, the timing when the counting circuit that counts the number of clocks of the horizontal synchronizing signal with the vertical synchronizing signal of the previous field as the base point tries to count 259.5H, and the timing when this counting circuit is reset by the vertical synchronizing signal. Are overlapped with each other, this counting circuit is 259.
There are cases where 5H can be counted and cases where it cannot be counted. As a result, there are cases where a field sync signal pulse is generated with the falling edge of the vertical sync signal of the previous field as a reference on the time axis, and a case where the field sync signal pulse is missing. As can be understood from the above description, the standard / non-standard discriminating circuit 3 discriminates (1)
By using the formula, the most harmonious field sync signal can be obtained.

By the above series of operations, field synchronization is performed even when the number of lines per field of the video signal is smaller than the number of lines of the standard signal such as fast-forward reproduction of VHS system VTR. An extremely stable circuit operation can be performed without the loss of the signal synchronization pulse and without the operation of the signal processing circuit in the subsequent stage breaking down.

[0030]

According to the synchronizing signal processing device of the first and second aspects of the invention, the number of lines per field is different from the number of lines included in the standard signal as in the fast-forward reproduction of the VHS system VTR. Even in the case where the number of fields is decreased, the field sync signal is not lost, and the operation of the signal processing circuit in the subsequent stage does not break down, and stable circuit operation can be realized.

According to the synchronizing signal processing device of the third aspect of the present invention, a more harmonious field synchronizing signal can be obtained than the synchronizing signal processing device of the first and second aspects of the invention. Therefore, the operation of the signal processing circuit in the subsequent stage does not break down, and extremely stable circuit operation can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a structure of a synchronization signal processing device according to an exemplary embodiment of the present invention.

FIG. 2 is a timing chart for explaining an operation of the synchronization signal processing device according to the exemplary embodiment of the present invention when a video signal having 260.5 lines per field is input.

FIG. 3 is a timing chart for explaining the operation of the synchronization signal processing device according to the exemplary embodiment of the present invention when a video signal having 259.5 lines per field is input.

FIG. 4 is a timing chart for explaining the operation of the synchronization signal processing device according to the exemplary embodiment of the present invention when a video signal in which the number of lines per field is 258.5 is input.

FIG. 5 is a timing chart for explaining the operation of the synchronization signal processing device according to the exemplary embodiment of the present invention when a video signal having 260.5 lines per field is input.

FIG. 6 is a timing chart for explaining the operation of the synchronization signal processing device according to the exemplary embodiment of the present invention when a video signal in which the number of lines per field is 259.5 is input.

FIG. 7 is a block diagram showing a structure of a conventional synchronization signal processing device.

FIG. 8 is a timing chart for explaining the operation of the conventional synchronization signal processing device.

[Explanation of symbols]

 1 sync separation circuit 2 field sync signal generation circuit 3 standard / non-standard signal discrimination circuit 4 field sync signal selection circuit 5 field sync signal output circuit 6 video signal timing adjustment circuit 7 video signal output circuit

Claims (3)

[Claims] 1. A sync signal separating means for separating a horizontal sync signal and a vertical sync signal from a composite sync signal superimposed on an input video signal, and a field sync signal serving as a reference on a time axis based on the vertical sync signal. And a standard / non-standard signal discriminating means for discriminating whether the input video signal is a standard type or a non-standard type based on the horizontal synchronizing signal and the vertical synchronizing signal. Field sync signal selecting means for selecting either the field sync signal or the vertical sync signal based on the result of the judgment by the standard signal judging means, and the field sync signal or the vertical signal selected by the field sync signal generating means. The field synchronization signal output means for outputting either one of the synchronization signals and the output video signal are the field synchronization signal generation means. Video signal timing adjustment for adjusting the timing of the input video signal so as to be temporally synchronized with either the field synchronization signal or the vertical synchronization signal selected by the generation means and output from the field synchronization signal output means. And a video signal output means for outputting the output video signal whose timing is adjusted by the timing adjusting means. 2. The field synchronization signal selection means is standard /
When the non-standard signal discriminating means discriminates the input video signal as the standard type, the field synchronizing signal is selected, and when the standard / non-standard signal discriminating means discriminates the input video signal as the non-standard type, the vertical synchronizing signal is selected. 2. The synchronization signal processing device according to claim 1, wherein the synchronization signal processing device is selected. 3. The standard / non-standard signal discriminating means inputs the input video signal when the number of lines (n) for each field satisfies the inequality of n> N-3 with respect to the standard number of lines (N). 2. The synchronization signal processing device according to claim 1, wherein the video signal is discriminated as a standard type and the input video signal is discriminated as a non-standard type when the inequality of n ≦ N−3 is satisfied.