JPH0981390A - Program downloading system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a device from stopping by storing a 2nd storage device with a program which controls a downloading processing, a program which controls the operation of the device, and a program to be downloaded, and controlling the device during the downloading processing according to the program in the 2nd storage device. SOLUTION: A control circuit 300 detects the program to be downloaded being prepared in the 2nd storage device 120 and then performs control for downloading the program to the 2nd storage device 120 to a 1st storage device 110. The control circuit 300 downloads the program and controls the 2nd device 20 according to the program stored in the 2nd storage device 120. If a command is received from the 1st device 10 during the downloading processing, the downloading processing is interrupted and the command is executed; when the execution is completed, the downloading processing is carried on and after the processing ends, the device 20 is controlled with the program downloading to the 1st storage device 110.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program download system for downloading a program to a second device which operates according to an instruction from the first device.

For example, an input / output control device (hereinafter referred to as an I / O control device) controlled by a central control device of an electronic exchange is controlled and operated by firmware stored in its own memory. There is a demand for a program download method capable of executing such a change in the firmware of the I / O control device without stopping the I / O control device.

[0003]

2. Description of the Related Art FIG. 11 is a block diagram for explaining a conventional example. The figure shows an I / O controller 20A controlled by a central controller 10A of an electronic exchange.

Reference numeral 310 in the figure is a microprocessor for controlling the I / O control unit 20A, and 111 is an I / O.
A flash ROM that stores a program that controls the control device 20A, a memory card 121 that stores a program that downloads, 13
Reference numeral 1 is a memory card flag detection unit that detects a memory card flag that indicates that the memory card 121 has been set, and 400 is an interface that interfaces with the central controller 10A.

In the configuration shown in the figure, the I / O controller 20A
Operates according to a program stored in the flash ROM 111. When this program is revised and the I / O controller 20A is operated by the new program, the memory card 12 storing the new program
1 is attached to the I / O control device 20A.

The microprocessor 310 periodically monitors the output of the memory card flag detecting section 131 to monitor whether or not the memory card 121 is attached.

When the microprocessor 310 detects from the output of the memory card flag detector 131 that the memory card 121 has been installed, it sets the download mode and puts the I / O controller 20A in the Out Of Service state. , Memory card 121 to flash ROM
The program is downloaded to 111.

[0008]

In the above-mentioned conventional example, I
When the memory card 121 is attached to the / O control device 20A, the memory card flag is set, and the microprocessor 310 detects this, thereby entering the download mode.

At this time, even if, for example, a data output command arrives from the central control unit 10A, the I / O control unit 20A cannot accept the command because it is in the process of downloading the program. The central controller 10A is notified that the command cannot be accepted.

The present invention provides a program download method capable of interrupting the download and processing the command when the second apparatus receives the command from the first apparatus even while the program is being downloaded. Try to make it happen.

[0011]

Means for Solving the Problems FIG. 1 is a block diagram for explaining the principle of the present invention.
The figure shows a second device 20 which operates according to commands from the first processing device 10.

Reference numeral 110 in the second device 20 is a first storage device for storing a program for controlling the operation of the second device 20, and 120 is a program to be downloaded to the first storage device 10 and download. Reference numeral 200 denotes a second storage device that stores a program that controls processing.
When it is detected that the program to be downloaded to the storage device 20 is prepared, a switching unit that switches the program for controlling the second device 20 to the program stored in the second storage device 120, and 300 is the first The control for detecting that the program to be downloaded to the second storage device 20 is prepared, issuing a program switching instruction to the switching unit 200, and downloading the program of the second storage device 120 to the first storage device 110. The control circuit 300 is a control circuit for
When it is detected that the program to be downloaded to the second storage device 120 is prepared, the program download and the control of the second device 20 are executed according to the program stored in the second storage device 120, and the first When the command from the device 10 is received, the download process is interrupted, the command from the first device 10 is executed, and when the command execution is completed, the download process is resumed and continued, and the download process ends. If you do
The control circuit 300 controls the second device 20 according to the program downloaded to the first storage device 110. (Claim 1) The second device 20, a microprocessor 310 for controlling the second device 20, a flash ROM 111 for storing a program for controlling the operation of the second device 20,
A program for downloading to the flash ROM 111, a memory card 121 for storing a program for controlling the download process, and a memory card flag detection for detecting a memory card flag set when the memory card 121 is attached to the second device 20. Part 131
The microprocessor 310 detects the memory card flag output from the memory card flag detection unit 131 and sets the download flag, which detects the download flag, and the microprocessor 310 detects the memory card flag and resets the software. Software reset detection unit 312 that detects that the operation has been performed
From the download flag detection output of the download flag detection unit 311 and the software reset detection output of the software reset detection unit 312, the flash ROM 1
11 and the memory card 121 are provided with an address allocation switching circuit 202. When the microprocessor 310 detects a memory card flag, the download flag is set, software is reset, and the address allocation switching circuit 202 causes the flash ROM 111. And the address of the memory card 121 are switched, and the memory card 121 is operated during the download process.
Control according to the download program of.
(Claim 2) The software reset detection unit 31 of the second device 20.
2 is configured by a reset circuit 313 that detects the rising edge of the download flag set by the microprocessor 312 and sends a hardware reset signal to the microprocessor 310 and the address allocation switching circuit 202, and the microprocessor 310 sets the memory card flag. When it is detected, the download flag is set, the reset circuit 313 detects the rising edge of the download flag, a hardware reset signal is generated, and the address allocation switching circuit 20 is generated by the hardware reset signal.
2 switches the addresses of the flash ROM 111 and the memory card 121, and performs control according to the download program of the memory card 121 during the download process. (Claim 3) Address allocation reset in which the microprocessor 310 detects the reset of the download flag reset at the end of the download and the reset output of the software reset detection unit 312 and restores the addresses of the flash ROM 111 and the memory card 121 to the original allocation. A circuit 204 is provided, and when the microprocessor 310 detects the memory card flag, the download flag is set, software is reset, and the address allocation switching circuit 202 switches the addresses of the flash ROM 111 and the memory card 121 to execute the download process. The microprocessor 310 detects the end of the download process and resets it. When the reset of the download flag is detected, the flash ROM 111 and the memory card 121 are reset. The dress is returned to the original layout, and the microprocessor 310 operates with the program stored in the flash ROM 111. (Claim 4) The memory card 121 of the second device 20, the memory card flag detection unit 131, the communication interface 500 for interfacing with the third device 30, and the program received through the communication interface 500 are accumulated. And a transfer completion detecting unit 510 that detects completion of transfer of the program from the third device 30 to the buffer memory 122 and sets a transfer completion flag, and the microprocessor 310 detects transfer completion. When the transfer completion flag set by the unit 510 is detected, the download flag is set, software is reset, and the address allocation switching circuit 202 switches the addresses of the flash ROM 111 and the memory card 121. 12
Control is performed according to the download program of 1. (Claim 5)

[0013]

FIG. 2 is a block diagram (1) for explaining the first embodiment of the present invention. The principle is the flash ROM 1 as the first storage device 110 explained in FIG.
11, a memory card 121 as a second storage device, a switching timing circuit 201 as a switching unit 200, an address allocation switching circuit 202, and a selector 203,
Further, as the control circuit 300, the microprocessor 31
It is composed of zero.

In the configuration shown in the figure, the address allocation switching circuit 202 is controlled by the switching timing circuit 201 which receives the outputs of the download flag detecting section 311 and the software reset detecting section 312 as input, and the selector 203 is a flash. A chip select signal for exchanging the address signals of the ROM 111 and the memory card 121 is generated.

The microprocessor 310 shown in the figure regularly monitors the output of the memory card flag detection unit 131, and when it detects that the flag has become "1", it sets the download flag for entering the download mode to " Set to 1 ”and reset the software.

The software reset detection unit 312 detects the restart address and notifies the switching timing circuit 201 that the software has been reset. The switching timing circuit 201 detects from the software reset detection output and the download flag "1", The address allocation switching circuit 202 is notified at a timing such that the address is switched after the access of the microprocessor 310 is completed.

The address allocation switching circuit 202 changes the address allocation of the memory by exchanging the memory card select signal and the flash ROM select signal generated by the higher address and passing the select signal to the flash ROM 111 and the memory card 121.

By this address change, the microprocessor 310 operates according to the program of the memory card 121. The microprocessor 310 is the memory card 12
According to the first download program, the program is downloaded from the memory card 121 to the flash ROM 111.

When a command from the second device 20 arrives from the first device 10 during the download, the download is stopped, the command from the first device 10 is executed, and then the download is performed again. Here, it is stored in the memory card 121 together with the program for executing the command from the first device 10 and the program for downloading.

FIG. 3 shows address allocation in the first embodiment of the present invention. (A) shows the address allocation during normal operation. RAM addresses from 0000 to 3FFF, memory cards from 4000 to 7FFF (MM in the figure).
An address (designated as CD) and 8000 to FFFF are assigned as flash (designated as F in the figure) ROM addresses, and the microprocessor 310 normally operates according to a program written in the flash ROM 111 at addresses 8000 to FFFF.

(B) is an address assignment switching circuit 202
The flash ROM 111 and the memory card 121
The following shows the address allocation after replacing the addresses of. Such address replacement is performed by, for example, b (bit) 14 = 1 at 4000 address and b15 = at 8000 address.
Since it is 1, it is possible to easily change the address allocation as shown in the figure by exchanging the address lines b14 and b15.

FIG. 4 is a block diagram (2) for explaining the first embodiment of the present invention. The configuration shown in the figure is obtained by adding an address allocation reset circuit 204 to the configuration described in FIG. 2, and is a circuit for resetting the address whose allocation has been switched by the address allocation switching circuit 202 to the original address.

The microprocessor 310 detects the end of the download and resets the download flag to "0", and the software reset detection section 312 detects the restart address and notifies the switching timing circuit 201 of the switching timing circuit. 201 takes a timing from the software reset and the download flag “0”, notifies the address allocation reset circuit 204, returns the addresses of the flash ROM 111 and the memory card 121 to the original allocation, and the microprocessor 310 is stored in the flash ROM 111. Works programmatically.

FIG. 5 is a flow chart of the first embodiment of the present invention. The operation of the first embodiment of the present invention shown in FIG. 4 will be described in more detail with reference to the steps (shown as S in the figure) of the flowchart.

S1: The microprocessor 310 periodically monitors the output of the memory card flag detector 131 (the memory card flag is shown as CDF in the figure). S2: It is determined whether or not the memory card flag has become "1". If it is not "1", the process returns to S1 to continue monitoring the memory card flag.

S3: When the memory card flag becomes "1", the microprocessor 310 resets the software and sets the download flag (shown as DLF in the drawing) to "1".

S4: It is detected whether or not the download flag has become "1", and if not "1", the monitoring of the download flag is continued. S5; When it is detected that the download flag has become "1", the switching timing circuit 201 takes a timing and sends a switching instruction signal to the address allocation switching circuit 202, and the address allocation switching circuit 202 receives from the selector 203. According to the chip select signal sent, the flash ROM 111 and the memory card 12
Change the connection of the designated address line 1 and change the address assignment.

S6: By changing the address allocation, the microprocessor 310 operates according to the program of the memory card 121.
Memory card 12 by the download program of 1
1 Download the specified program above.

S7: It is determined whether or not the download flag is "0" during the download process. If the download flag is "0", the process proceeds to S10. S8: The presence or absence of a command from another device, for example, the first device 10, is monitored during the download process.

S9: When a command from another device arrives, the command is executed, and when the command ends,
The process returns to S6 to continue the download process. S10: If the download flag is "0",
Now that the download is complete, reset the software.

S11: Address allocation reset circuit 20
At 4, the addresses of the flash ROM 111 and the memory card 121 are reset to the original allocation. S12: The program downloaded to the flash ROM 111 controls the second device 20.

FIG. 6 is a block diagram for explaining the second embodiment of the present invention. The figure shows the microprocessor 3 as the reset detection circuit 312 described in the first embodiment.
A reset circuit 313 that detects the rising edge of the download flag set by 10 and generates a hardware reset signal is provided. Reset circuit 313
A hardware reset signal output from the switching timing circuit 201 is input to the microprocessor 310 to reset the microprocessor 310 and
Is input to and used as a signal for changing the address allocation.

In the configuration shown, the microprocessor 3
10 periodically monitors the memory card flag detection unit 131, sets the download flag to "1" to enter the download mode when the flag becomes "1", and the reset circuit 313 starts at the rising edge. Generates a hardware reset signal.

The microprocessor 310 is reset by the hardware reset signal, and the switching timing circuit 201 receives the hardware reset signal and the download flag as inputs and notifies the address allocation switching circuit 202 of timing. The operation of the address allocation switching circuit 202 that has received the notification is the same as that described with reference to FIG. 2, and the change in address allocation is the same allocation as that described with reference to FIG.

Also, the address allocation reset circuit 204
Can be provided in the same manner as described in FIG. FIG. 7 shows a flowchart of the second embodiment of the present invention. The difference from the flowchart of the first embodiment described in FIG. 5 is that the reset circuit 313 in S3 detects the download flag “1”, generates a hardware reset signal, and outputs this hardware reset signal. The only point is that the microprocessor 310 is reset as an opportunity and a signal for switching the address allocation is sent to the switching timing circuit 201.

FIG. 8 is a block diagram for explaining the third embodiment of the present invention. The figure shows the memory card 121 and the memory card flag detection unit 131 described in the first embodiment.
As an example, a communication interface 500 serving as an interface between the buffer memory 122 and the third device 30 and a transfer completion detecting unit 510 for detecting the completion of the transfer of the program.

In the first and second embodiments of the present invention described with reference to FIGS. 2 and 6, the program to be downloaded is stored in the memory card 121 and the memory card 121 is stored.
Although the memory card 121 is downloaded to the flash ROM 111 by mounting the device on the second device 20, in FIG. 8, the third device 30 and the second device 20 are connected via the communication interface 500. The program to be downloaded is transferred to the buffer memory 122.

In the configuration shown, the program is transferred from the third device 30 through the communication interface 500 and stored in the buffer memory 122. Transfer completion detector 5
Reference numeral 10 internally includes a counter for counting the transfer data amount, and when the counter value reaches a preset program transfer amount, the transfer completion flag is set to "1" as transfer completion.

The microprocessor 310 regularly monitors the transfer completion flag, sets the download flag to "1" and resets the software to enter the download mode when the flag becomes "1". .

Subsequent operations are the same as the subsequent operations of the software reset detection unit 312 described with reference to FIG. FIG. 9 shows address allocation according to the third embodiment of the present invention.

(A) shows address allocation during normal operation, where 0000 to 3FFF are RAM addresses and 400 is
Buffer memory from 0 to 7FFF (shown as BM in the figure)
Address, 8000 to FFFF is assigned as a flash ROM address, and normally 8000 to FFFF
The microprocessor 310 operates according to the program of the flash ROM 111 written in the address.

(B) is an address allocation switching circuit 202
The flash ROM 111 and the buffer memory 12
The address assignment after exchanging the addresses of 2 is shown.
For address replacement, address allocation can be easily changed by replacing address lines as described with reference to FIG.

FIG. 10 is a block diagram for explaining the fourth embodiment of the present invention. The figure shows the memory card 121 and the memory card flag detection unit 13 described in the second embodiment.
The first example is an example including a communication interface 500 that interfaces between the buffer memory 122 and the third device 30, and a transfer completion detection unit 510 that detects completion of program transfer.

In FIG. 10, the program is transferred from the third device 30 through the communication interface 500 and stored in the buffer memory 122. Transfer completion detector 51
0 has a counter internally counting the transfer data amount, and when the counter value reaches a preset program transfer amount, the transfer completion flag is set to “1” as transfer completion.
Set to.

In the subsequent operations, the reset circuit 313 described in FIG. 6 generates a hardware reset signal,
This is similar to the operation of switching the address allocation of the memory. Although the description of each of the above-described embodiments has been made assuming that the program for controlling the operation of the apparatus is downloaded, the firmware and the micro program can be easily downloaded by the same configuration.

[0046]

According to the present invention, from the second storage device,
When the program is downloaded to the first storage device, the program for controlling the download process, the program for controlling the operation of the device, and the program for download are stored in the second storage device. By controlling the device by the program of the storage device, it is possible to realize a program download method that does not require stopping the device even during the download process.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram (1) for explaining the first embodiment of the present invention.

FIG. 3 is an address allocation according to the first embodiment of the present invention.

FIG. 4 is a block diagram (2) illustrating the first embodiment of the present invention.

FIG. 5 is a flowchart of the first embodiment of the present invention.

FIG. 6 is a block diagram illustrating a second embodiment of the present invention.

FIG. 7 is a flowchart of the second embodiment of the present invention.

FIG. 8 is a block diagram illustrating a third embodiment of the present invention.

FIG. 9 is an address allocation according to the third embodiment of the present invention.

FIG. 10 is a block diagram illustrating a fourth embodiment of the present invention.

FIG. 11 is a block diagram illustrating a conventional example.

[Explanation of symbols]

 10 First Device 20 Second Device 30 Third Device 10A Central Control Unit 20A I / O Control Device 110 First Storage Device 111 Flash ROM 120 Second Storage Device 121 Memory Card 122 Buffer Memory 131 Memory Card Flag Detection unit 200 Switching unit 201 Switching timing circuit 202 Address allocation switching circuit 203 Selector 204 Address allocation reset circuit 300 Control circuit 310 Microprocessor 311 Download flag detection unit 312 Software reset detection unit 313 Reset circuit 400 interface 500 Communication interface 510 Transfer completion detection unit

Claims (5)

[Claims] 1. A method of downloading a program to a second device that operates according to a command from the first device, wherein the second device stores a program for controlling the operation of the second device. Storage device, and a program downloaded to the first storage device,
The second that stores the program that controls the download process
And a program for downloading to the second storage device are detected, the program for controlling the second device is switched to the program stored in the second storage device. Unit, detecting that a program to be downloaded to the second storage device is prepared, issuing a program switching instruction to the switching unit, and causing the program of the second storage device to store the program of the second storage device. A control circuit for controlling download to the second storage device, the control circuit detecting the second program when the program to be downloaded to the second storage device is prepared.
Download the program and control the second device according to the program stored in the storage device, and when the command is received from the first device during the download, the download process is interrupted, When the command from the first device is executed and the execution of the command is completed, the download process is resumed and continued, and when the download process is completed, the control circuit is configured to operate the first circuit.
Program download method characterized in that control is performed according to the program downloaded to the storage device. 2. The program download method according to claim 1, wherein the second device includes a microprocessor that controls the second device, a flash ROM that stores a program that controls the operation of the second device, and A program to be downloaded to the flash ROM, a memory card to store the program to control the download process, and a memory card flag detection unit to detect a memory card flag set by the memory card being attached to the second device. And a download flag detecting section for detecting a download flag that the microprocessor detects and sets a memory card flag output from the memory card flag detecting section, and the microprocessor detects the memory card flag and performs a software reset. Was A software reset detection unit for detecting the above, a download flag detection output of the download flag detection unit, and an address allocation switching circuit for switching the address allocation of the flash ROM and the memory card from the software reset detection output of the software reset detection unit When the microprocessor detects a memory card flag, a software flag is set after the download flag is set, the address allocation switching circuit switches the addresses of the flash ROM and the memory card, and the memory card is in the process of downloading. 2. The program download method according to claim 1, wherein the control is performed according to the download program. 3. The program download method according to claim 1, wherein the software reset detection unit of the second device comprises:
When the rising edge of the download flag set by the microprocessor is detected, a hardware reset signal is sent to the microprocessor and the address allocation switching circuit, and the reset circuit is provided. When the microprocessor detects a memory card flag, A download flag is set, the reset circuit detects the rising edge of the download flag, and generates a hardware reset signal. The hardware reset signal causes the address allocation switching circuit to switch the addresses of the flash ROM and the memory card. The program download method according to claim 2, which is switched. 4. The program download method according to claim 2, wherein the microprocessor resets a download flag reset at the end of the download and a reset output of a software reset detection unit to detect the addresses of the flash ROM and the memory card. Is provided with an address allocation reset circuit for returning to the original allocation, and when the microprocessor detects a memory card flag, after setting a download flag, software reset is applied, and the address allocation switching circuit causes the flash ROM and the memory card to The microprocessor executes the download process by switching the address, and the microprocessor detects the end of the download process and resets the download flag. Returns the address of the card to the original allocation, the microprocessor program downloading method of claim 2, wherein the operating in a program stored in the flash ROM. 5. The program download method according to claim 2 or 3, wherein a memory card of the second device, a memory card flag detection unit, a communication interface for interfacing with a third device, and the communication interface. A microprocessor that stores a program received through a buffer memory; and a transfer completion detection unit that detects completion of transfer of the program from the third device to the buffer memory and sets a transfer completion flag. When the transfer completion flag set by the transfer completion detecting unit is detected, the download flag is set, software is reset, and the address allocation switching circuit switches the addresses of the flash ROM and the memory card. The program according to claim 2 or 3, Downloading method.