JPH02307124A - Interruption control system - Google Patents

Abstract

PURPOSE:To attain the interruption control which has a large freedom degree of program without increasing the hardware quantity by deciding a process level where the program runs next via a processor based on the information stored in an interruption control area when an interruption factor is produced to a higher process level from a lower process level. CONSTITUTION:If an interruption factor is produced to a higher process level from a lower process level, a processor 3 decides the priority of the interruption factor based on the priority information stored in a channel-based priority holding area 10b and a process sequence-based priority holding area 10c. Based on these information, the information showing the occurrence of an interruption within an interruption control area 10a is stored. Then a process level where a program runs next is decided based on the information stored in the area 10a. Thus it is possible to perform the interruption control having a large freedom degree of program without increasing the hardware quantity.

Description

[Detailed Description of the Invention] [Summary] Regarding a program interrupt control method in a program control system in which a plurality of channels are connected, the present invention aims to realize interrupt control with a high degree of program freedom without increasing hardware. It is equipped with a processor that performs various controls, a memory connected to the processor via a bus, and a plurality of channel interface units connected to the bus, and the memory is used to monitor and control the state of each channel. When performed by programs with different processing levels stored in
The memory includes an interrupt management area that manages interrupt occurrence information from a lower processing level to an upper processing level by priority, a channel-specific priority holding area that holds the priority of each channel, and a processing sequence of each channel. A processing sequence-specific priority holding area is provided to hold the priority, and when an interrupt factor from a lower processing level to an upper processing level occurs, the priority of this interrupt factor is stored in the channel-based priority holding area and the processing sequence. Distinguishing from priority information in a separate priority holding area, and storing information indicating that an interrupt has occurred in the interrupt management area based on the information;
The processing level at which the program runs next is determined based on the information in the interrupt management area.

[Industrial Application Field] The present invention relates to a program interrupt control method in a program control system in which a plurality of channels are connected.

In recent years, with the expansion and speeding up of computer networks and the progress and development of digital technology, a method of multiplexing multiple lines (also called channels) into one transmission path has become popular. Some systems for connecting such lines employ a program-based control method in order to efficiently control a plurality of multiplexed lines.

[Prior Art] FIG. 7 is a block diagram showing a configuration example of a conventional system. This system is externally connected to a network 2 via a transmission line 1, and shows a system in which a plurality of channels are multiplexed into one transmission line.

In the figure, 3 is a processor that performs various controls, and 4 is a memory connected to the processor 3 via a bus 5. In addition to the control program, the memory 4 contains a block ICB that stores line control data for each channel, a block DTB that tables the processes performed by the program according to the hardware status by sequence, and control data for the entire system. , a system management block SCB that holds data such as error information and program operating environment.

6 is a multiplexing processing unit that performs data multiplexing and demultiplexing processing between a plurality of (n) channels and the transmission line 1; Reference numeral 7 denotes channel interface sections, of which there are n, which perform matching of data formats, control of transmission/reception timing, and control of various control lines between the terminal devices connected to each channel and the multiplexing processing section 6. Reference numeral 8 denotes an interrupt control circuit which receives interrupt signals from the channel interface section 7 and the multiplexing processing section 6 and provides an interrupt to the processor 3 according to the interrupt level.

The multiplexing processing unit 6 includes a network side interface unit 6a that provides an interrupt signal from the network 2 side to the processor 3, and an error detection circuit 6b that also provides an interrupt signal with the highest priority to the processor 3. The channel interface section 7 includes an error detection circuit 7a that detects errors, and a line side interface section 7b that interfaces with the line side.
and a terminal-side interface section 7C that interfaces with the terminal side. The outputs of the error detection circuit 7a, the line side interface section 7b, and the terminal side interface section 7C are respectively connected to the interrupt control circuit 8 in a fed-or connection, and provide an interrupt signal to the interrupt control circuit 8. When the interrupt control circuit 8 receives these interrupt signals, it inputs the interrupt level of the processor 3 and gives interrupts to the processors 1 to L4 according to their priorities. As for the interrupt level, Ll is the highest, followed by L2. Continues with L3...

In the system configured in this way, the program is stored in the memory 4, and the processor 3 is stored in the memory 4.
Read the instructions and execute the program. In this case, there are registers in the multiplexing processing unit 6 and each channel interface unit 7 for displaying and controlling the state of the hardware, and the program (processor 3) can access the hardware by accessing these registers. control.

The program has five processing levels from L1 to L5 (L5 is the lowest level and is not shown in the drawing), and the processor 3 is provided with an interrupt function corresponding to each level. This interrupt function is performed by the interrupt control circuit 8.
The hardware is connected to each part of the hardware through It is now possible to generate interrupts.

Each processing level has a priority level, and the hardware interrupt function is connected to the interrupt control circuit 8 according to the priority level. For example, in FIG. 7, the error detection circuits 6b and 7a are at the processing level L, which has the highest priority.
It is connected to the interrupt function of 1. Furthermore, interrupts due to changes in the state of the transmission line 1 in the multiplexing processing unit 6 are placed at the processing level L2, and interrupts due to changes in the status of the control line in each channel interface unit 7 are placed at the processing level L3, and the processing related to the line side interface is placed at the processing level L3. Processing related to the side interface is respectively associated with processing level L4. Note that the lowest level processing is assigned to level L5, and is used when there is no interrupt.

FIG. 8 is a diagram showing an outline of control data used by the program, and shows the internal structure of the memory 4. As shown in FIG. ICB(
Interface Control Block
) block stores line control data. As shown in the figure, this line control data is provided for each channel, and its internal data is stored in the ICB status area, current DTB pointer address, next DTB pointer address, and input monitoring hardware register address 1.2. It is configured.

DTB (Control Data Block
) block contains processing sequence tables, and these processing sequence tables are tables of processing performed by the program according to the hardware state, organized by sequence. This processing sequence table includes the DTB status area, output pattern 1.2. It consists of an input cover turn 1.2 and a DTB address 1.2 for the next processing sequence.

SCB (System Control Block)
k) The block stores a system management area that holds data such as control data for the entire system, error information, and program operating environment. This system management area is SCB status.

It consists of an ICB pointer address, reference table, system operation mode, and total number of channels.

The program extracts the corresponding ■CB pointer address from the channel number and accesses the ICB area.

Next, the program refers to the current processing sequence in the DTB from the DTB pointer address in the control data in the ICB of each channel, and performs processing for the interrupt factor. Also, since the DTB pointer address for the next sequence is included in the same DTB, the ICB
The DTB pointer address in the DTB pointer is updated and the processing sequence proceeds.

FIG. 9 is a diagram showing a program processing sequence according to the conventional method. Normally, the program is running at processing level 5, performing processing with the lowest priority, such as checking the operating mode of the system and updating the operating environment of the program. Processing level 1 is a level for processing errors that occur in hardware and has the highest priority. At processing level 2, the multiplexing processing section 6 (see FIG. 7) controls the control line and transmits and receives data to and from the network in response to changes in the state of the transmission line 1.

Processing level 3 mainly controls between the channel interface section 7 and the multiplexing processing section 6;
mainly performs operations related to control between the channel interface unit 7 and the terminal device.

In this way, processing determined for each processing level is performed.

In FIG. 9, first, when an interrupt to processing level 3 shown in (■) occurs while processing level 5 is being executed, the upper level processing has priority over the lower level processing, so the program moves to processing level 3 and the processing Execute level 3. Next, when an interrupt to processing level 2 shown in (3) occurs while processing level 3 is being executed, the program interrupts execution of processing level 3 and starts executing processing level 2, which has a higher priority. Then, when the processing of processing level 2 is completed,
Execute the remaining processing of the original processing level 3.

Here, while processing level 3 is being executed, processing level 4 shown in ■
When an interrupt occurs, since processing level 4 has a lower priority than processing level 3, the program does not accept the interrupt and continues processing at processing level 3. Then, after the processing at processing level 3 is completed, execution at processing level 4 is started, and when the processing at processing level 4 is completed, the processing returns to processing at processing level 5, which is the lowest level. In this way, in the conventional method, when an interrupt to a certain processing level occurs from hardware, the processor 3 interrupts processing at the current processing level, and
The program execution address is changed to the start address of the program area corresponding to the interrupt processing level, and processing at the new processing level is started.

When processing is completed, the program returns to the processing level before the interrupt and resumes processing at that level.

[Problems to be Solved by the Invention] As described above, in the conventional system, the priority of interrupts is determined by the hardware configuration.

On the other hand, even interrupts to the same processing level may have different degrees of importance depending on the interrupt factor. For example, at level 3, activation processing for channel transmission and reception is more important than blockage processing, and the blockage processing also has priority over control line control during data transmission and reception. Furthermore, even in the same activation process, activation on the terminal side has higher priority than activation of the interface on the network side. In this way, there are various priorities depending on the contents of the interrupt factor.

On the other hand, the priority differs depending on which channel causes the interrupt.

For example, although all channels are equivalent in terms of hardware structure, a certain channel may perform call control for a plurality of other channels of its multiplexed line. In such a case, control of this channel needs to be given priority over control of other channels.

As explained above, when attempting to implement interrupt functions according to various priorities using hardware, the problem inevitably occurs that the circuit becomes complex and large-scale. Furthermore, in the configuration of the prior art, the degree of freedom in priority control of interrupts is also limited.

The present invention has been made in view of these problems, and an object of the present invention is to provide an interrupt control method that can realize interrupt control with a high degree of program freedom without increasing hardware.

[Means to solve the problem] FIG. 1 is a block diagram of the principle of the system of the present invention.

Components that are the same as those in FIG. 7 are designated by the same reference numerals.

In the figure, 3 is a processor that performs various controls, 10 is a memory connected to the processor 3 via a bus 5, and 7
are a plurality of channel interface units connected to the bus 5.

Reference numeral 10a indicates an interrupt management area in the memory 10 for managing interrupt occurrence information from a lower processing level to an upper processing level by priority level, 10b indicates a priority holding area for each channel, and 10c indicates a priority holding area for each channel. This is a processing sequence priority holding area that holds priorities for each channel processing sequence.

[Operation] When the state of each channel is monitored and controlled by programs having different processing levels stored in the memory 10, when an interrupt factor from a lower processing level to an upper processing level occurs, the processor 3 The priority of this interrupt factor is determined from the priority information in the channel-specific priority holding area 10b and the processing sequence-specific priority holding area 10c, and based on the information, an interrupt is generated in the interrupt management area 10a. The processing level in which the program runs next is determined based on the information in the interrupt management area 10a. With such a configuration, it is possible to provide an interrupt control method that can realize interrupt control with a high degree of program freedom without increasing hardware.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. Components that are the same as those in FIGS. 1 and 7 are designated by the same reference numerals. In the memory 10, the interrupt management area 10a is S
Contained within the CB block, priority retention area 1 for each channel
0b is included in the ICB block, and the processing sequence priority holding area 10c is included in the DTB block. The outputs of the error detection circuits 6b and 7a in each hardware are connected by wired-or, and the level 1 of the interrupt control circuit 8
It is connected to the interrupt generating section and has the highest priority level L1.

All interrupt factors from other hardware are wired-OR connected and connected to the level 2 interrupt generation section of the interrupt control circuit 8. As a result, interrupts of level 3 or lower can only be generated by a program. The interrupt control circuit 8 is provided with a channel (CH) holding register 8a that indicates from which channel when an interrupt occurs from each piece of hardware.

FIG. 3 is a diagram showing an example of the configuration of the interrupt management area 10a. As shown in the figure, it is blocked by priority irregularities,
The priority information is a pointer address for accessing the corresponding priority irregular block within the interrupt management area. At the beginning of each block, there is an interrupt occurrence counter and an interrupt processing counter. After updating the interrupt occurrence counter value, the program writes interrupt factor information to the interrupt factor information holding area of each block based on the updated value.

This interrupt occurrence counter is an offset value indicating a location in each block where interrupt cause information is stored, and is used cyclically.

The interrupt processing counter is a counter that is updated every time processing for an interrupt factor is completed, and also serves as an offset value indicating the location of unprocessed interrupt factor information.

FIG. 4 is a diagram showing a configuration example of a DTB and an ICB according to the present invention. In comparison with the conventional example shown in FIG. 8, in the DTB block, the processing sequence priority holding area 10c is
The B block is different in that it includes a channel-specific priority holding area 10b. The operation of the system configured as described above will be explained below according to the flowchart shown in FIG.

First, processing related to interrupt priority control will be explained. Consider the case where an interrupt other than error processing, which has the highest priority level, occurs. When this interrupt occurs, the program immediately shifts to processing level 2. At processing level 2, the program reads information set in an interrupt cause register (not shown) in the interrupt control circuit 8 and analyzes the interrupt cause. At the same time, the program is
The channel generated from the data held in the holding register 8a is recognized.

Having thus determined in which channel the interrupt occurred, the program retrieves the ICB pointer address corresponding to that channel in the corresponding ICB (Sl)
. When the IcB area of the channel can be accessed in this way, the priority of that channel is read from the channel-specific priority holding area 10b, and the priority of the current ICB is set to level 2.
It is checked whether it is (S2). There are two levels of priority for each channel, and when the priority is high, processing level 2 is selected. Then, processing for the corresponding interrupt factor is performed using ICB and DTB (S3). In this case, it does not depend on the priority of each processing sequence.

If the priority is lower than level 2, the processing level is selected based on the priority of each processing sequence.

Which processing sequence the channel is currently in is determined by I
Control data within the CB block can be extracted. The program extracts the current DTB pointer address in the rcB block (S4), accesses the DTB area corresponding to the current processing sequence, and reads priority information from the processing sequence priority holding area 10c in that area.

Then, it is checked whether the priority of the current processing sequence is level 2 (S5). If so, step S3 is executed. If this is not the case, the program writes the interrupt factor information to the corresponding priority block in the interrupt management area 10a according to the priority of the current processing sequence.

Also, an interrupt occurrence counter is updated (S6).

Specifically, the program accesses the corresponding area of the interrupt management area 10a based on the priority information. The internal configuration of the interrupt management area 10a is as described with reference to FIG. 3, and interrupt cause information is written in blocks classified by priority. When the process of registering interrupt factor information in the interrupt management area 10a is completed, the program accesses the block with the highest priority in the interrupt management area 10a, and if there is unprocessed interrupt factor information, it accesses the block according to the priority. Select the processing level. Here, whether or not there is unprocessed interrupt factor information is identified by comparing the values of the interrupt processing counter and the interrupt occurrence counter (S7).
.

Then, it is checked whether the count values of these two counters match (S8). When these two count values are equal, there is no unprocessed interrupt factor information in that block. Therefore, in this case, it is difficult to judge whether all priority blocks have been checked (S9).
, in the case of No, the priority block to be checked is changed and step S7 is executed. If YES, it means that all interrupt processing has been completed, so the process returns to processing level 5 (S10).

In step S8, if the two counter values do not match, the process moves to the processing level corresponding to the corresponding priority (Sll). At the new processing level, the program accesses the priority block corresponding to that level in the interrupt management area 10a and extracts the interrupt cause information to be processed from now on from the interrupt processing counter value (S1
2). From this information, the corresponding channel area of the ICB block is accessed (see FIG. 4), and the DTB corresponding to the current processing sequence is accessed using the current DTB pointer address set in the ICB block.

Then, based on the interrupt factor information and the information in the DTB block, the program determines the processing for the hardware,
Execute (S13).

A DTB pointer address corresponding to the next processing sequence is held in the DTB block, and the program updates the current DTB pointer address in the JCB block with this address.

When all processing is completed in this manner, the program updates the interrupt processing counter of the corresponding block in the interrupt management area 10a, and determines the processing level to be executed next in the same manner as control at processing level 2. If unprocessed interrupt factor information does not exist in all priority irregular blocks within the interrupt management area 10a, the process returns to processing level 5.

FIG. 6 is a diagram showing a program processing sequence according to the method of the present invention. Assume that while the program is executing processing level 5, an interrupt factor corresponding to processing level 3 occurs as shown in (3). The program immediately moves to processing level 2 and analyzes the cause of the interrupt. As a result, the processing level shifts to level 3. Assume that an interrupt factor equivalent to processing level 2 occurs during execution of processing level 3, as shown in (3).

The program interrupts execution of processing level 3, moves to processing level 2 again, and analyzes the cause of the interrupt. the result,
Since level 2 has the highest priority, the processing of processing level 2 is executed as is.

When the processing at processing level 2 is completed, the processing moves to processing level 3, which has been interrupted, and the processing at processing level 3 is restarted.

Here, it is assumed that an interrupt factor equivalent to processing level 4 occurs while processing level 3 is being executed, as shown in (3). The program interrupts level 3 processing, moves to level 2 again, and analyzes the cause of the interrupt.

As a result, since processing level 4 has a lower priority than processing level 3, the program returns to processing level 3 and executes the remaining processing of processing level 3.

When the processing at processing level 3 is completed, the processing level shifts to level 4, and the processing at processing level 4 is executed. and,
When the processing at processing level 4 is completed, the process moves to processing level 5, which is the lowest priority level, and the processing at level 5 is restarted.

[Effects of the Invention] As described above in detail, according to the present invention, when an interrupt factor from a lower processing level to an upper processing level occurs, the processor sets the priority of this interrupt factor to the channel-specific priority. - Distinguish from the priority information in the priority holding area and the priority holding area for each processing sequence, and store information indicating that an interrupt has occurred in the interrupt management area based on that information, and the program will run next. To provide an interrupt control method capable of realizing interrupt control with a high degree of freedom in a program without increasing hardware by configuring the processing level to be determined based on information in the interrupt management area. be able to.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the method of the present invention, FIG. 2 is a block diagram of the configuration of an embodiment of the present invention, FIG. 3 is a diagram of an example of the configuration of an interrupt management area, and FIG. 4 is a block diagram of the DTB according to the present invention. FIG. 5 is a flowchart showing the operation of the method of the present invention; FIG. 6 is a diagram showing a program processing sequence according to the method of the present invention; FIG. 7 is a block diagram showing an example of the configuration of a conventional system. 8 is a diagram showing an outline of control data used by the program, and FIG. 9 is a diagram showing a processing sequence of the program according to the conventional method. In FIG. 1, 3 is a processor, 5 is a bus, 7 is a channel interface section, 8 is an interrupt control circuit, 10 is a memory, 10a is an interrupt management area, 10b is a priority holding area for each channel, and 10c is a priority for each processing sequence. It is in the degree retention area.

Claims (1)

[Claims] A processor (3) that performs various controls, a memory (10) connected to the processor (3) via a bus (5), and a plurality of channels connected to the bus (5). and an interface section (7), and the memory (10) monitors and controls the state of each channel.
an interrupt management area (10a) for managing interrupt occurrence information from a lower processing level to an upper processing level according to priority in the memory (10); A channel-by-channel priority holding area (10b) that holds the priority of each channel and a processing sequence-specific priority holding area (10c) that holds the priority of each channel's processing sequence are provided, and the process can be carried out from the lower processing level to the upper processing level. When an interrupt factor occurs, the priority of this interrupt factor is determined from the priority information in the channel-specific priority holding area (10b) and the processing sequence-specific priority holding area (10c), and the information Based on this, information indicating that an interrupt has occurred is stored in the interrupt management area (10a), and the processing level at which the program will run next is stored in the interrupt management area (10a).
An interrupt control method characterized in that the interrupt control method is configured to make a decision based on information in the interrupt control method.