JPH098133A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE: To achieve wiring connection which can be easily and stably obtained without increasing connection resistance between fine lower-layer and upper- layer wires. CONSTITUTION: A joint is made to the surface and side-surface parts of a lower- layer wiring 3 at an interlayer connection part of a position for electrical connection to an upper-layer wiring to be formed on a lower-layer wiring 3, at the same time a stand-shaped conductor block 5 being partially extended on the insulation layer 2 is formed, and an upper-layer wiring 8 is joined to the upper surface of a conductor block 5 being exposed to the upper surface of an interlayer insulation film 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a multi-layer wiring.

[0002]

2. Description of the Related Art Conventionally, a semiconductor integrated circuit device having a wiring structure in which reliability is improved by flattening is provided as a multilayer wiring of a mounting substrate on which a semiconductor device or a semiconductor element is mounted (JP-A-62-39027, or JP-A-60-
No. 57997) is known. The wiring structure according to the above conventional technique will be described below.

(A) As a wiring structure of a semiconductor device, for example, in a first example disclosed in Japanese Patent Application Laid-Open No. 62-39027, future lower layer wiring and upper layer wiring on an insulating film provided on a semiconductor substrate will be described. A trapezoidal conductor block is formed at a position where the electrical connection is to be made. After forming a lower wiring layer so as to cover the conductor block, an interlayer insulating film is deposited. Next, a photoresist film is applied on the interlayer insulating film and etched back to flatten the upper surface to expose the upper portion of the lower wiring layer formed on the conductor block, and the upper wiring layer is connected so as to be connected to it. It has a formed structure.

(B) Multilayer wiring of a mounting substrate on which a semiconductor element is mounted is formed, for example, in the second example disclosed in Japanese Patent Laid-Open No. 60-57997, it is formed on a mounting substrate made of an insulating material. A trapezoidal conductor block is formed on the lower layer wiring at a position where electrical connection with the upper layer wiring layer should be made in the future. An interlayer insulating film is deposited on the lower wiring layer including the conductor block, and the upper wiring layer connected to the lower wiring is formed by the same process as in the first example.

[0005]

The conventional multilayer wiring technique has the following problems.

(A) For example, in the first conventional example, since the lower wiring layer is formed on the trapezoidal conductor block, its height (thickness) is set for the purpose of installing the conductor block. The higher the value, the worse the step coverage of the conductor block, and there is a problem that a disconnection or an increase in wiring resistance is likely to occur.

(B) In the second example, the problem of pattern misalignment of the metal laminating mask used when forming the trapezoidal conductor block on the lower wiring layer cannot be avoided. There is a problem that a connection failure with the upper wiring layer occurs.

In the finer and more highly integrated wiring structure of the semiconductor integrated circuit device, these problems of connection problems become more serious as the wiring width of the lower wiring layer becomes narrower. There was a problem that the structure could not be avoided at all.

Further, there is a problem that the metal used as the trapezoidal conductor block is limited by the metal used as the one-layer wiring layer. The problem is that when the above-mentioned mask misalignment defect occurs, the wiring reliability is impaired as a fatal wiring defect.

According to the present invention, in a multi-layer wiring structure that requires high-density wiring, regardless of the selection and combination of the metals of the lower layer wiring, and even if the deposition method of the metal to be laminated is freely selected,
Alternatively, with respect to misalignment of connection between the lower layer wiring and the upper layer wiring, high reliability that wiring failure such as increase in resistance does not occur,
Moreover, it is an object of the present invention to provide a semiconductor integrated circuit device having a wiring structure with high workability.

[0011]

A semiconductor integrated circuit device according to the present invention electrically connects a lower layer wiring formed on an insulating film provided on a semiconductor substrate, the lower layer wiring and an upper layer wiring provided thereon. A trapezoidal shape that is formed on the lower layer wiring of the interlayer connection portion for connection and is joined to the upper surface and both side surfaces of the lower layer wiring and a part of which extends on the insulating film adjacent to the side surface of the lower layer wiring. A conductor block and a surface of the conductor block other than the uppermost surface of the conductor block and the insulating film including the lower layer wiring are formed and the upper surface is planarized including the uppermost surface of the conductor block. And an upper layer wiring which is joined to the upper surface of the conductor block and extends on the interlayer insulating film.

[0012]

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1A to 1E are sectional views showing the order of steps for explaining the manufacturing method of the first embodiment of the present invention.

First, as shown in FIG. 1A, an Al film having a thickness of 500 to 600 nm or Al as a main component is formed on an insulating film 2 formed on a semiconductor substrate 1 such as silicon on which an element is formed. The lower wiring 3 made of an alloy film containing Cu, Cu, etc. is formed. The lower layer wiring 3 is formed of an Al film or A
It is obtained by depositing an l-alloy film on the insulating film 2 by an electron beam evaporation method or the like and then patterning it by a photolithography technique.

Next, as shown in FIG. 1B, the mask 4
A refractory metal film of Cu or the like is selectively deposited on the lower wiring 3 by electron beam evaporation to form a trapezoidal conductor block 5
To form The conductor block 5 has a form in which the lower layer wiring 3 is completely covered with a certain width, and its position is an interlayer connecting portion for connecting to the upper layer wiring formed on the lower layer wiring 3. The mask is adjusted. The thickness of the Cu film formed as the conductive block 5 is set to be higher than at least the highest portion of the step generated up to the previous step.

Next, as shown in FIG. 1C, a SiO ₂ film, for example, is deposited as a interlayer insulating film 6 on the surface including the lower layer wiring 3 and the conductor block 5 by the CVD method, and the interlayer insulating film 6 is formed. A photoresist film 7 is applied on the above.

Next, as shown in FIG. 1 (d), the entire surface of the conductor block 5 is exposed until the upper surface of the conductor block 5 is exposed by setting the selection ratio of the photoresist film 7 and the SiO ₂ film, which is the interlayer insulating film 6, to 1: 1. Etch back to flatten the surface.

Next, as shown in FIG. 1E, an Al film or an Al alloy film is deposited and patterned on the interlayer insulating film 6 including the conductor block 5, and the lower layer is formed via the conductor block 5. An upper layer wiring 8 that is electrically connected to the wiring 3 is formed.

In this embodiment, the conductor block 5 is formed by direct metal deposition using a mask. However, a desired metal film is deposited on the entire surface and then patterned by photolithography technique. Alternatively, a so-called replica method may be used to form a desired wiring pattern. In this case, it is also preferable that a photoresist film for patterning is formed thick using a photoresist having high viscosity.

In this embodiment, the conductor block 5 is also used.
The case where a single layer of Cu is used as the refractory metal has been described in forming the alloy. However, for example, Mo, Ni, Cr, Ti, Pt, Au, W, T containing a compound of the refractory metal has been described.
Similar effects can be obtained by forming a single layer of iN, TiW, or the like, or by stacking them including Cu.

Here, each of the metal films of Mo, Ni, Cr, Ti, and Au is formed by the electron beam evaporation method, each of the metal films of Ti, Pt, and TiW is formed by the ordinary sputtering method using each metal as a target, and TiN is formed. Is N ₂ targeting a Ti plate
It can be deposited by a sputtering method in which a gas is introduced. The Au layer may be formed by a plating method, and the W layer is generally deposited by a CVD method using a mixed gas of WF ₆ and H ₂ as a reaction gas.

When forming a conductor block having a laminated structure with respect to the Al film of the lower layer wiring, Ti, Mo, etc. should be taken into consideration in consideration of the adhesion between the Al metal and the metal deposited on the upper layer and the prevention of thermal diffusion. , Cr, TiN, etc. are used as the barrier metal. In this case, the reliability of the wiring structure of the semiconductor device can be further improved as compared with the case where only a single refractory metal layer is attached.

2A to 2D are sectional views showing the manufacturing method of the second embodiment of the present invention in the order of steps for explaining the manufacturing method.

First, as shown in FIG. 2A, the lower layer wiring 3 is formed on the insulating film 2 formed on the semiconductor substrate 1 by the same process as in the first embodiment, and then the lower layer wiring 3 is formed. The photoresist film 9 is applied on the insulating film 2 containing the insulating film 2, and the photoresist film 9 on the insulating film 2 in the region including the lower layer wiring 3 of the interlayer connection part and both side surfaces thereof is removed by a normal photoresist process and then left. Using the photoresist film 9 as a mask, a Ti film 10 having a thickness of 100 nm and a TiN film 11 having a thickness of 0.2 to 0.3 μm are deposited on the entire surface by sputtering as a barrier metal film.

Here, the thickness of the photoresist film 9 is 2 to 3
The thickness is adjusted to μm so that the metal film does not adhere to the side wall of the photoresist film 9. Since the TiN film 11 can be formed by using Ti as a sputtering target and a mixed gas of argon and nitrogen as a discharge gas, the TiN film 11 is deposited by the same sputtering apparatus as that for forming the Ti film 10 and without breaking the vacuum degree of the sputtering chamber. What you can do, productivity is good.

Next, as shown in FIG. 2B, the photoresist film 9 is removed with a photoresist stripping solution, and at the same time, the laminated film of the Ti film 10 and the TiN film 11 on the photoresist film 9 is lifted off to form a lower layer. The laminated film of the Ti film 10 and the TiN film 11 is left only on the wiring 3 and the insulating film 2 on both side surfaces thereof. The upper surface and the both side surfaces of the lower layer wiring 3 of the interlayer connecting portion thus obtained are covered with a laminated film of the Ti film 10 and the TiN film 11.

Next, as shown in FIG. 2C, a trapezoidal conductor block 12 made of a Cu film is formed on the barrier metal film made of the Ti film 10 and the TiN film 11 formed on the lower wiring 3. Form. Here, the conductor block 12 is C
The u film can be formed using electron beam evaporation and photolithography technology. Next, after forming the conductor block 12, upper layer wiring is formed by the same process as in the first embodiment.

In this second embodiment, the conductor block 1
Although the case where the laminated film of the Ti film and the TiN film is used as the lower layer film of No. 2 has been described, for example, a single layer of the TiN film may be used, or the same effect can be obtained by laminating the Ti film and the Pt film. The metal as the upper layer film is Au or W instead of Cu.
May be used. The combination of these metals and the selection of the forming method are the same as in the first embodiment.

3 (a) and 3 (b) are cross-sectional views showing steps in order to explain the third embodiment of the present invention.

As shown in FIG. 3A, the insulating film 2 provided on the semiconductor substrate 1 is processed by the same process as in the second embodiment.
After the lower layer wiring 3 is formed on the upper surface of the wiring layer, and a stack of the Ti film 10 and the TiN film 11 that covers the upper surface and both side surfaces of the lower layer wiring 3 of the interlayer connection portion is selectively formed by the lift-off method, the interlayer insulating film 6 is formed. As an example, a SiO ₂ film is deposited by the CVD method. If the refractory metals used are Ti and TiN, the whole laminated film of the Ti film 9 and the TiN film 10 in the Al wiring layer 3 and its interlayer connection is covered with the interlayer insulating film 6 made of a SiO ₂ film. Becomes Next, the interlayer insulating film 6 is patterned by the photolithography technique to form the through hole 13.

Next, as shown in FIG. 3B, a W plug 14 is formed by being embedded in the contact hole 13 by a selective CVD method using a mixed gas of WF ₆ and H ₂ as a reaction gas. Next, A is formed on the interlayer insulating film 6 including the W plug 14.
An I film or an Al alloy film is deposited and patterned to form an upper wiring 8 which is electrically connected to the lower wiring 3 via the W plug 14. In this case, it is preferable that the surface of the interlayer insulating film 6 is flattened by an etch back method or the like and then the upper wiring is formed.

[0032]

As described above, according to the present invention, since the trapezoidal conductor block made of a refractory metal covers the upper surface and the side surface of the interlayer connection portion of the lower wiring, the mask misalignment occurs. Even with this, there is an effect that it is possible to prevent the contact connection failure of the interlayer connection portion.

Further, by forming the trapezoidal conductor block by laminating a plurality of different refractory metal layers, there is an advantage that the degree of freedom can be increased including selection and combination of metals, or deposition thereof. Further, there is an advantage that the contact resistance of the through hole can be prevented from increasing due to the formation of a metal compound for the lower wiring layer.

Further, the surface of the conductor block including the inter-layer insulating film after it is formed can be flattened, and disconnection or short circuit due to the step of the upper wiring can be prevented to obtain high reliability. High-density multilayer wiring can be formed.

[Brief description of drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing method according to a first embodiment of the present invention in the order of steps for explaining the manufacturing method.

2A to 2D are sectional views showing the manufacturing method of the second embodiment of the present invention in the order of steps for explaining the manufacturing method.

3A to 3D are cross-sectional views showing the manufacturing method of the third embodiment of the present invention in the order of steps for explaining the manufacturing method.

[Explanation of symbols]

 1 Semiconductor Substrate 2 Insulating Film 3 Lower Layer Wiring 4 Mask 5,12 Conductor Block 6 Interlayer Insulating Film 7,9 Photoresist Film 8 Upper Layer Wiring 10 Ti Film 11 TiN Film 13 Through Hole 14 W Plug

Claims (4)

[Claims] 1. A lower layer wiring formed on an insulating film provided on a semiconductor substrate, and an upper layer wiring provided on the lower layer wiring on the lower layer wiring for electrically connecting the lower layer wiring and the upper layer wiring provided thereon. A trapezoidal conductor block which is formed and joined to the upper surface and both side surfaces of the lower layer wiring and a part of which extends on the insulating film adjacent to the side surface of the lower layer wiring, and other than the uppermost surface of the conductor block An interlayer insulating film formed on the surface of the conductor block and the insulating film including the lower layer wiring and having a top surface planarized to include the uppermost surface of the conductor block; and an upper surface of the conductor block. A semiconductor integrated circuit device, comprising: an upper layer wiring which is joined and extended on the interlayer insulating film. 2. The lower layer wiring and the upper layer wiring are made of Al or Al.
The semiconductor integrated circuit device according to claim 1, which is made of an alloy. 3. The semiconductor integrated circuit device according to claim 1, wherein the conductor block is made of a refractory metal or a refractory metal compound. 4. The conductor block has a laminated structure composed of at least two kinds of refractory metal layers or refractory metal compound layers, and at least the lowermost layer covers the upper surface and both side surfaces of the lower layer wiring and joins them. The semiconductor integrated circuit device according to claim 1 or 2.