JPH0964116A - Method and apparatus for detecting defective bonding in wire bonding device - Google Patents

Method and apparatus for detecting defective bonding in wire bonding device

Info

Publication number
JPH0964116A
JPH0964116A JP23762695A JP23762695A JPH0964116A JP H0964116 A JPH0964116 A JP H0964116A JP 23762695 A JP23762695 A JP 23762695A JP 23762695 A JP23762695 A JP 23762695A JP H0964116 A JPH0964116 A JP H0964116A
Authority
JP
Japan
Prior art keywords
bonding
wire
frequency signal
circuit
high frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23762695A
Other languages
Japanese (ja)
Inventor
Masanao Ura
正直 浦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kaijo Corp
Original Assignee
Kaijo Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kaijo Corp filed Critical Kaijo Corp
Priority to JP23762695A priority Critical patent/JPH0964116A/en
Publication of JPH0964116A publication Critical patent/JPH0964116A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518—Translational movements
    • H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
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    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01055—Cesium [Cs]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01072—Hafnium [Hf]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PROBLEM TO BE SOLVED: To detect deflective bonding of a semiconductor device having a capacitance component such as a MOS integrated circuit. SOLUTION: A semiconductor device having a capacitive component C such as a MOS integrated circuit bonding-processed through a current transformer 2 is supplied with a high-frequency signal from a high-frequency signal generating circuit 1. An induced current flowing through the capacitive component C by the MOS integrated circuit is extracted from the current transformer 2, and rectified and integrated by a rectifier integrated circuit 3. A level decision circuit 4 is supplied with an integrated output by the rectifier integrated circuit 3, and deflective bonding is detected in the level decision circuit 4.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体デバイスの
組立工程に用いられるワイヤボンディング装置に係り、
特にボンディング時におけるボンディング不着状態を検
出する検出方法及び検出装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wire bonding apparatus used in a semiconductor device assembly process,
In particular, the present invention relates to a detection method and a detection device for detecting a non-bonding state during bonding.

【０００２】[0002]

【従来の技術】半導体デバイスの組立工程に用いられる
ワイヤボンディング装置においては、金線又は銅、アル
ミニウムなどのワイヤを用いて第１ボンディング点とな
る半導体チップ上のパッド（電極）と、第２ボンディン
グ点となるリードとを接続するように成される。2. Description of the Related Art In a wire bonding apparatus used in a semiconductor device assembling process, a pad (electrode) on a semiconductor chip serving as a first bonding point using a gold wire or a wire such as copper or aluminum is connected to a second bonding point. The connection is made with a lead which is a point.

【０００３】従来、この種のワイヤボンディング装置に
おいては、先ずボンディングツールとしてのキャピラリ
から突出したワイヤの先端と放電電極（電気トーチ）と
の間に高電圧を印加することにより放電を起こさせ、そ
の放電エネルギーによりワイヤの先端部を溶融してキャ
ピラリの先端にボールを形成するようにしている。Conventionally, in this type of wire bonding apparatus, first, a high voltage is applied between the tip of a wire protruding from a capillary as a bonding tool and a discharge electrode (electric torch) to cause discharge, and The tip of the wire is melted by the discharge energy to form a ball at the tip of the capillary.

【０００４】そして図３（ａ）乃至（ｃ）に示すよう
に、キャピラリ２０の先端に形成されたボール２１ａ
を、第１ボンディング点である半導体チップ２２上のパ
ッドに対して所定のボンディング荷重を加えつつ、超音
波及び他の加熱手段を併用して加熱を行い、ワイヤ２１
を接続するように成される。Then, as shown in FIGS. 3A to 3C, a ball 21a formed at the tip of the capillary 20.
While applying a predetermined bonding load to the pad on the semiconductor chip 22 which is the first bonding point, the wire 21 is heated by using ultrasonic waves and other heating means in combination.
Is made to connect.

【０００５】そして図３（ｄ）乃至（ｅ）に示すように
ワイヤ２１をキャピラリ２０の先端から繰り出しつつ、
キャピラリ２０を所定のループコントロールに従って相
対移動せしめ、キャピラリ２０を第２ボンディング点で
あるリード２３の直上に位置させる。さらに（ｆ）に示
すようにキャピラリ２０に所定のボンディング荷重を加
えつつ第２ボンディング点に圧着し、超音波及び他の加
熱手段を併用して加熱を行い、第２ボンディング点に対
してワイヤ２１を接続するように成される。Then, as shown in FIGS. 3 (d) to 3 (e), the wire 21 is extended from the tip of the capillary 20,
The capillary 20 is relatively moved according to a predetermined loop control, and the capillary 20 is positioned directly above the lead 23 which is the second bonding point. Further, as shown in (f), the capillary 20 is pressed against the second bonding point while applying a predetermined bonding load, heated by using ultrasonic waves and other heating means, and the wire 21 is applied to the second bonding point. Is made to connect.

【０００６】続いて（ｇ）に示すようにワイヤ２１をキ
ャピラリ２０の先端より所定のフィード量ｆだけ引き出
した状態でワイヤ２１を挿通するクランパ２４を閉じて
キャピラリ２０と共に上方に引き上げることで、（ｈ）
に示すようにワイヤ２１は第２ボンディング点より切断
され、第１ボンディング点及び第２ボンディング点との
間にワイヤ２１の接続が完了する。Subsequently, as shown in (g), with the wire 21 pulled out from the tip of the capillary 20 by a predetermined feed amount f, the clamper 24 for inserting the wire 21 is closed and pulled up together with the capillary 20. h)
As shown in, the wire 21 is cut from the second bonding point, and the connection of the wire 21 is completed between the first bonding point and the second bonding point.

【０００７】図４は、以上のような工程を具備するワイ
ヤボンディング装置に採用された従来のボンディング不
着検出の一例を示したものである。なお図４において、
前記図３と同一の符号で示した箇所は同一部分であり、
従ってその説明は省略する。このボンディング不着検出
は、第１ボンディング点としてのパッドと第２ボンディ
ング点としてのリードとが接続された状態で直流電流を
検出することによってワイヤ切れ等のボンディング不着
を検出するものである。FIG. 4 shows an example of conventional non-bonding detection adopted in a wire bonding apparatus having the above-mentioned steps. In addition, in FIG.
The parts indicated by the same reference numerals as those in FIG. 3 are the same parts,
Therefore, the description is omitted. In this bonding non-bonding detection, a bonding non-bonding such as wire breakage is detected by detecting a direct current in a state where a pad as a first bonding point and a lead as a second bonding point are connected.

【０００８】従って、前記第１ボンディング点又は第２
ボンディング点に正常なボンディングが成された場合に
は、前記クランパ２４よりワイヤ２１を介して半導体チ
ップ２２のパッドとベース２２ａ間で直流閉回路が形成
される。そして電流検出器（図示せず）によって直流電
流の存在を検出することで、第１ボンディング点又は第
２ボンディング点に正常にボンディングが成されたもの
と判定し、直流電流が流れない場合には、ワイヤ切れ等
であると判定するようにしている。Therefore, the first bonding point or the second bonding point
When normal bonding is achieved at the bonding point, a DC closed circuit is formed between the pad of the semiconductor chip 22 and the base 22a via the wire 21 from the clamper 24. Then, by detecting the presence of a direct current with a current detector (not shown), it is determined that the bonding has been normally performed at the first bonding point or the second bonding point, and if the direct current does not flow, It is determined that the wire is broken.

【０００９】[0009]

【発明が解決しようとする課題】ところで、前記した従
来のボンディング不着検出では、ボンディングが成され
る半導体デバイスとして、例えばバイポーラタイプのも
のについては、前記のように微弱な直流電流が流れるか
否かにより不着検出を成すことができるが、半導体デバ
イスとして、例えばＳ−ＲＡＭに代表されるようなＭＯ
Ｓ（Metal-OxideSemiconductor ）集積回路等の半導体
部品においては、直流の流通経路が形成されず、従来の
ような直流による検出方法においては不着検出を行うこ
とができないという問題点を有している。By the way, in the above-described conventional bonding non-adhesion detection, whether or not the weak DC current flows as described above is applied to the semiconductor device to be bonded, for example, of the bipolar type. The non-attachment detection can be performed by using a semiconductor memory device such as an MO-MOB typified by an S-RAM.
In a semiconductor component such as an S (Metal-Oxide Semiconductor) integrated circuit, a direct current flow path is not formed, and there is a problem that non-contact detection cannot be performed by a conventional direct current detection method.

【００１０】本発明は前記した従来のものの問題点に鑑
みて成されたものであり、ＭＯＳ集積回路等のような容
量成分を有する半導体デバイスに対するものであっても
不着検出が可能な不着検出方法及び装置を提供すること
を目的とするものである。The present invention has been made in view of the above problems of the prior art, and is a non-stick detection method capable of non-stick detection even for a semiconductor device having a capacitive component such as a MOS integrated circuit. And to provide a device.

【００１１】[0011]

【課題を解決するための手段】本発明に係るワイヤボン
ディング装置におけるボンディング不着検出方法は、ボ
ンディングツールによって被ボンディング部品にワイヤ
をボンディングするボンディング装置において、ボンデ
ィングが成された半導体チップのパッドとベース間に前
記ワイヤを介して高周波信号を印加させると共に、前記
ワイヤを介して半導体チップに流入する電流に対応する
出力レベルを判定することによって、ボンディングの不
着検出を行うようにしたものである。また、本発明に係
るワイヤボンディング装置におけるボンディング不着検
出装置は、ボンディングツールによってボンディングが
成された半導体チップのパッドとベース間にワイヤを介
して高周波信号を印加させるための高周波信号発生手段
と、前記高周波信号発生手段からの高周波信号に基づく
電流を検出する電流検出手段と、前記電流検出手段によ
って得られる出力レベルを弁別するレベル判定手段とを
備え、前記レベル判定手段による弁別出力により、ボン
ディングの不着状態を検出するように構成したものであ
る。前記したボンディング不着検出方法及びその装置に
おいては、ボンディング用ワイヤを介して半導体チップ
のパッドに対して高周波信号を送り、この高周波信号に
基づく電流を検出するように成される。そして、この電
流に基づく出力レベルを弁別することにより、ボンディ
ングの状態を検証するものであり、従って半導体チップ
が例えば容量性の素子であるＭＯＳ集積回路であって
も、ボンディングの不着状態を確実に検出することがで
きる。A method for detecting non-bonding in a wire bonding apparatus according to the present invention is a bonding apparatus for bonding a wire to a component to be bonded by a bonding tool. The non-bonding detection is performed by applying a high-frequency signal via the wire and determining the output level corresponding to the current flowing into the semiconductor chip through the wire. Further, the bonding non-adhesion detecting device in the wire bonding device according to the present invention comprises a high frequency signal generating means for applying a high frequency signal between the pad and the base of the semiconductor chip bonded by the bonding tool via the wire, The current detection means for detecting a current based on the high frequency signal from the high frequency signal generation means and the level determination means for discriminating the output level obtained by the current detection means are provided, and the discriminative output by the level determination means allows non-bonding of bonding It is configured to detect the state. The above-described bonding non-adhesion detection method and apparatus are configured to send a high frequency signal to the pad of the semiconductor chip via the bonding wire and detect a current based on this high frequency signal. Then, the state of bonding is verified by discriminating the output level based on this current. Therefore, even if the semiconductor chip is, for example, a MOS integrated circuit that is a capacitive element, the state of non-bonding is surely confirmed. Can be detected.

【００１２】[0012]

【発明の実施の形態】本発明に係るワイヤボンディング
装置におけるボンディング不着検出は、ボンディングツ
ールによって被ボンディング部品にワイヤをボンディン
グするボンディング装置において、ボンディングが成さ
れた半導体チップのパッドとベース間に前記ワイヤを介
して高周波信号を印加させると共に、前記ワイヤを介し
て半導体チップに流入する電流に対応する出力レベルを
判定することによって、ボンディングの不着検出を行う
ようにしたものである。このように構成することによっ
て、高周波信号に基づく誘導電流を検出し、この誘導電
流による信号を整流積分してレベルを弁別することによ
り、ボンディングの状態を判別してボンディングの不着
状態を確実に検出することができる。BEST MODE FOR CARRYING OUT THE INVENTION Bonding failure detection in a wire bonding apparatus according to the present invention is performed in a bonding apparatus for bonding a wire to a component to be bonded by a bonding tool. The non-bonding is detected by applying a high-frequency signal via the wire and determining the output level corresponding to the current flowing into the semiconductor chip via the wire. With this configuration, the induced current based on the high-frequency signal is detected, and the signal due to this induced current is rectified and integrated to discriminate the levels, thereby determining the bonding state and reliably detecting the non-bonding state of the bonding. can do.

【００１３】[0013]

【実施例】以下、本発明の実施例について図面を参照し
つつ説明する。図１は本発明のボンディング不着検出装
置の実施例を示したものである。この図１における端子
Ａはクランパ２４に接続され、端子Ｂは半導体チップ２
２のベース２２ａに接続されるものである。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of a non-bonding detection device of the present invention. In FIG. 1, the terminal A is connected to the clamper 24, and the terminal B is the semiconductor chip 2
It is connected to the second base 22a.

【００１４】図１において、高周波信号発生手段として
の高周波信号発生回路１からは数ボルト程度の不着検出
用の高周波信号が間欠的に一定時間発生される。この高
周波信号発生回路１の一方の出力端は電流検出手段とし
てのカレントトランス２の一端に接続されており、カレ
ントトランス２の他端は、前記した端子Ａに接続されて
いる。また前記高周波信号発生回路１の他方の出力端と
端子Ｂとの間には、閉回路の帰路を構成するリード線が
接続されている。In FIG. 1, a high-frequency signal generating circuit 1 as high-frequency signal generating means intermittently generates a high-frequency signal for detecting non-attachment of about several volts for a fixed period of time. One output end of the high frequency signal generating circuit 1 is connected to one end of a current transformer 2 as a current detecting means, and the other end of the current transformer 2 is connected to the above-mentioned terminal A. Further, between the other output end of the high frequency signal generating circuit 1 and the terminal B, a lead wire forming a return path of the closed circuit is connected.

【００１５】前記カレントトランス２は、電流路をＯ型
の磁気コア２ａによって囲み、磁気コア２ａに対して誘
導コイル２ｂを巻回した構成になされており、これによ
り電流・電圧変換器としての作用をする。The current transformer 2 has a structure in which a current path is surrounded by an O-type magnetic core 2a and an induction coil 2b is wound around the magnetic core 2a, whereby the function as a current / voltage converter is obtained. do.

【００１６】そして前記カレントトランス２における誘
導コイル２ｂの出力は、これを直流電圧レベルに変換す
る整流積分回路３に供給されるように成されている。こ
の整流積分回路３は、カレントトランス２からの誘導出
力信号を整流し、整流出力を積分するものである。前記
整流積分回路３による出力はレベル判定手段としてのレ
ベル判定回路４に印加され、このレベル判定回路４にお
いて整流積分回路３からの出力レベルが弁別される。The output of the induction coil 2b in the current transformer 2 is supplied to a rectifying / integrating circuit 3 for converting it into a DC voltage level. The rectification integration circuit 3 rectifies the induction output signal from the current transformer 2 and integrates the rectification output. The output from the rectification / integration circuit 3 is applied to a level determination circuit 4 as level determination means, and the level determination circuit 4 discriminates the output level from the rectification / integration circuit 3.

【００１７】ここで、前記端子Ａは、図４に示すクラン
パ２４及びボンディング用ワイヤ２１を介して第１ボン
ディンク点となる半導体チップ２２におけるパッドに接
続されており、また端子Ｂは半導体チップ２２における
ベース２２ａに接続されている。なお端子Ｂは、ベース
２２ａの他のボンディングステージ等に接続される場合
もある。そして前記半導体チップ２２がＭＯＳタイプで
あった場合には、半導体チップ２２は等価的にコンデン
サＣとしての作用を呈することとなり、図１における端
子Ａ及びＢの間には、等価的にコンデンサＣが接続され
たことになる。Here, the terminal A is connected to a pad on the semiconductor chip 22 which is the first bond point via the clamper 24 and the bonding wire 21 shown in FIG. 4, and the terminal B is on the semiconductor chip 22. It is connected to the base 22a. The terminal B may be connected to another bonding stage or the like of the base 22a. If the semiconductor chip 22 is of the MOS type, the semiconductor chip 22 equivalently acts as the capacitor C, and the capacitor C is equivalently provided between the terminals A and B in FIG. You are connected.

【００１８】図２はボンディングが成される半導体チッ
プがＭＯＳタイプのものである場合における前記図１に
示す各部の信号波形を示している。以下図２に示す信号
波形の説明と共に、図１に示した回路の作用を説明す
る。FIG. 2 shows the signal waveform of each part shown in FIG. 1 when the semiconductor chip to be bonded is of the MOS type. The operation of the circuit shown in FIG. 1 will be described together with the description of the signal waveforms shown in FIG.

【００１９】図２における（ａ）は前記高周波信号発生
回路１からもたらされるサイン波形の高周波信号を示し
ており、この高周波信号（ａ）は電流検出手段としての
カレントトランス２を介して端子Ａに導入される。ここ
で、図２における（ａ′）は作用の説明をし易くするた
めにサイン波形の時間軸を拡大して示しており、以下に
おいて（ａ′）として示すサイン波形の発生タイミング
に基づいて、各部の信号波形を説明する。2A shows a sine waveform high frequency signal provided from the high frequency signal generating circuit 1. The high frequency signal (a) is supplied to the terminal A through a current transformer 2 as a current detecting means. be introduced. Here, (a ′) in FIG. 2 is an enlarged view of the time axis of the sine waveform in order to facilitate the explanation of the action, and based on the generation timing of the sine waveform shown as (a ′) below, The signal waveform of each part will be described.

【００２０】前記端子Ａ及びＢには、正常なボンディン
グが成された場合には、前記したように等価的にコンデ
ンサＣが接続された形に成されるため、端子Ａ，Ｂ間は
高周波信号（ａ′）により、チャージおよびディスチャ
ージが繰り返される。この結果としてカレントトランス
２におけるコイル２ｂには、図２の（ｂ１）として示す
ような誘導波形の出力が発生する。When the terminals A and B are normally bonded, the capacitor C is equivalently connected as described above, so that a high-frequency signal is applied between the terminals A and B. By (a '), charging and discharging are repeated. As a result, the coil 2b of the current transformer 2 produces an induced waveform output as shown in (b1) of FIG.

【００２１】このカレントトランス２からの前記誘導波
形出力（ｂ１）は、整流積分回路３による整流作用によ
り正方向の上半部のみが抽出され、さらに積分されて図
２の（ｃ１）に示すような出力が得られる。この出力
（ｃ１）は、レベル判定回路４において弁別され、レベ
ル判定回路４において予め設定されたスレッショルドレ
ベル（ｄ）よりもレベルが大である場合には、正常なボ
ンディングが成された状態であると判定される。The induced waveform output (b1) from the current transformer 2 is extracted by the rectifying action of the rectifying and integrating circuit 3 only in the upper half portion in the positive direction and further integrated, as shown in (c1) of FIG. Output is obtained. This output (c1) is discriminated by the level determination circuit 4, and when the level is higher than the threshold level (d) set in advance by the level determination circuit 4, normal bonding is performed. Is determined.

【００２２】また第１ボンディング点が不着状態となっ
た場合には、図１における端子Ａ及びＢ間には、等価的
なコンデンサＣは接続されず、解放状態となる。従って
カレントトランス２からは誘導波形は現れず、前記レベ
ル判別器４に対しての出力も発生しないため、レベル判
定回路４においては、第１ボンディング点は不着状態で
あると判定される。When the first bonding point is in a non-attached state, the equivalent capacitor C is not connected between the terminals A and B in FIG. 1 and is in a released state. Therefore, since the induced waveform does not appear from the current transformer 2 and the output to the level discriminator 4 does not occur, the level determining circuit 4 determines that the first bonding point is in the non-attached state.

【００２３】図２に示す波形（ｂ１）及び（ｃ１）は、
端子Ａ及びＢ間に接続される等価的なコンデンサＣの容
量が比較的大きな場合を示している。この等価コンデン
サＣの容量が比較的小さい場合には、カレントトランス
２からの誘導波形出力は、図２の（ｂ２）として示した
ようになり、結果として整流積分回路３による出力は図
２の（ｃ２）として示すようにレベルが小となる。しか
しながらレベル判定回路４において設定されるスレッシ
ョルドレベル（ｄ）を十分に小さな値にしておくことに
より、確実にレベル判定回路４の弁別機能を発揮するこ
とができる。The waveforms (b1) and (c1) shown in FIG.
The case where the capacitance of the equivalent capacitor C connected between the terminals A and B is relatively large is shown. When the capacitance of the equivalent capacitor C is relatively small, the induced waveform output from the current transformer 2 becomes as shown as (b2) in FIG. 2, and as a result, the output by the rectifying and integrating circuit 3 becomes The level becomes small as shown as c2). However, by setting the threshold level (d) set in the level determination circuit 4 to a sufficiently small value, the discriminating function of the level determination circuit 4 can be surely exhibited.

【００２４】ここで、前記レベル判定回路４において設
定される前記スレッショルドレベル（ｄ）は、半導体デ
バイスの等価容量Ｃに対しては十分に小さく、かつ機器
の浮遊容量によって判定を誤らないレベル以上に設定し
ておくことが必要である。Here, the threshold level (d) set in the level determination circuit 4 is sufficiently smaller than the equivalent capacitance C of the semiconductor device, and is equal to or higher than the level at which the determination is not erroneous due to the stray capacitance of the equipment. It is necessary to set it.

【００２５】なお、本発明に係るボンディング不着検出
装置は、ボンディング装置に組み込まれて一体に構成さ
れてもよいことは勿論である。It is needless to say that the non-bonding detection device according to the present invention may be incorporated in the bonding device and integrally formed.

【００２６】[0026]

【発明の効果】以上の説明で明らかなように、本発明に
係るワイヤボンディング装置におけるボンディング不着
検出方法及び不着検出装置によると、ボンディング用ワ
イヤを介して半導体チップの電極に対して一定時間高周
波信号を送り、この高周波信号に基づく誘導電流を検出
するように成される。そして、この誘導電流による信号
を整流積分してレベルを弁別することにより、ボンディ
ングの状態を判別するようにしており、従って半導体チ
ップが例えば容量性の素子である例えばＭＯＳ集積回路
であっても、ボンディングの不着状態を確実に検出する
ことができる。As is apparent from the above description, according to the bonding non-bonding detection method and the non-bonding detection device in the wire bonding apparatus of the present invention, the high frequency signal is supplied to the electrode of the semiconductor chip for a certain time through the bonding wire. To detect the induced current based on this high frequency signal. The signal due to the induced current is rectified and integrated to discriminate the level to determine the bonding state. Therefore, even if the semiconductor chip is a capacitive element, for example, a MOS integrated circuit, It is possible to reliably detect the non-bonding state of bonding.

【図面の簡単な説明】[Brief description of drawings]

【図１】図１は、本発明に係るボンディング不着検出装
置の一実施例を示したブロック図である。FIG. 1 is a block diagram showing an embodiment of a bonding non-sticking detection device according to the present invention.

【図２】図２は、図１における各部の信号波形を示した
波形図である。FIG. 2 is a waveform diagram showing signal waveforms of respective parts in FIG.

【図３】図３は、ボンディングの工程を示した工程図で
ある。FIG. 3 is a process diagram showing a bonding process.

【図４】図４は、従来のボンディング不着検出装置の一
例を示した構成図である。FIG. 4 is a configuration diagram showing an example of a conventional bonding non-sticking detection device.

【符号の説明】[Explanation of symbols]

１ 高周波信号発生回路（高周波信号発生手段） ２ カレントトランス（電流検出手段） ３ 整流積分回路 ４ レベル判定回路（レベル判定手段） ２０ キャピラリ（ボンディングツール） ２１ ワイヤ ２２ 半導体チップ ２３ リード ２４ クランパ 1 high-frequency signal generation circuit (high-frequency signal generation means) 2 current transformer (current detection means) 3 rectification integration circuit 4 level determination circuit (level determination means) 20 capillary (bonding tool) 21 wire 22 semiconductor chip 23 lead 24 clamper

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 ボンディングツールによって被ボンディ
ング部品にワイヤをボンディングするボンディング装置
において、ボンディングが成された半導体チップのパッ
ドとベース間に前記ワイヤを介して高周波信号を印加さ
せると共に、前記ワイヤを介して半導体チップに流入す
る電流に対応する出力レベルを判定することによって、
ボンディングの不着検出を行うようにしたことを特徴と
するワイヤボンディング装置におけるボンディング不着
検出方法。1. A bonding apparatus for bonding a wire to a component to be bonded by a bonding tool, wherein a high frequency signal is applied between the pad and the base of a bonded semiconductor chip through the wire and the wire is also passed through the wire. By determining the output level corresponding to the current flowing into the semiconductor chip,
A method for detecting non-bonding in a wire bonding apparatus, wherein non-bonding detection of bonding is performed. 【請求項２】 ボンディングツールによってボンディン
グが成された半導体チップのパッドとベース間にワイヤ
を介して高周波信号を印加させるための高周波信号発生
手段と、前記高周波信号発生手段からの高周波信号に基
づく電流を検出する電流検出手段と、前記電流検出手段
によって得られる出力レベルを弁別するレベル判定手段
とを備え、 前記レベル判定手段による弁別出力により、ボンディン
グの不着状態を検出するようにしたことを特徴とするワ
イヤボンディング装置におけるボンディング不着検出装
置。2. A high frequency signal generating means for applying a high frequency signal between a pad and a base of a semiconductor chip bonded by a bonding tool via a wire, and a current based on the high frequency signal from the high frequency signal generating means. And a level determination means for discriminating the output level obtained by the current detection means, and the non-bonding state of the bonding is detected by the discrimination output by the level determination means. Non-bonding detection device for wire bonding equipment.
JP23762695A 1995-08-23 1995-08-23 Method and apparatus for detecting defective bonding in wire bonding device Pending JPH0964116A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23762695A JPH0964116A (en) 1995-08-23 1995-08-23 Method and apparatus for detecting defective bonding in wire bonding device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23762695A JPH0964116A (en) 1995-08-23 1995-08-23 Method and apparatus for detecting defective bonding in wire bonding device

Publications (1)

Publication Number Publication Date
JPH0964116A true JPH0964116A (en) 1997-03-07

Family

ID=17018115

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23762695A Pending JPH0964116A (en) 1995-08-23 1995-08-23 Method and apparatus for detecting defective bonding in wire bonding device

Country Status (1)

Country Link
JP (1) JPH0964116A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110118817A (en) * 2019-05-31 2019-08-13 云谷（固安）科技有限公司 Conducting wire testing apparatus and its detection method
KR20220018470A (en) 2020-08-04 2022-02-15 야마하 로보틱스 홀딩스 가부시키가이샤 Wire bonding state determination method and wire bonding state determination apparatus
KR20230049713A (en) 2021-05-10 2023-04-13 야마하 로보틱스 홀딩스 가부시키가이샤 Defect detection device and defect detection method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110118817A (en) * 2019-05-31 2019-08-13 云谷（固安）科技有限公司 Conducting wire testing apparatus and its detection method
KR20220018470A (en) 2020-08-04 2022-02-15 야마하 로보틱스 홀딩스 가부시키가이샤 Wire bonding state determination method and wire bonding state determination apparatus
KR20230049713A (en) 2021-05-10 2023-04-13 야마하 로보틱스 홀딩스 가부시키가이샤 Defect detection device and defect detection method

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