JP4056505B2 - Wire bonding equipment - Google Patents

Wire bonding equipment Download PDF

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JP4056505B2
JP4056505B2 JP2004246201A JP2004246201A JP4056505B2 JP 4056505 B2 JP4056505 B2 JP 4056505B2 JP 2004246201 A JP2004246201 A JP 2004246201A JP 2004246201 A JP2004246201 A JP 2004246201A JP 4056505 B2 JP4056505 B2 JP 4056505B2
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wire
time
detection
voltage
bonding
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JP2006066565A (en
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志信 石井
正幹 齊藤
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Kaijo Corp
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Kaijo Corp
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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

本発明は、ワイヤボンディング装置に係わり、特に、静電容量が低いデバイスに対しても不着検出が可能なワイヤボンディング装置に関する。   The present invention relates to a wire bonding apparatus, and more particularly, to a wire bonding apparatus capable of detecting non-sticking even with respect to a device having a low capacitance.

ワイヤボンディング装置は、金線、アルミニウムなどからなるワイヤを用いて第１ボンディング点となる半導体チップ上の電極と、第２ボンディング点となるリードとを接続するものである。   The wire bonding apparatus connects an electrode on a semiconductor chip serving as a first bonding point and a lead serving as a second bonding point using a wire made of gold wire, aluminum, or the like.

二次元方向に移動可能なＸＹテーブル上に搭載されたボンディングヘッドのリニアモータ若しくはモータ軸に連結したカムなどによりボンディングアームが上下に揺動され、このボンディングアームの超音波ホーンの先端に取り付けられたキャピラリからワイヤが送り出され、このワイヤの先端と放電電極との間に高電圧を印加することにより放電を起こさせる。その放電エネルギーによってワイヤの先端を溶融させてワイヤの先端にボールを形成する。そしてキャピラリの先端に保持されたボールを第１ボンディング点である半導体チップの電極にボンディングアームの揺動による機械的な加圧力により押し付けつつ、超音波及び加熱手段を併用して熱圧着を行い、第１ボンディング点に対してワイヤを接続する。   The bonding arm was swung up and down by a linear motor of a bonding head mounted on an XY table movable in two dimensions or a cam connected to a motor shaft, and attached to the tip of the ultrasonic horn of this bonding arm. A wire is sent out from the capillary, and discharge is caused by applying a high voltage between the tip of the wire and the discharge electrode. The tip of the wire is melted by the discharge energy to form a ball at the tip of the wire. Then, while pressing the ball held at the tip of the capillary against the electrode of the semiconductor chip that is the first bonding point by mechanical pressure by swinging the bonding arm, thermocompression bonding is performed using both ultrasonic and heating means, A wire is connected to the first bonding point.

図５（ａ）乃至（ｄ）は、上記ワイヤボンディング装置によるワイヤボンディングを行う工程を説明する図である。
図５（ａ）及び（ｂ）に示すように、キャピラリ２の先端に送り出されたワイヤ１の先端と放電電極４との間で放電を一定の時間起こさせ、ワイヤ１の先端を溶融してボール２０を形成し、キャピラリ２の先端で保持してキャピラリ２を第１ボンディング点１５なる半導体チップ１３の電極１２の直上に位置させる。 FIGS. 5A to 5D are views for explaining a process of performing wire bonding by the wire bonding apparatus.
As shown in FIGS. 5 (a) and 5 (b), discharge is caused between the tip of the wire 1 fed to the tip of the capillary 2 and the discharge electrode 4 for a certain period of time, and the tip of the wire 1 is melted. A ball 20 is formed and held at the tip of the capillary 2, and the capillary 2 is positioned immediately above the electrode 12 of the semiconductor chip 13, which is the first bonding point 15.

次に、図５（ｃ）に示すように、キャピラリ２を下降させてボール２０を電極１２に押し付けて加圧すると同時にキャピラリ２の先端に対して前記ボンディングアームの超音波ホーンを介して超音波振動を印加する。これにより、電極にワイヤ１を接続する。
次いで、図５（ｄ）に示すようにキャピラリ２を所定のループコントロールに従って上昇させ、第２ボンディング点１６となるリード１４方向に移動させる。 Next, as shown in FIG. 5C, the capillary 2 is lowered and the ball 20 is pressed against the electrode 12 to pressurize it. At the same time, the ultrasonic wave is applied to the tip of the capillary 2 via the ultrasonic horn of the bonding arm. Apply vibration. Thereby, the wire 1 is connected to the electrode.
Next, as shown in FIG. 5D, the capillary 2 is raised according to a predetermined loop control and moved in the direction of the lead 14 that becomes the second bonding point 16.

次に、キャピラリ２を下降させワイヤ１をリード１４に押し付けて加圧すると同時にキャピラリ２の先端に対して超音波ホーンを介して超音波振動を印加してリード１４に対しワイヤ１を接続する。この後、キャピラリ２を上昇させてあらかじめ設定されたキャピラリ２の上昇位置でワイヤカットクランプ３を閉じ、リード１４上のワイヤをカットして一回のボンディング作業が完了する。   Next, the capillary 2 is lowered to press and pressurize the wire 1 against the lead 14, and at the same time, ultrasonic vibration is applied to the tip of the capillary 2 through an ultrasonic horn to connect the wire 1 to the lead 14. Thereafter, the capillary 2 is raised and the wire cut clamp 3 is closed at a preset position where the capillary 2 is raised, and the wire on the lead 14 is cut to complete one bonding operation.

従来のワイヤボンディング装置は、半導体チップ１３の電極１２にボール２０を押しつぶしてボンディングが行われた状態で、ボンディングが確実に成されたか否か、すなわちワイヤが不着状態であるか否かを不着検出装置によって判断している。この不着検出装置は、次のような手順で不着検出が行われる。   The conventional wire bonding apparatus detects whether or not bonding has been performed reliably, that is, whether or not the wire is in a non-attached state, in a state where the ball 20 is crushed to the electrode 12 of the semiconductor chip 13 and the bonding is performed. It is determined by the device. This non-stick detection device detects non-stick in the following procedure.

図６は、従来の不着検出方法を示すフローチャートである。
ボンディング前に検出区間・開始位置、検出しきい値を一括で設定する（ＳＴ１，ＳＴ２）。なお、検出区間、開始位置、検出しきい値をワイヤ毎に設定することはできない。 FIG. 6 is a flowchart showing a conventional non-stick detection method.
Before the bonding, the detection section / start position and detection threshold are set in a batch (ST1, ST2). Note that the detection section, start position, and detection threshold cannot be set for each wire.

次いで、半導体チップの電極とリードとをワイヤによって接続するワイヤボンディングを行う（ＳＴ３）。そして、ワイヤが半導体チップの電極に確実にボンディングされたか否かの不着検出を行う（ＳＴ４）。このとき、ワイヤが不着であると判断した場合、ワイヤボンディング装置を停止するなどのエラー処理が行われる。また、ワイヤが確実にボンディングされたと判断した場合、次のワイヤボンディングを行い、同様に不着検出を行う（ＳＴ３，ＳＴ４）。すべてのワイヤボンディングが行われたらワイヤボンディング作業を終了する（ＳＴ５）。   Next, wire bonding for connecting the electrodes of the semiconductor chip and the leads with wires is performed (ST3). Then, non-sticking detection is performed as to whether or not the wire is securely bonded to the electrode of the semiconductor chip (ST4). At this time, if it is determined that the wire is not attached, error processing such as stopping the wire bonding apparatus is performed. If it is determined that the wire has been securely bonded, the next wire bonding is performed and non-stick detection is similarly performed (ST3, ST4). When all wire bonding is performed, the wire bonding operation is finished (ST5).

次に、上記不着検出方法を実施する不着検出装置について説明する。
図７は、従来のワイヤボンディング装置のＤＣ専用不着検出装置を示すブロック図である。ＤＣ専用不着検出装置は、ＤＣ特性を有する半導体チップ専用の不着検出を行うものである。
ＤＣ専用不着検出装置は、ＤＣ用不着検出基板４４及びボンディングＣＰＵ基板１８を有している。ボンディングＣＰＵ基板１８はＩ／Ｏポート３２を備えている。ＤＣ用不着検出基板４４は、Ｉ／Ｏポート３３、ＣＰＵ３０、Ａ／Ｄコンバータ３５、増幅器（ＡＭＰ）３７、直流発生器４５及び抵抗４６を備えている。 Next, a non-stick detection device that implements the non-stick detection method will be described.
FIG. 7 is a block diagram showing a DC non-stick detection device of a conventional wire bonding apparatus. The DC non-stick detection device performs non-stick detection dedicated to a semiconductor chip having DC characteristics.
The DC non-stick detection device has a DC non-stick detection substrate 44 and a bonding CPU substrate 18. The bonding CPU board 18 includes an I / O port 32. The DC non-adherence detection board 44 includes an I / O port 33, a CPU 30, an A / D converter 35, an amplifier (AMP) 37, a DC generator 45, and a resistor 46.

出力部３８は、図５に示すワイヤボンディング装置のワイヤ１に接続されている。また、接地電位（ＧＮＤ）３９は、半導体チップ１３が載置されたボンディングステージに出力部３８を介して接続されている。   The output unit 38 is connected to the wire 1 of the wire bonding apparatus shown in FIG. The ground potential (GND) 39 is connected to the bonding stage on which the semiconductor chip 13 is placed via the output unit 38.

ＤＣ専用不着検出装置を用いて不着検出を行う場合、ワイヤボンディング時に直流発生器４５から抵抗４６、出力部３８、ワイヤ１を介して半導体チップ１３の電極１２に電圧が印加される。そして、半導体チップ１３の電極１２からワイヤ１を介して検出信号が増幅器３７に入力され、増幅器３７から出力された出力信号がＡ／Ｄコンバータ３５によってＡＤ変換されＣＰＵ３０に入力される。このＣＰＵ３０において、検出された信号がしきい値内であれば正常にボンディングされたと判断され、検出信号がしきい値から外れていれば異常ボンディング（即ち不着）であると判断される。そして、正常ボンディングであるか不着であるかの信号がＩ／Ｏポート３３，３２を介してボンディングＣＰＵ基板１８に入力され、不着検出が行われる。   When non-stick detection is performed using a DC non-stick detector, a voltage is applied from the DC generator 45 to the electrode 12 of the semiconductor chip 13 via the resistor 46, the output unit 38, and the wire 1 during wire bonding. A detection signal is input from the electrode 12 of the semiconductor chip 13 to the amplifier 37 via the wire 1, and an output signal output from the amplifier 37 is AD converted by the A / D converter 35 and input to the CPU 30. In this CPU 30, if the detected signal is within the threshold value, it is determined that the bonding is normally performed, and if the detected signal is outside the threshold value, it is determined that the bonding is abnormal (that is, non-bonding). A signal indicating whether the bonding is normal or non-bonding is input to the bonding CPU board 18 via the I / O ports 33 and 32, and non-bonding detection is performed.

図８は、従来のワイヤボンディング装置のＡＣ専用不着検出装置の具体的な構成を示す回路図である（特許文献１参照）。ＡＣ専用不着検出装置は、ＡＣ特性を有する半導体チップ専用の不着検出を行うものである。
ワイヤスプール２１より繰り出されたワイヤ１は、ワイヤ１の保持、解放が可能なワイヤカットクランプ３の保持面の間を通り、ワイヤカットクランプ３の直下に位置するキャピラリ２を挿通している。ワイヤスプール２１のワイヤの端であるスプールワイヤ端２２と、フレームとしてのリードフレーム１１を載置する基準電位点であるボンディングステージ１７との間には交流ブリッジ回路５が接続されている。 FIG. 8 is a circuit diagram showing a specific configuration of an AC non-stick detection device of a conventional wire bonding apparatus (see Patent Document 1). The AC non-stick detection device performs non-stick detection dedicated to a semiconductor chip having AC characteristics.
The wire 1 fed out from the wire spool 21 passes between the holding surfaces of the wire cut clamp 3 that can hold and release the wire 1 and is inserted through the capillary 2 positioned immediately below the wire cut clamp 3. An AC bridge circuit 5 is connected between a spool wire end 22 which is an end of a wire of the wire spool 21 and a bonding stage 17 which is a reference potential point on which the lead frame 11 as a frame is placed.

この交流ブリッジ回路５は交流発生器５ａを備え、前記交流発生器５ａは所定の周波数で発振する正弦波発振回路を内蔵している。交流ブリッジ回路５は、交流発生器５ａと、交流発生器５ａからの出力信号を受ける可変抵抗器Ｒ１とコンデンサＣ１からなる第１直列回路５ｃ１、交流発生器５からの交流信号を受ける固定抵抗Ｒ２と、スプールワイヤ端２２から基準電位点であるボンディングステージ１７に至る電気経路を含む第２直列回路５ｃ２とで閉ループを形成している。   The AC bridge circuit 5 includes an AC generator 5a, and the AC generator 5a includes a sine wave oscillation circuit that oscillates at a predetermined frequency. The AC bridge circuit 5 includes an AC generator 5a, a first series circuit 5c1 composed of a variable resistor R1 that receives an output signal from the AC generator 5a and a capacitor C1, and a fixed resistor R2 that receives an AC signal from the AC generator 5. And a second series circuit 5c2 including an electrical path from the spool wire end 22 to the bonding stage 17 which is a reference potential point, forms a closed loop.

また、前記可変抵抗Ｒ１と、コンデンサＣ１との間の第１接続点Ｘは、差動増幅器６の一方の入力端に接続され、前記固定抵抗Ｒ２と前記スプールワイヤ端２２との間の第２接続点Ｙが、前記差動増幅器６の他方の入力端に接続されている。
前記固定抵抗Ｒ２とスプールワイヤ端２２との間には、同軸ケーブル５ｂが外来ノイズの影響を避けるために接続されている。従って、同軸ケーブル５ｂの芯線と外被との間で発生する同軸ケーブル５ｂの静電容量Ｃ２が生じ、静電容量Ｃ２が等価的に固定抵抗Ｒ２とボンディングステージ１７との間に接続されることになる。 A first connection point X between the variable resistor R1 and the capacitor C1 is connected to one input end of the differential amplifier 6, and a second connection point between the fixed resistor R2 and the spool wire end 22 is connected. A connection point Y is connected to the other input terminal of the differential amplifier 6.
A coaxial cable 5b is connected between the fixed resistor R2 and the spool wire end 22 in order to avoid the influence of external noise. Accordingly, a capacitance C2 of the coaxial cable 5b generated between the core wire of the coaxial cable 5b and the jacket is generated, and the capacitance C2 is equivalently connected between the fixed resistor R2 and the bonding stage 17. become.

差動増幅器６は、演算増幅器Ａ１、演算増幅器Ａ２、抵抗Ｒ３、抵抗Ｒ４、抵抗Ｒ５より構成される。この差動増幅器６は、前記第１接続点Ｘ、第２接続点Ｙから両入力端に供給される信号入力の差成分を検出して出力するものであり、前記差動増幅器６の出力端には、コンデンサＣ及びトランス７の一次側入力端子が直列に接続されている。   The differential amplifier 6 includes an operational amplifier A1, an operational amplifier A2, a resistor R3, a resistor R4, and a resistor R5. The differential amplifier 6 detects and outputs a difference component between signal inputs supplied from the first connection point X and the second connection point Y to both input terminals. The output terminal of the differential amplifier 6 The capacitor C and the primary side input terminal of the transformer 7 are connected in series.

トランス７の二次側出力端子は、絶対値変換器８に接続されており、絶対値変換器８は、トランス７より出力される正極性及び負極性の交流電圧を正極性の絶対値電圧に変換するものである。そして絶対値変換器８の出力端には第１レベル弁別器９が接続され、第１レベル弁別器９の出力はボンディング判定器２６に入力され不着状態を検出するようにしている。   The secondary output terminal of the transformer 7 is connected to an absolute value converter 8, and the absolute value converter 8 converts the positive and negative AC voltages output from the transformer 7 into positive absolute voltage. To convert. The first level discriminator 9 is connected to the output terminal of the absolute value converter 8, and the output of the first level discriminator 9 is input to the bonding determiner 26 so as to detect the non-attached state.

また、交流ブリッジ回路５の第２接続点Ｙに接続された差動増幅器６の演算増幅器Ａ１の出力端子には、ローパスフィルタ２３が接続されている。ローパスフィルタ２３の出力は、第２レベル弁別器２４に入力される。第２レベル弁別器２４は、ローパスフィルタ２３の出力信号を前もって設定された基準の信号レベルと比較し、ローパスフィルタ２３の出力信号が基準の信号レベル以上であれば論理値“０”の信号を論理積器２５に出力し、ローパスフィルタ２３の出力信号が基準の信号レベル以下であれば論理値“１”の信号を論理積器２５に出力する。   A low-pass filter 23 is connected to the output terminal of the operational amplifier A1 of the differential amplifier 6 connected to the second connection point Y of the AC bridge circuit 5. The output of the low pass filter 23 is input to the second level discriminator 24. The second level discriminator 24 compares the output signal of the low-pass filter 23 with a reference signal level set in advance. If the output signal of the low-pass filter 23 is equal to or higher than the reference signal level, a signal having a logical value “0” is output. If the output signal from the low-pass filter 23 is equal to or lower than the reference signal level, a signal having a logical value “1” is output to the logical multiplier 25.

ボンディング検出切替器２７は第１ボンディング（チップボンディング）時に論理値“１”の信号を出力し、第２ボンディング（リードボンディング）時に論理値“０”の信号を論理積器２５に出力する。論理積器２５は、ボンディング検出切替器２７の出力信号と第２レベル弁別器２４の出力との論理積（ＡＮＤ演算）を行い、第１ボンディング（チップボンディング）時には、論理値“１”又は“０”をボンディング判定器２６に出力し、第２ボンディング（リードボンディング）時には、常に論理値“０”をボンディング判定器２６に出力する。   The bonding detection switching unit 27 outputs a signal having a logical value “1” during the first bonding (chip bonding), and outputs a signal having a logical value “0” to the logical product 25 during the second bonding (lead bonding). The logical product unit 25 performs a logical product (AND operation) of the output signal of the bonding detection switching unit 27 and the output of the second level discriminator 24. At the first bonding (chip bonding), the logical value “1” or “ 0 ”is output to the bonding determination unit 26, and the logical value“ 0 ”is always output to the bonding determination unit 26 during the second bonding (lead bonding).

ボンディング判定器２６は、第１ボンディング点としての半導体チップ１３上の電極１２又は第２ボンディング点としてのリードフレーム１１のリード１４にボンディング接続したとき、不着検出タイミング、すなわちボンディング装置からの指令により不着検出モードでの検出を行う状態で論理積器２５からの出力信号を読みとり、不着検出を行う設定となっている。   When the bonding determination unit 26 is bonded to the electrode 12 on the semiconductor chip 13 as the first bonding point or the lead 14 of the lead frame 11 as the second bonding point, the bonding determination unit 26 is not attached according to the non-stick detection timing, that is, a command from the bonding apparatus. The output signal from the AND circuit 25 is read in a state where detection in the detection mode is performed, and non-delivery detection is performed.

特開２０００−２６０８０８号公報（４〜５頁、図１）JP 2000-260808 A (pages 4-5, FIG. 1)

ところで、上記従来のワイヤボンディング装置における不着検出装置では、ＤＣ専用不着検出装置及びＡＣ専用不着検出装置のいずれにおいてもＡＣ又はＤＣの出力電圧に対する検出電圧の差を判定することにより正常着であるか不着であるかを判別している。この方式では、ＤＣ専用不着検出とＡＣ専用不着検出と共に、検出電圧の波形が定常状態になってからの電圧値を検出電圧としている。このため、検出対象物である半導体チップ及びリードフレームが一定以上の大きさの静電容量（例えば１００ＰＦ程度）を有していなければ、出力電圧と検出電圧との間に正常着であるか不着であるかを判定するのに必要な差が生じにくい。言い換えると、数ＰＦから数十ＰＦといった極めて低い静電容量しか有さない検出対象物については、従来の不着検出装置で不着検出を行うことができない。また、検出対象物の低静電容量化はますます進む方向にある。   By the way, in the non-stick detection device in the above-mentioned conventional wire bonding apparatus, is it normal wearing by determining the difference between the detection voltage with respect to the output voltage of AC or DC in both the DC non-stick detection device and the AC dedicated non-stick detection device? It is determined whether it is non-delivery. In this method, the detection voltage is a voltage value after the waveform of the detection voltage is in a steady state, together with DC-only non-stick detection and AC-only non-stick detection. For this reason, if the semiconductor chip and the lead frame, which are detection objects, do not have a certain capacitance or more (for example, about 100 PF), the output voltage and the detection voltage are normal or non-adherent. The difference necessary to determine whether or not is less likely to occur. In other words, a non-stick detection cannot be performed by a conventional non-stick detection device for a detection target having an extremely low capacitance such as several PF to several tens of PF. In addition, the reduction in the capacitance of the detection target is in the direction of further progress.

本発明は上記のような事情を考慮してなされたものであり、その目的は、静電容量が低いデバイスに対しても不着検出が可能なワイヤボンディング装置を提供することにある。   The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a wire bonding apparatus capable of detecting non-bonding even for a device having a low capacitance.

上記課題を解決するため、本発明に係るワイヤボンディング装置は、半導体チップの電極とリードフレームのリードをワイヤによって接続するワイヤボンディング装置又は半導体チップのパッドにバンプをボンディングするワイヤボンディング装置において、
ＤＣ電圧をワイヤ又はバンプに印加するＤＣ印加手段と、
前記ワイヤ又はバンプからの検出電圧を検出する電圧検出手段と、
前記ＤＣ電圧を印加した時から前記検出電圧が検出しきい値電圧に達した時又は超えた時までの第１時間を検出する時間検出手段と、
前記第１時間と、ボンディングが不着のワイヤ又はバンプに前記ＤＣ電圧を印加した時から前記検出しきい値電圧に達するまで又は超えるまでの第２時間とを比較することにより、ワイヤ又はバンプが正常にボンディング接続されたか否かを判定する判定手段とを具備することを特徴とする。 In order to solve the above problems, a wire bonding apparatus according to the present invention is a wire bonding apparatus that connects electrodes of a semiconductor chip and leads of a lead frame by wires, or a wire bonding apparatus that bonds bumps to pads of a semiconductor chip.
DC application means for applying a DC voltage to the wire or bump;
Voltage detection means for detecting a detection voltage from the wire or bump;
Time detection means for detecting a first time from when the DC voltage is applied to when the detection voltage reaches or exceeds a detection threshold voltage;
The wire or bump is normal by comparing the first time with the second time from when the DC voltage is applied to the wire or bump to which bonding is not applied until the detection threshold voltage is reached or exceeded. And determining means for determining whether or not a bonding connection is made.

上記本発明に係るワイヤボンディング装置では、ボンディング対象物が静電容量を有するため、正常着である場合の検出しきい値電圧に達した時又は超えた時までの第１時間が、不着である場合の検出しきい値電圧に達するまで又は超えるまでの第２時間に比べて長いことを利用する。これにより、検出対象物の静電容量が極めて小さい場合でも第１時間と第２時間とを比較することができ、それにより不着検出が可能となる。   In the above-described wire bonding apparatus according to the present invention, since the bonding target has a capacitance, the first time until the detection threshold voltage in the case of normal wearing is reached or exceeded is not attached. The advantage is that it is longer than the second time until the detection threshold voltage is reached or exceeded. As a result, even when the capacitance of the detection target is extremely small, the first time and the second time can be compared, thereby enabling non-stick detection.

また、本発明に係るワイヤボンディング装置において、前記ＤＣ印加手段は、ＤＣパルス信号をワイヤ又はバンプに印加する手段であることが好ましい。   In the wire bonding apparatus according to the present invention, the DC applying means is preferably means for applying a DC pulse signal to the wire or the bump.

また、本発明に係るワイヤボンディング装置において、前記判定手段は、前記第１時間が前記第２時間より長ければワイヤ又はバンプが正常にボンディング接続されたと判定し、前記第１時間が前記第２時間に比べて長くなければワイヤ又はバンプが不着であると判定する手段であることが好ましい。   Further, in the wire bonding apparatus according to the present invention, the determination unit determines that the wire or the bump is normally bonded and connected if the first time is longer than the second time, and the first time is the second time. If it is not longer than the above, it is preferable to determine that the wire or bump is not attached.

また、本発明に係るワイヤボンディング装置において、前記ＤＣ印加手段はＣＰＵ、Ｄ／Ａコンバータ及び抵抗を有し、
前記電圧検出手段は増幅器及びＣＰＵを有し、
前記時間検出手段は、前記ＤＣ電圧を印加した時からの時間をカウントするタイマー回路、前記検出電圧と前記検出しきい値電圧を比較する比較回路、及び、前記検出電圧が前記検出しきい値電圧を超えたか否かを判定する判定回路を有し、
前記判定手段は、前記第１時間と前記第２時間を比較する比較回路、前記第１時間が前記第２時間より長いか短いかを判定する判定回路、及びＣＰＵを有していることも可能である。 Moreover, in the wire bonding apparatus according to the present invention, the DC application means includes a CPU, a D / A converter, and a resistor,
The voltage detection means includes an amplifier and a CPU,
The time detection means includes a timer circuit that counts time from when the DC voltage is applied, a comparison circuit that compares the detection voltage with the detection threshold voltage, and the detection voltage is the detection threshold voltage. Having a determination circuit for determining whether or not
The determination means may include a comparison circuit that compares the first time and the second time, a determination circuit that determines whether the first time is longer or shorter than the second time, and a CPU. It is.

また、本発明に係るワイヤボンディング装置においては、前記検出しきい値電圧及び前記第２時間を予め設定しておき、前記ＤＣ印加手段によりＤＣ電圧をワイヤ又はバンプに印加し、前記電圧検出手段によりワイヤ又はバンプからの検出電圧を検出し、前記時間検出手段により前記第１時間を検出し、前記判定手段により前記第１時間と前記第２時間とを比較してワイヤ又はバンプが正常にボンディング接続されたか否かを判定することをソフトウエア制御により行うことが好ましい。   In the wire bonding apparatus according to the present invention, the detection threshold voltage and the second time are set in advance, a DC voltage is applied to the wire or the bump by the DC application means, and the voltage detection means is used. The detected voltage from the wire or bump is detected, the first time is detected by the time detecting means, and the first time is compared with the second time by the determining means, and the wire or bump is normally bonded. It is preferable to determine whether or not it has been performed by software control.

以上説明したように本発明によれば、静電容量が低いデバイスに対しても不着検出が可能なワイヤボンディング装置を提供することができる。   As described above, according to the present invention, it is possible to provide a wire bonding apparatus capable of detecting non-bonding even for a device having a low capacitance.

発明を実施するための形態BEST MODE FOR CARRYING OUT THE INVENTION

以下、図面を参照して本発明の実施の形態について説明する。
図１は、本発明の実施の形態による不着検出装置を模式的に示すブロック図である。図２は、図１に示す不着検出基板とワイヤボンディング装置との配線による接続関係を概略的に示す図である。なお、従来のワイヤボンディング装置と同一の構造及び機能を有する部分については要部のみを説明し、詳細な説明は省略する。 Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram schematically showing a non-stick detection device according to an embodiment of the present invention. FIG. 2 is a diagram schematically showing a connection relationship between the non-stick detection substrate and the wire bonding apparatus shown in FIG. 1 by wiring. In addition, about the part which has the same structure and function as the conventional wire bonding apparatus, only a principal part is demonstrated and detailed description is abbreviate | omitted.

本実施の形態による不着検出装置は、ＤＣパルス方式によるものであり、検出区間・開始位置などのパラメータ設定項目について、ワイヤ毎に設定できるものである。尚、ＡＣ／ＤＣ特性の混在しているデバイスに対しても不着検出は可能である。   The non-sticking detection apparatus according to the present embodiment is based on the DC pulse method, and can set parameter setting items such as detection section and start position for each wire. Note that non-delivery detection is possible even for devices with mixed AC / DC characteristics.

図１に示すように、不着検出装置は、ＤＣパルス方式不着検出基板１０、ボンディングＣＰＵ基板１８及びメインＣＰＵ基板１９を有している。メインＣＰＵ基板１９はＣＰＵ２８を備えており、このＣＰＵ２８はキーボード３１に接続されている。検出区間・開始位置、検出しきい値などのワイヤ毎のパラメータをキーボード３１によって入力することができる。   As shown in FIG. 1, the non-stick detection device includes a DC pulse system non-stick detection board 10, a bonding CPU board 18, and a main CPU board 19. The main CPU board 19 includes a CPU 28, which is connected to a keyboard 31. Parameters for each wire such as a detection section / start position and a detection threshold value can be input by the keyboard 31.

ボンディングＣＰＵ基板１８はＩ／Ｏポート３２及びＣＰＵ２９を備えており、ＣＰＵ２９はＣＰＵ２８に接続されている。
ＤＣパルス方式不着検出基板１０は、Ｉ／Ｏポート３３、ＣＰＵ３０、比較回路Ｃとタイマー回路Ｔと判定回路Ｊを有する回路群４１、増幅器（ＡＭＰ）３７、メモリ３４、Ｄ／Ａコンバータ３６及び抵抗４０を備えている。 The bonding CPU board 18 includes an I / O port 32 and a CPU 29, and the CPU 29 is connected to the CPU 28.
The DC pulse system non-stick detection substrate 10 includes an I / O port 33, a CPU 30, a circuit group 41 having a comparison circuit C, a timer circuit T, and a determination circuit J, an amplifier (AMP) 37, a memory 34, a D / A converter 36, and a resistor. 40.

Ｉ／Ｏポート３３の入力側はＣＰＵ３０に接続されており、Ｉ／Ｏポート３３の出力側はＩ／Ｏポート３２に接続されている。また、ＣＰＵ３０は回路群４１に接続されており、この回路群４１は増幅器（ＡＭＰ）３７に接続されている。ＣＰＵ３０はＤ／Ａコンバータ３６に接続されており、Ｄ／Ａコンバータ３６は抵抗４０に接続されている。また、ＣＰＵ３０はメモリ３４に接続されている。   The input side of the I / O port 33 is connected to the CPU 30, and the output side of the I / O port 33 is connected to the I / O port 32. The CPU 30 is connected to a circuit group 41, and the circuit group 41 is connected to an amplifier (AMP) 37. The CPU 30 is connected to the D / A converter 36, and the D / A converter 36 is connected to the resistor 40. The CPU 30 is connected to the memory 34.

出力部３８は、図２に示すワイヤ（金線）１に接続されている。また、接地電位（ＧＮＤ）３９は、半導体チップ１３が載置されたボンディングステージに出力部を介して接続されている。   The output unit 38 is connected to a wire (gold wire) 1 shown in FIG. The ground potential (GND) 39 is connected to the bonding stage on which the semiconductor chip 13 is placed via the output unit.

次に、上記不着検出装置によって不着検出を行う方法について図１乃至図４を参照しつつ説明する。
図３は、図１に示す不着検出装置によって不着検出を行う流れを示すフローチャートである。図４は、図１に示す不着検出装置によって不着検出を行う際、出力電圧Ｅをワイヤに印加してから時間ｔの経過による検出電圧Ｖｃの変化を示す図である。参照符号４２は不着（オープン）波形を示しており、参照符号４３は正常着波形を示している。Ｖｃ１は不着検出用しきい値電圧を示している。 Next, a method of performing non-stick detection by the non-stick detection device will be described with reference to FIGS.
FIG. 3 is a flowchart showing the flow of non-stick detection by the non-stick detection device shown in FIG. FIG. 4 is a diagram showing a change in the detection voltage Vc as time elapses after the output voltage E is applied to the wire when non-stick detection is performed by the non-stick detection device shown in FIG. Reference numeral 42 indicates a non-attached (open) waveform, and reference numeral 43 indicates a normal arrival waveform. Vc1 represents a non-stick detection threshold voltage.

まず、半導体チップとリードとを接続するボンディングを行う前に、半導体チップ１３におけるワイヤ毎について、検出区間・開始位置、ＤＣパルス方式、不着検出用しきい値電圧、時間ｔ１などのパラメータ設定項目をキーボード３１から入力する。これにより、メインＣＰＵ基板１９のＣＰＵ２８にパラメータ設定項目が入力される。   First, before performing bonding for connecting the semiconductor chip and the lead, parameter setting items such as a detection section / start position, a DC pulse method, a non-stick detection threshold voltage, and a time t1 are set for each wire in the semiconductor chip 13. Input from the keyboard 31. Thereby, the parameter setting item is input to the CPU 28 of the main CPU board 19.

尚、不着検出用しきい値電圧は、図１及び図２に示す不着検出装置を備えたワイヤボンディング装置によって予め実測した電圧値を用いる。具体的には、意図的に不着（オープン）であるワイヤボンディングを行い、その際に出力電圧Ｅをワイヤに印加してから時間ｔ１が経過した時の検出電圧Ｖｃを測定し、この測定した電圧値から不着検出用しきい値電圧Ｖｃ１を決定する。この時間ｔ１における検出電圧Ｖｃの測定を１回だけ行い、その測定値を不着検出用しきい値電圧としても良いし、その測定値に所定の電圧値を加算したものを不着検出用しきい値電圧としても良い。また、このような測定を複数回行うことも好ましく、その場合は複数の測定値のうち最も高い電圧値を不着検出用しきい値電圧としても良いし、最も高い電圧値に所定の電圧値を加算したものを不着検出用しきい値電圧としても良いし、また複数の測定値の平均値を不着検出用しきい値電圧としても良いし、前記平均値に所定の電圧値を加算したものを不着検出用しきい値電圧としても良い。   As the non-stick detection threshold voltage, a voltage value measured in advance by a wire bonding apparatus including the non-stick detection device shown in FIGS. 1 and 2 is used. Specifically, wire bonding that is intentionally non-bonded (open) is performed, and the detected voltage Vc is measured when the time t1 has elapsed since the output voltage E was applied to the wire. The non-stick detection threshold voltage Vc1 is determined from the value. The detection voltage Vc at the time t1 is measured only once, and the measured value may be used as a non-stick detection threshold voltage, or a value obtained by adding a predetermined voltage value to the measurement value is a non-stick detection threshold. It may be a voltage. It is also preferable to perform such measurement a plurality of times. In this case, the highest voltage value among the plurality of measurement values may be used as the non-stick detection threshold voltage, and a predetermined voltage value is set as the highest voltage value. The added value may be used as a non-stick detection threshold voltage, or an average value of a plurality of measurement values may be used as a non-stick detection threshold voltage, or a value obtained by adding a predetermined voltage value to the average value. It may be a non-stick detection threshold voltage.

次いで、ソフトウエア制御により前記パラメータ設定項目がボンディングＣＰＵ基板１８のＣＰＵ２９からＩ／Ｏポート３２，３３を通してＤＣパルス方式不着検出基板１０のＣＰＵ３０に通知され、メモリ３４に格納される。すなわち、検出区間・開始位置設定がボンディングＣＰＵ基板１８のＣＰＵ２９からＩ／Ｏポート３２，３３を通してＤＣパルス方式不着検出基板１０のＣＰＵ３０に通知され（ＳＴ１１）、ＤＣパルス方式設定がボンディングＣＰＵ基板１８のＣＰＵ２９からＩ／Ｏポート３２，３３を通してＤＣパルス方式不着検出基板１０のＣＰＵ３０に通知され（ＳＴ１２）、不着検出しきい値電圧設定がボンディングＣＰＵ基板１８のＣＰＵ２９からＩ／Ｏポート３２，３３を通してＤＣパルス方式不着検出基板１０のＣＰＵ３０に通知され（ＳＴ１３）、時間ｔ１設定がボンディングＣＰＵ基板１８のＣＰＵ２９からＩ／Ｏポート３２，３３を通してＤＣパルス方式不着検出基板１０のＣＰＵ３０に通知され（ＳＴ１４）、これらのパラメータ設定項目がメモリ３４に格納される。そして、不着検出しきい値電圧Ｖｃ１についてはメモリ３４からＣＰＵ３０を介して比較回路Ｃに設定される。   Next, the parameter setting items are notified by software control from the CPU 29 of the bonding CPU board 18 to the CPU 30 of the DC pulse system non-sticking detection board 10 through the I / O ports 32 and 33 and stored in the memory 34. That is, the detection section / start position setting is notified from the CPU 29 of the bonding CPU board 18 to the CPU 30 of the DC pulse system non-delivery detection board 10 through the I / O ports 32 and 33 (ST11), and the DC pulse system setting is set to the bonding CPU board 18 The CPU 29 notifies the CPU 30 of the DC pulse system non-stick detection board 10 through the I / O ports 32 and 33 (ST12), and the non-stick detection threshold voltage is set from the CPU 29 of the bonding CPU board 18 through the I / O ports 32 and 33 to the DC. The CPU 30 of the pulse system non-sticking detection board 10 is notified (ST13), and the time t1 setting is notified from the CPU 29 of the bonding CPU board 18 to the CPU 30 of the DC pulse system non-sticking detection board 10 through the I / O ports 32 and 33 (ST14). These parameter settings Items are stored in the memory 34. The non-stick detection threshold voltage Vc1 is set from the memory 34 to the comparison circuit C via the CPU 30.

次いで、１ワイヤボンディングを行う（ＳＴ１５）。具体的には、図２に示すワイヤ（金線）１の先端を溶融してボールを形成し、キャピラリ２の先端で保持してキャピラリ２を第１ボンディング点である半導体チップ１３の電極１２の直上に位置させ、キャピラリ２を下降させてボールを電極１２に押し付けて加圧すると同時にキャピラリ２の先端に対してボンディングアームの超音波ホーンを介して超音波振動を印加する。これにより、電極にワイヤ１を接続する。   Next, one-wire bonding is performed (ST15). Specifically, the tip of the wire (gold wire) 1 shown in FIG. 2 is melted to form a ball and held at the tip of the capillary 2 to hold the capillary 2 of the electrode 12 of the semiconductor chip 13 as the first bonding point. Positioned immediately above, the capillary 2 is lowered and the ball is pressed against the electrode 12 to pressurize it. At the same time, ultrasonic vibration is applied to the tip of the capillary 2 via the ultrasonic horn of the bonding arm. Thereby, the wire 1 is connected to the electrode.

上記のワイヤボンディング時に不着検出を行う（ＳＴ１６〜ＳＴ１９）。以下、不着検出方法について詳細に説明する。
半導体チップ１３の電極１２にＤＣ電圧をステップ状に与えた場合、下記式（１）に示すような関係及び図４に示すような特性がある。ワイヤが電極１２に正常にボンディング接続されると検出電圧は図４に示すような正常着波形４３となるが、ワイヤが電極１２に不着（オープン）であると検出電圧は不着（オープン）波形４２となる。これは、ボンディング対象の電極には静電容量が存在するためである。従って、正常にボンディング接続された場合の不着検出用しきい値電圧Ｖｃ１に達するまでの時間ｔ２は、不着（オープン）である場合の電圧Ｖｃ１に達するまでの時間ｔ１に比べて遅れる。この時間差（ｔ２−ｔ１）は、正常にボンディング接続された場合の静電容量と不着（オープン）である場合の静電容量との差に比例するため、検出対象物の静電容量が極めて小さい場合でも時間差を検出することができ、それにより不着検出が可能となる。
Non-bonding detection is performed during the wire bonding (ST16 to ST19). Hereinafter, the non-stick detection method will be described in detail.
When a DC voltage is applied stepwise to the electrode 12 of the semiconductor chip 13, there is a relationship as shown in the following formula (1) and characteristics as shown in FIG. When the wire is normally bonded to the electrode 12, the detection voltage has a normal arrival waveform 43 as shown in FIG. 4, but when the wire is not attached (open) to the electrode 12, the detection voltage is a non-attachment (open) waveform 42. It becomes. This is because the electrode to be bonded has a capacitance. Therefore, the time t2 until reaching the non-stick detection threshold voltage Vc1 in the case of normal bonding connection is delayed compared to the time t1 until reaching the voltage Vc1 in the non-sticky (open) state. This time difference (t2-t1) is proportional to the difference between the electrostatic capacity when normally bonded and the non-attached (open) electrostatic capacity, so the electrostatic capacity of the detection target is extremely small. Even in this case, it is possible to detect a time difference, thereby enabling non-stick detection.

ｔ＝−Ｒ・Ｃ・Ｌｎ｛１−（Ｖｃ１／Ｅ）｝ ・・・（１）
但し、Ｅは印加電圧（出力電圧）であり、Ｖｃ１は不着検出用しきい値電圧であり、ｔは電圧Ｖｃ１に達するまでの時間であり、Ｃは検出対象物の静電容量である。

 t = −R · C · Ln {1- (Vc1 / E)} (1)
However, E is an applied voltage (output voltage), Vc1 is a non-stick detection threshold voltage, t is a time until it reaches the voltage Vc1 , and C is a capacitance of a detection object.

上述した内容を踏まえて、不着検出方法について具体的に説明する。
まず、ソフトウエア制御によりＣＰＵ３０内部で演算されＤ／Ａコンバータ３６、抵抗４０を介してＤＣパルス信号による出力電圧（図４に示す印加電圧Ｅ）が出力部３８から出力され、このＤＣパルス信号がワイヤ１を通して半導体チップ１３の電極１２に印加される。そして、その印加時からの時間ｔ２を図１に示すタイマー回路Ｔによってカウントする（ＳＴ１６）。これと同時に、増幅器（ＡＭＰ）３７を通して検出電圧Ｖｃを検出する。この検出電圧Ｖｃ１と検出しきい値電圧（不着検出用しきい値電圧Ｖｃ１）を比較回路Ｃによって比較し、検出電圧Ｖｃが検出しきい値電圧Ｖｃ１を超えたか否か（又は検出電圧Ｖｃが検出しきい値電圧Ｖｃ１に達したか否か）を判定回路Ｊによって判定する（ＳＴ１７）。検出電圧Ｖｃが検出しきい値電圧Ｖｃ１を超えていない場合（又は検出電圧Ｖｃが検出しきい値電圧Ｖｃ１に達していない場合）はタイマー回路Ｔによる時間ｔ２のカウントを続行し、検出電圧Ｖｃが検出しきい値電圧Ｖｃ１を超えた場合（又は検出電圧Ｖｃが検出しきい値電圧Ｖｃ１に達した場合）は時間ｔ２のカウントを終了する（ＳＴ１８）。これらの処理はソフトウエア制御により行われる。 Based on the contents described above, the non-stick detection method will be specifically described.
First, an output voltage (applied voltage E shown in FIG. 4) is output from the output unit 38 through the D / A converter 36 and the resistor 40 and is output from the output unit 38 through the D / A converter 36 and the resistor 40 under software control. It is applied to the electrode 12 of the semiconductor chip 13 through the wire 1. Then, the time t2 from the application is counted by the timer circuit T shown in FIG. 1 (ST16). At the same time, the detection voltage Vc is detected through the amplifier (AMP) 37. The detection voltage Vc1 and the detection threshold voltage (non-stick detection threshold voltage Vc1) are compared by the comparison circuit C, and whether or not the detection voltage Vc exceeds the detection threshold voltage Vc1 (or the detection voltage Vc is detected). Whether or not the threshold voltage Vc1 has been reached is determined by the determination circuit J (ST17). When the detection voltage Vc does not exceed the detection threshold voltage Vc1 (or when the detection voltage Vc has not reached the detection threshold voltage Vc1), the timer circuit T continues to count the time t2, and the detection voltage Vc is When the detection threshold voltage Vc1 is exceeded (or when the detection voltage Vc reaches the detection threshold voltage Vc1), the counting of the time t2 is ended (ST18). These processes are performed by software control.

次いで、カウントされた時間ｔ２と予め決められている時間ｔ１を比較回路Ｃによって比較する。時間ｔ２が時間ｔ１を超える場合は正常着（ボンディング接続されたこと）と判定回路Ｊによって判断し、時間ｔ２が時間ｔ１を超えていない場合は不着（オープン）と判定回路Ｊによって判断する（ＳＴ１９）。この着／不着の結果は、Ｉ／Ｏポートを介してボンディングＣＰＵ基板１８のＣＰＵ２９に通知される。ワイヤが不着であると通知された場合、ワイヤボンディング装置を停止するなどのエラー処理が行われる。また、ワイヤが正常着（確実にボンディングされた）と通知された場合、次のワイヤボンディングを行う。   Next, the counted time t2 is compared with the predetermined time t1 by the comparison circuit C. When the time t2 exceeds the time t1, the determination circuit J determines that it is normally attached (bonded connection), and when the time t2 does not exceed the time t1, the determination circuit J determines that it is non-attached (open) (ST19). ). The result of the attachment / non-attachment is notified to the CPU 29 of the bonding CPU board 18 through the I / O port. When notified that the wire is not attached, error processing such as stopping the wire bonding apparatus is performed. Further, when it is notified that the wire is normally attached (bonded surely), the next wire bonding is performed.

尚、本実施の形態では、時間ｔ２のカウント開始（ＳＴ１６）、検出電圧が検出しきい値電圧を超えたか否か（又は検出電圧が検出しきい値電圧に達したか否か）の判定（ＳＴ１７）、時間ｔ２のカウント終了（ＳＴ１８）のステップを１回のみ、すなわちＤＣパルス信号をワイヤに印加し、その印加時からの時間ｔ２のカウントを１回のみ行っているが、１ワイヤボンディングにおいてＤＣパルス信号をワイヤに複数回印加し、時間ｔ２のカウントを複数回行うことも可能である。この場合は、複数の時間ｔ２のうち最も短い時間ｔ２を時間ｔ１と比較しても良いし、最も短い時間ｔ２から所定の時間を差引いた時間を時間ｔ１と比較しても良いし、また複数の時間ｔ２の平均時間を時間ｔ１と比較しても良いし、前記平均時間に所定の時間を差引いた時間を時間ｔ１と比較しても良い。   In the present embodiment, the start of counting at time t2 (ST16), whether or not the detection voltage exceeds the detection threshold voltage (or whether or not the detection voltage has reached the detection threshold voltage) ( ST17) The time t2 count end (ST18) step is performed only once, that is, the DC pulse signal is applied to the wire, and the time t2 from the application is counted only once. It is also possible to apply the DC pulse signal to the wire a plurality of times and count the time t2 a plurality of times. In this case, the shortest time t2 among the plurality of times t2 may be compared with the time t1, or a time obtained by subtracting a predetermined time from the shortest time t2 may be compared with the time t1. The average time of the time t2 may be compared with the time t1, or the time obtained by subtracting a predetermined time from the average time may be compared with the time t1.

ワイヤが確実にボンディングされたと判断した場合、次のワイヤボンディングについてパラメータ設定項目の設定をソフトウエア制御により行い（ＳＴ１１〜ＳＴ１４）、ワイヤボンディングを行い（ＳＴ１５）、ワイヤボンディング時に不着検出を行う（ＳＴ１６〜ＳＴ１９）。所定のワイヤ数まで繰り返し、すべてのワイヤボンディングが行われたらワイヤボンディング作業を終了する（ＳＴ２０）。   If it is determined that the wire has been securely bonded, parameter setting items for the next wire bonding are set by software control (ST11 to ST14), wire bonding is performed (ST15), and non-sticking detection is performed during wire bonding (ST16). -ST19). The process is repeated up to a predetermined number of wires, and when all wire bonding is performed, the wire bonding operation is finished (ST20).

上述したワイヤボンディング及び不着検出は、図５に示す第１ボンディング点１５である半導体チップの電極へのワイヤボンディングについて説明しているが、図５に示す第２ボンディング点１６であるリードへのワイヤボンディングについても上述した不着検出方法とほぼ同様に不着検出することが可能であり、またワイヤ１の先端を溶融してボールを形成し、このボールを半導体チップの電極又はパッドにバンプとして接続する場合についても上述した不着検出方法とほぼ同様に不着検出することが可能である。   In the above-described wire bonding and non-bonding detection, the wire bonding to the electrode of the semiconductor chip, which is the first bonding point 15 shown in FIG. 5, has been described, but the wire to the lead, which is the second bonding point 16 shown in FIG. Bonding can be detected in substantially the same manner as the above-described non-stick detection method, and the tip of the wire 1 is melted to form a ball and the ball is connected to an electrode or pad of a semiconductor chip as a bump. The non-stick detection can be performed in substantially the same manner as the non-stick detection method described above.

上記実施の形態によれば、正常にボンディング接続された場合の不着検出用しきい値電圧Ｖｃ１に達するまでの時間ｔ２が、不着（オープン）である場合の電圧Ｖｃ１に達するまでの時間ｔ１に比べて遅れることを利用する。これにより、検出対象物の静電容量が極めて小さい場合でも時間差（ｔ２−ｔ１）を検出することができ、それにより不着検出が可能となる。よって、従来の不着検出装置では不着検出できないような極めて低い静電容量しか有さない検出対象物についても不着検出が可能となる。   According to the above embodiment, the time t2 until reaching the non-stick detection threshold voltage Vc1 in the case of normal bonding connection is compared with the time t1 until reaching the voltage Vc1 in the non-sticky (open) state. Take advantage of being late. Thereby, even when the capacitance of the detection target is extremely small, the time difference (t2−t1) can be detected, and thereby non-stick detection can be performed. Therefore, non-stick detection can be performed even for a detection target having a very low capacitance that cannot be detected by a conventional non-stick detection device.

尚、本発明は上記実施の形態に限定されず、本発明の主旨を逸脱しない範囲内で種々変更して実施することが可能である。例えば、本実施の形態では、検出区間・開始位置などのパラメータ設定項目をワイヤ毎に設定しているが、全てのワイヤについてパラメータ設定項目を統一的に設定して本発明を実施することも可能である。   Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, in this embodiment, the parameter setting items such as the detection section and the start position are set for each wire. However, the present invention can also be implemented by setting the parameter setting items uniformly for all wires. It is.

本発明の実施の形態による不着検出装置を模式的に示すブロック図である。It is a block diagram which shows typically the non-sticking detection apparatus by embodiment of this invention. 図１に示す不着検出基板とワイヤボンディング装置との配線による接続関係を概略的に示す図である。It is a figure which shows roughly the connection relationship by the wiring of the non-sticking detection board | substrate shown in FIG. 1, and a wire bonding apparatus. 図１に示す不着検出装置によって不着検出を行う流れを示すフローチャートである。It is a flowchart which shows the flow which performs non-sticking detection by the non-sticking detection apparatus shown in FIG. 図１に示す不着検出装置によって不着検出を行う際、出力電圧Ｅをワイヤに印加してから時間ｔの経過による検出電圧Ｖｃの変化を示す図である。When non-stick detection is performed by the non-stick detection device shown in FIG. 1, it is a diagram showing a change in the detection voltage Vc over time after the output voltage E is applied to the wire. （ａ）乃至（ｄ）は、ワイヤボンディング装置によるワイヤボンディングを行う工程を説明する図である。(A) thru | or (d) is a figure explaining the process of performing the wire bonding by a wire bonding apparatus. 従来の不着検出方法を示すフローチャートである。It is a flowchart which shows the conventional non-sticking detection method. 従来のワイヤボンディング装置のＤＣ専用不着検出装置を示すブロック図である。It is a block diagram which shows the non-sticking detection apparatus only for DC of the conventional wire bonding apparatus. 従来のワイヤボンディング装置のＡＣ専用不着検出装置の具体的な構成を示す回路図である。It is a circuit diagram which shows the specific structure of the non-sticking detection apparatus only for AC of the conventional wire bonding apparatus.

符号の説明Explanation of symbols

１…ワイヤ、２…キャピラリ、３…ワイヤカットクランプ、４…放電電極、５…交流ブリッジ回路、５ａ…交流発生器、５ｂ…同軸ケーブル、５ｃ１…第１直列回路、５ｃ２…第２直列回路、Ｘ…第１接続点、Ｙ…第２接続点、６…差動増幅器、７…トランス、８…絶対値変換器、９…第１レベル弁別器、１０…ＤＣパルス方式不着検出基板、１１…リードフレーム、１２…半導体チップの電極、１３…半導体チップ、１４…リード、１５…第１ボンディング点、１６…第２ボンディング点、１７…ボンディングステージ、１８…ボンディングＣＰＵ基板、１９…メインＣＰＵ基板、２０…ボール、２１…ワイヤスプール、２２…スプールワイヤ端、２３…ローパスフィルタ、２４…第２レベル弁別器、２５…論理積器、２６…ボンディング判定器、２７…ボンディング検出切替器、２８，２９，３０…ＣＰＵ、３１…キーボード、３２，３３…Ｉ／Ｏポート、３４…メモリ、３５…Ａ／Ｄコンバータ、３６…Ｄ／Ａコンバータ、３７…増幅器（ＡＭＰ）、３８…出力部、３９…接地電位（ＧＮＤ）、４０…抵抗、４１…回路群、Ｃ…比較回路、Ｔ…タイマー回路、Ｊ…判定回路、４２…不着（オープン）波形、４３…正常着波形、４４…ＤＣ用不着検出基板、４５…直流発生器、４６…抵抗 DESCRIPTION OF SYMBOLS 1 ... Wire, 2 ... Capillary, 3 ... Wire cut clamp, 4 ... Discharge electrode, 5 ... AC bridge circuit, 5a ... AC generator, 5b ... Coaxial cable, 5c1 ... 1st series circuit, 5c2 ... 2nd series circuit, X ... 1st connection point, Y ... 2nd connection point, 6 ... Differential amplifier, 7 ... Transformer, 8 ... Absolute value converter, 9 ... 1st level discriminator, 10 ... DC pulse system non-sticking detection board, 11 ... Lead frame, 12 ... Semiconductor chip electrode, 13 ... Semiconductor chip, 14 ... Lead, 15 ... First bonding point, 16 ... Second bonding point, 17 ... Bonding stage, 18 ... Bonding CPU board, 19 ... Main CPU board, 20 ... ball, 21 ... wire spool, 22 ... spool wire end, 23 ... low pass filter, 24 ... second level discriminator, 25 ... logical product, 26 ... bonding 27, bonding detection switching device, 28, 29, 30 ... CPU, 31 ... keyboard, 32, 33 ... I / O port, 34 ... memory, 35 ... A / D converter, 36 ... D / A converter, 37 ... Amplifier (AMP), 38 ... Output unit, 39 ... Ground potential (GND), 40 ... Resistance, 41 ... Circuit group, C ... Comparison circuit, T ... Timer circuit, J ... Determination circuit, 42 ... Non-attached (open) waveform , 43 ... Normal arrival waveform, 44 ... DC non-adherence detection board, 45 ... DC generator, 46 ... Resistance

Claims (5)

半導体チップの電極とリードフレームのリードをワイヤによって接続するワイヤボンディング装置又は半導体チップのパッドにバンプをボンディングするワイヤボンディング装置において、
ＤＣ電圧をワイヤ又はバンプに印加するＤＣ印加手段と、
前記ワイヤ又はバンプからの検出電圧を検出する電圧検出手段と、
前記ＤＣ電圧を印加した時から前記検出電圧が検出しきい値電圧に達した時又は超えた時までの第１時間を検出する時間検出手段と、
前記第１時間と、ボンディングが不着のワイヤ又はバンプに前記ＤＣ電圧を印加した時から前記検出しきい値電圧に達するまで又は超えるまでの第２時間とを比較することにより、ワイヤ又はバンプが正常にボンディング接続されたか否かを判定する判定手段と、
を具備することを特徴とするワイヤボンディング装置。 In a wire bonding apparatus that connects electrodes of a semiconductor chip and leads of a lead frame by wires or a wire bonding apparatus that bonds bumps to pads of a semiconductor chip,
DC application means for applying a DC voltage to the wire or bump;
Voltage detection means for detecting a detection voltage from the wire or bump;
Time detection means for detecting a first time from when the DC voltage is applied to when the detection voltage reaches or exceeds a detection threshold voltage;
The wire or bump is normal by comparing the first time with the second time from when the DC voltage is applied to the wire or bump to which bonding is not applied until the detection threshold voltage is reached or exceeded. Determining means for determining whether or not a bonding connection has been made;
A wire bonding apparatus comprising: 前記ＤＣ印加手段は、ＤＣパルス信号をワイヤ又はバンプに印加する手段である請求項１に記載のワイヤボンディング装置。 The wire bonding apparatus according to claim 1, wherein the DC applying unit is a unit that applies a DC pulse signal to a wire or a bump. 前記判定手段は、前記第１時間が前記第２時間より長ければワイヤ又はバンプが正常にボンディング接続されたと判定し、前記第１時間が前記第２時間に比べて長くなければワイヤ又はバンプが不着であると判定する手段であることを特徴とする請求項１又は２に記載のワイヤボンディング装置。 The determination unit determines that the wire or bump is normally bonded when the first time is longer than the second time, and the wire or bump is not attached when the first time is not longer than the second time. The wire bonding apparatus according to claim 1, wherein the wire bonding apparatus is a means for determining that 前記ＤＣ印加手段はＣＰＵ、Ｄ／Ａコンバータ及び抵抗を有し、
前記電圧検出手段は増幅器及びＣＰＵを有し、
前記時間検出手段は、前記ＤＣ電圧を印加した時からの時間をカウントするタイマー回路、前記検出電圧と前記検出しきい値電圧を比較する比較回路、及び、前記検出電圧が前記検出しきい値電圧を超えたか否かを判定する判定回路を有し、
前記判定手段は、前記第１時間と前記第２時間を比較する比較回路、前記第１時間が前記第２時間より長いか短いかを判定する判定回路、及びＣＰＵを有していることを特徴とする請求項１乃至３のいずれか一項に記載のワイヤボンディング装置。 The DC applying means has a CPU, a D / A converter and a resistor,
The voltage detection means includes an amplifier and a CPU,
The time detection means includes a timer circuit that counts time from when the DC voltage is applied, a comparison circuit that compares the detection voltage with the detection threshold voltage, and the detection voltage is the detection threshold voltage. Having a determination circuit for determining whether or not
The determination unit includes a comparison circuit that compares the first time with the second time, a determination circuit that determines whether the first time is longer or shorter than the second time, and a CPU. The wire bonding apparatus according to any one of claims 1 to 3. 前記検出しきい値電圧及び前記第２時間を予め設定しておき、前記ＤＣ印加手段によりＤＣ電圧をワイヤ又はバンプに印加し、前記電圧検出手段によりワイヤ又はバンプからの検出電圧を検出し、前記時間検出手段により前記第１時間を検出し、前記判定手段により前記第１時間と前記第２時間とを比較してワイヤ又はバンプが正常にボンディング接続されたか否かを判定することをソフトウエア制御により行う請求項１乃至４のいずれか一項に記載のワイヤボンディング装置。 The detection threshold voltage and the second time are set in advance, a DC voltage is applied to the wire or the bump by the DC application unit, a detection voltage from the wire or the bump is detected by the voltage detection unit, Software control to detect the first time by a time detection means and to determine whether the wire or bump is normally bonded by comparing the first time and the second time by the determination means The wire bonding apparatus as described in any one of Claims 1 thru | or 4 performed by.
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