JPH0964096A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0964096A JPH0964096A JP7218477A JP21847795A JPH0964096A JP H0964096 A JPH0964096 A JP H0964096A JP 7218477 A JP7218477 A JP 7218477A JP 21847795 A JP21847795 A JP 21847795A JP H0964096 A JPH0964096 A JP H0964096A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- base substrate
- semiconductor pellet
- semiconductor
- pellet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/71—Means for bonding not being attached to, or not being formed on, the surface to be connected
- H01L2224/72—Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置に関し、特
に、ベース基板の電極と半導体ペレットの電極とをバン
プ電極を介在して電気的に接続する半導体装置に適用し
て有効な技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique effectively applied to a semiconductor device in which an electrode of a base substrate and an electrode of a semiconductor pellet are electrically connected via a bump electrode. Is.
【０００２】[0002]
【従来の技術】ベース基板の主面のペレット塔載領域上
にフェースダウン方式で半導体ペレットを塔載する半導
体装置は、ベース基板の主面のペレット塔載領域に配置
された電極と半導体ペレットの主面に配置された電極と
をＰｂ−Ｓｎ系の合金材からなるバンプ電極を介在して
電気的に接続している。この種の半導体装置のバンプ電
極は、その一端側が下地金属膜(ＢＬＭ：Ｂall Ｌimiti
ng Ｍetallization)を介在してベース基板の電極に固着
固定され、その他端側が下地金属膜を介在して半導体ペ
レットの電極に固着固定される。下地金属膜は、バンプ
電極との濡れ性を高める目的としてベース基板の電極上
並びに半導体ペレットの電極上に配置される。2. Description of the Related Art A semiconductor device in which semiconductor pellets are mounted on a pellet mounting area on the main surface of a base substrate by a face-down method is known as a method of mounting electrodes and semiconductor pellets on the pellet mounting area on the main surface of a base substrate. The electrodes arranged on the main surface are electrically connected via bump electrodes made of a Pb-Sn alloy material. Bump electrodes of this type of semiconductor device has its one end underlying metal film (BLM: B all L imiti
ng M etallization) and is fixed and fixed to the electrode of the base substrate, and the other end side is fixed and fixed to the electrode of the semiconductor pellet through the underlying metal film. The base metal film is arranged on the electrode of the base substrate and the electrode of the semiconductor pellet for the purpose of improving the wettability with the bump electrode.
【０００３】なお、ベース基板の主面のペレット塔載領
域上にフェースダウン方式で半導体ペレットを塔載する
半導体装置については、例えば特開昭６２−２４９４２
９号公報並びに特開昭６３−３１０１３９号公報に記載
されている。A semiconductor device in which semiconductor pellets are mounted face down on the pellet mounting region on the main surface of the base substrate is disclosed in, for example, Japanese Patent Laid-Open No. 62-24942.
No. 9 and JP-A No. 63-310139.
【０００４】[0004]
【発明が解決しようとする課題】前記半導体装置におい
て、バンプ電極は、その一端側が下地金属膜を介在して
ベース基板の電極に固着固定され、その他端側が下地金
属膜を介在して半導体ペレットの電極に固着固定されて
いる。このため、製品完成後の環境試験である温度サイ
クル時や実装基板に半導体装置を実装する実装時の熱処
理工程において、ベース基板、半導体ペレットの夫々の
熱膨張係数の差に起因する熱応力がバンプ電極に集中
し、バンプ電極が破損するいとう問題があった。このバ
ンプ電極の破損は、熱に対する半導体装置の信頼性を著
しく低下させる。In the semiconductor device described above, one end of the bump electrode is fixedly fixed to the electrode of the base substrate with the underlying metal film interposed, and the other end of the bump electrode of the semiconductor pellet is interposed with the underlying metal film interposed. It is firmly fixed to the electrode. Therefore, in the heat treatment process during the temperature cycle, which is an environmental test after the product is completed, or when mounting the semiconductor device on the mounting substrate, the thermal stress caused by the difference in thermal expansion coefficient between the base substrate and the semiconductor pellet is There was a problem that the bump electrodes would be damaged by concentrating on the electrodes. The damage of the bump electrode significantly reduces the reliability of the semiconductor device against heat.
【０００５】また、前述の問題を解決するために、ベー
ス基板を半導体ペレットの熱膨張係数(例えばＳｉ基板
の熱膨張係数)に近い材料からなるセラミックス基板で
形成し、熱膨張係数の差に起因する熱応力の発生を低減
している。具体的には、ベース基板は、ムライト、窒化
アルミニウム等からなるセラミックス基板で形成され
る。しかしながら、セラミックス基板で形成されるベー
ス基板は樹脂基板で形成されるベース基板に比べて部品
コストが高いので、半導体装置の製造コストが増加す
る。In order to solve the above-mentioned problems, the base substrate is formed of a ceramic substrate made of a material close to the thermal expansion coefficient of the semiconductor pellet (for example, the thermal expansion coefficient of the Si substrate), and the difference in the thermal expansion coefficient is caused. The occurrence of thermal stress is reduced. Specifically, the base substrate is formed of a ceramic substrate made of mullite, aluminum nitride or the like. However, since the base substrate formed of a ceramic substrate has a higher component cost than the base substrate formed of a resin substrate, the manufacturing cost of the semiconductor device increases.
【０００６】本発明の目的は、ベース基板の電極と半導
体ペレットの電極とを電気的に接続するバンプ電極の破
損を防止し、熱に対する半導体装置の信頼性を高めるこ
とが可能な技術を提供することにある。An object of the present invention is to provide a technique capable of preventing a bump electrode for electrically connecting an electrode of a base substrate and an electrode of a semiconductor pellet from being damaged and improving reliability of a semiconductor device against heat. Especially.
【０００７】また、本発明の他方の目的は、前記目的を
達成し、半導体装置の製造コストを低減することが可能
な技術を提供することにある。Another object of the present invention is to provide a technique capable of achieving the above object and reducing the manufacturing cost of a semiconductor device.
【０００８】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面によって明らか
になるであろう。The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
【０００９】[0009]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
下記のとおりである。SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.
【００１０】ベース基板の電極と半導体ペレットの電極
とをバンプ電極を介在して電気的に接続する半導体装置
において、前記ベース基板の電極又は前記半導体ペレッ
トの電極と前記バンプ電極の一端側とを固着固定し、前
記ベース基板に向って前記半導体ペレットを押圧する押
圧部材の押圧力で前記半導体ペレットの電極又は前記ベ
ース基板の電極と前記バンプ電極の他端側とを押圧固定
する。In a semiconductor device in which an electrode on a base substrate and an electrode on a semiconductor pellet are electrically connected via a bump electrode, the electrode on the base substrate or the electrode on the semiconductor pellet and one end of the bump electrode are fixed to each other. Then, the electrode of the semiconductor pellet or the electrode of the base substrate and the other end of the bump electrode are pressed and fixed by the pressing force of the pressing member that presses the semiconductor pellet toward the base substrate.
【００１１】[0011]
【作用】上述した手段によれば、ベース基板の電極、半
導体ペレットの電極のうち、どちらか一方の電極がバン
プ電極に対して固着固定されていないので、ベース基板
の電極と半導体ペレットの電極との位置関係を平面方向
にずらすことができる。この結果、製品完成後の環境試
験である温度サイクル時や実装基板に半導体装置を実装
する実装時の熱処理工程において、ベース基板、半導体
ペレットの夫々の熱膨張係数の差に起因する熱応力をベ
ース基板の電極と半導体ペレットの電極との位置ずれで
緩和することができるので、ベース基板の電極と半導体
ペレットの電極とを電気的に接続するバンプ電極の破損
を防止し、熱に対する半導体装置の信頼性を高めること
ができる。According to the above-mentioned means, one of the electrodes of the base substrate and the electrode of the semiconductor pellet is not fixedly fixed to the bump electrode, so that the electrode of the base substrate and the electrode of the semiconductor pellet are not fixed. The positional relationship of can be shifted in the plane direction. As a result, the thermal stress caused by the difference in the thermal expansion coefficient between the base substrate and the semiconductor pellet is eliminated during the heat treatment process during the temperature cycle, which is an environmental test after the product is completed, and when the semiconductor device is mounted on the mounting substrate. Since it can be mitigated by the positional deviation between the electrode of the substrate and the electrode of the semiconductor pellet, the bump electrode that electrically connects the electrode of the base substrate and the electrode of the semiconductor pellet can be prevented from being damaged, and the reliability of the semiconductor device against heat can be reduced. You can improve your sex.
【００１２】また、ベース基板、半導体ペレットの夫々
の熱膨張係数の差に起因する熱応力をベース基板の電極
と半導体ペレットの電極との位置ずれで緩和することが
できるので、ベース基板を半導体ペレットの熱膨張係数
に近い材料からなるセラミックス基板で形成する必要が
なく、セラミックス基板に比べて部品コストの低い樹脂
基板でベース基板を形成することができる。この結果、
ベース基板の部品コストに相当する分、半導体装置の製
造コストを低減することができる。Further, since the thermal stress caused by the difference in thermal expansion coefficient between the base substrate and the semiconductor pellet can be relieved by the positional deviation between the electrode of the base substrate and the electrode of the semiconductor pellet, the base substrate can be used as the semiconductor pellet. It is not necessary to form the base substrate using a ceramic substrate made of a material having a coefficient of thermal expansion close to that of 1., and the base substrate can be formed using a resin substrate having a lower component cost than the ceramic substrate. As a result,
The manufacturing cost of the semiconductor device can be reduced by an amount corresponding to the component cost of the base substrate.
【００１３】また、ベース基板の電極、半導体ペレット
の電極のうち、どちらか一方の電極がバンプ電極に対し
て押圧固定されているので、ベース基板と半導体ペレッ
トとの熱膨張係数の整合性を問わずにベース基板の電極
と半導体ペレットの電極とをバンプ電極で電気的に接続
することができる。Further, since either one of the electrode of the base substrate and the electrode of the semiconductor pellet is pressed and fixed to the bump electrode, the matching of the thermal expansion coefficients of the base substrate and the semiconductor pellet is questioned. Instead, the electrode of the base substrate and the electrode of the semiconductor pellet can be electrically connected by the bump electrode.
【００１４】また、ベース基板の電極、半導体ペレット
の電極のうち、どちらか一方の電極がバンプ電極に対し
て押圧固定されているので、ベース基板の電極、半導体
ペレットの電極のうち、どちらか一方の電極とバンプ電
極との間に介在される下地金属膜を廃止することができ
る。この結果、下地金属膜の廃止に相当する分、半導体
装置の製造コストを低減することができる。Since either one of the electrode of the base substrate and the electrode of the semiconductor pellet is pressed and fixed to the bump electrode, either one of the electrode of the base substrate and the electrode of the semiconductor pellet is pressed. The underlying metal film interposed between the electrode and the bump electrode can be eliminated. As a result, the manufacturing cost of the semiconductor device can be reduced by the amount corresponding to the elimination of the underlying metal film.
【００１５】[0015]
【実施例】以下、本発明の構成について、半導体装置に
本発明を適用した実施例とともに説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the present invention will be described below together with embodiments in which the present invention is applied to a semiconductor device.
【００１６】なお、実施例を説明するための全図におい
て、同一機能を有するものは同一符号を付け、その繰り
返しの説明は省略する。In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and their repeated description will be omitted.
【００１７】（実 施 例 １）図１は本発明の実施例１
である半導体装置の断面図である。(Embodiment 1) FIG. 1 shows Embodiment 1 of the present invention.
FIG. 3 is a cross-sectional view of the semiconductor device of FIG.
【００１８】図１に示すように、本実施例の半導体装置
は、ベース基板１の主面のペレット塔載領域上にフェー
スダウン方式で半導体ペレット３を塔載し、この半導体
ペレット３をベース基板１及び保護キャップ５で形成さ
れるキャビティ内に気密封止した構造で構成される。As shown in FIG. 1, in the semiconductor device of this embodiment, semiconductor pellets 3 are mounted on a pellet mounting area on the main surface of the base substrate 1 by a face-down method, and the semiconductor pellets 3 are mounted on the base substrate. 1 and the protective cap 5 are hermetically sealed in the cavity.
【００１９】前記ベース基板１は、詳細に図示していな
いが、例えば多層配線構造で構成される。この多層配線
構造のベース基板は、例えばガラス繊維にエポキシ樹
脂、ポリイミド樹脂等を含浸させた樹脂基板で形成され
る。樹脂基板は、ムライト、窒化アルミニウム等からな
るセラミックス基板に比べて熱膨張係数が大きい。例え
ば、樹脂基板は１０〜１５×１０~6［Ｋ~1］程度の熱膨
張係数を有し、セラミックス基板は３〜４×１０~6［Ｋ
~1］程度の熱膨張係数を有する。Although not shown in detail, the base substrate 1 has a multilayer wiring structure, for example. The base substrate having this multilayer wiring structure is formed of, for example, a resin substrate obtained by impregnating glass fiber with epoxy resin, polyimide resin, or the like. The resin substrate has a larger coefficient of thermal expansion than a ceramic substrate made of mullite, aluminum nitride or the like. For example, a resin substrate has a thermal expansion coefficient of about 10 to 15 × 10 6 [K- 1 ], and a ceramic substrate has a thermal expansion coefficient of 3 to 4 × 10 6 [K].
~ 1 ] thermal expansion coefficient.
【００２０】前記ベース基板１の主面のペレット塔載領
域には複数の電極１Ａが行列状に配置され、その主面と
対向する裏面には複数の電極１Ｂが行列状に配置され
る。この電極１Ａ、電極１Ｂの夫々は、多層配線構造の
配線を介して電気的に接続される。電極１Ａ、電極１
Ｂ、配線の夫々は例えばＷ膜で形成される。A plurality of electrodes 1A are arranged in a matrix in the pellet mounting region on the main surface of the base substrate 1, and a plurality of electrodes 1B are arranged in a matrix on the back surface facing the main surface. The electrodes 1A and 1B are electrically connected to each other through wirings having a multilayer wiring structure. Electrode 1A, electrode 1
Each of B and wiring is formed of, for example, a W film.
【００２１】前記半導体ペレット３は、例えば単結晶珪
素からなるＳｉ基板３Ａ及びこのＳｉ基板３Ａ上に形成
された配線層３Ｂを主体に構成される。Ｓｉ基板３Ａの
主面側(素子形成面側)には、論理回路システム、記憶回
路システム、或はそれらの混合回路システムが塔載され
る。また、Ｓｉ基板３Ａの主面上には複数の電極３Ｃが
行列状に配置される。複数の電極３Ｃの夫々は、配線層
３Ｂのうち、最上層の配線層に形成され、例えばＡｌ膜
又はＡｌ合金膜で形成される。なお、Ｓｉ基板３Ａは３
×１０~6［Ｋ~1］程度の熱膨張係数を有する。The semiconductor pellet 3 is mainly composed of a Si substrate 3A made of, for example, single crystal silicon and a wiring layer 3B formed on the Si substrate 3A. A logic circuit system, a memory circuit system, or a mixed circuit system thereof is mounted on the main surface side (element formation surface side) of the Si substrate 3A. Further, a plurality of electrodes 3C are arranged in a matrix on the main surface of the Si substrate 3A. Each of the plurality of electrodes 3C is formed in the uppermost wiring layer of the wiring layer 3B and is formed of, for example, an Al film or an Al alloy film. In addition, the Si substrate 3A is 3
It has a coefficient of thermal expansion of about × 10 to 6 [K to 1 ].
【００２２】前記保護キャップ５は、断面形状がコの字
形状で形成され、例えば窒化アルミニウムで形成され
る。保護キャップ５はベース基板１の主面の周辺領域に
ろう材６で固着固定される。ろう材６は例えばＰｂ−Ｓ
ｎ系の合金材で形成される。The protective cap 5 has a U-shaped cross section, and is made of, for example, aluminum nitride. The protective cap 5 is fixed and fixed to the peripheral region of the main surface of the base substrate 1 with a brazing material 6. The brazing material 6 is, for example, Pb-S.
It is made of an n-based alloy material.
【００２３】前記ベース基板１の電極１Ａと半導体ペレ
ット３の電極３Ｃとは、例えばＳｎ−Ａｇ系の合金材か
らなるバンプ電極４で電気的に接続されている。バンプ
電極４は、その一端側が下地金属膜(ＢＬＭ：Ｂall Ｌi
miting Ｍetallization)２を介在してベース基板１の電
極１Ａに固着固定され、その他端側が半導体ペレット３
の電極３Ｃに押圧固定される。下地金属膜２は、バンプ
電極４との濡れ性を高める目的としてベース基板１の電
極１Ａ上に配置される。下地金属膜２は、これに限定さ
れないが、例えばベース基板１の電極１Ａの表面側から
Ａｕ膜、Ｎｉ膜の夫々を順次積層した積層膜で形成され
る。なお、半導体ペレット３の電極３Ｃとバンプ電極４
との間に介在される下地金属膜は廃止されている。The electrode 1A of the base substrate 1 and the electrode 3C of the semiconductor pellet 3 are electrically connected by a bump electrode 4 made of, for example, a Sn--Ag alloy material. Bump electrode 4, one end side of the base metal film (BLM: B all L i
miting M etallization) 2 by interposing fixed secured to the electrode 1A of the base substrate 1, the other end is the semiconductor pellet 3
The electrode 3C is pressed and fixed. The base metal film 2 is arranged on the electrode 1A of the base substrate 1 for the purpose of improving the wettability with the bump electrode 4. Although not limited to this, the base metal film 2 is formed of, for example, a laminated film in which an Au film and a Ni film are sequentially laminated from the surface side of the electrode 1A of the base substrate 1. The electrode 3C of the semiconductor pellet 3 and the bump electrode 4
The underlying metal film interposed between and is abolished.
【００２４】前記バンプ電極４は、ベース基板１の電極
１Ａ上の下地金属膜２の表面上にリフトオフ法でＳｎ−
Ａｇ合金膜を形成することにより形成される。バンプ電
極４は、熱処理によってその形状を球形状に成形する工
程、所謂ウエットバック処理が施されていない。即ち、
バンプ電極１４の形状は、円錐台形状で形成され、その
縦方向の断面形状は台状に形成される。このように構成
されるバンプ電極４はウエットバック処理が施されてい
ないので、ウエットバック処理が施された球形状のバン
プ電極並びに下地金属膜２の表面上にボール供給法で供
給された球形状のバンプ電極に比べて各バンプ電極４の
高さを均一にすることができる。The bump electrode 4 is Sn-formed by a lift-off method on the surface of the base metal film 2 on the electrode 1A of the base substrate 1.
It is formed by forming an Ag alloy film. The bump electrode 4 is not subjected to a so-called wet-back process of forming the bump electrode 4 into a spherical shape by heat treatment. That is,
The bump electrode 14 is formed in a truncated cone shape, and its vertical cross-sectional shape is formed in a trapezoidal shape. Since the bump electrode 4 configured in this manner is not subjected to wet back processing, the spherical bump electrode subjected to wet back processing and the spherical shape supplied on the surface of the underlying metal film 2 by the ball supply method. It is possible to make the height of each bump electrode 4 more uniform than that of the bump electrode.
【００２５】前記バンプ電極４の他端側と半導体ペレッ
ト３の電極３Ｃとの押圧固定は、ベース基板１に向って
半導体ペレット３を押圧する押圧部材７の押圧力で行な
われる。本実施例の押圧部材７は、弾性力を有するコイ
ル形状のバネ部材で形成され、ベース基板１に固定され
た保護キャップ５と半導体ペレット３との間に配置され
る。本実施例において、半導体ペレット３の主面に配置
される複数の電極３Ｃは行列状に配置されているので、
各電極３Ｃと各バンプ電極４との押圧固定を均一にする
ため、押圧部材７は例えば半導体ペレット３の４つの隅
及びその中央部に計５つ配置される。The other end of the bump electrode 4 and the electrode 3C of the semiconductor pellet 3 are pressed and fixed by the pressing force of the pressing member 7 that presses the semiconductor pellet 3 toward the base substrate 1. The pressing member 7 of this embodiment is formed of a coil-shaped spring member having elastic force, and is arranged between the protective cap 5 fixed to the base substrate 1 and the semiconductor pellet 3. In this embodiment, since the plurality of electrodes 3C arranged on the main surface of the semiconductor pellet 3 are arranged in a matrix,
In order to uniformly press and fix the electrodes 3C and the bump electrodes 4, a total of five pressing members 7 are arranged at four corners of the semiconductor pellet 3 and in the center thereof.
【００２６】前記ベース基板１の電極１Ｂ上には、下地
金属膜(図示せず)を介在して例えばボール供給法で供給
された球形状のバンプ電極８が配置される。バンプ電極
８は、例えばＰｂ−Ｓｎ系の合金材で形成される。On the electrode 1B of the base substrate 1, a spherical bump electrode 8 supplied by, for example, a ball supplying method with a base metal film (not shown) interposed is arranged. The bump electrode 8 is formed of, for example, a Pb—Sn based alloy material.
【００２７】以上の説明からかわかるように、本実施例
によれば以下の効果が得られる。As can be seen from the above description, according to this embodiment, the following effects can be obtained.
【００２８】（１）ベース基板１の電極１Ａと半導体ペ
レット３の電極１Ｃとをバンプ電極４を介在して電気的
に接続する半導体装置において、前記ベース基板１の電
極１Ａと前記バンプ電極４の一端側とを固着固定し、前
記ベース基板１に向って前記半導体ペレット３を押圧す
る押圧部材７の押圧力で前記半導体ペレット３の電極３
Ｃと前記バンプ電極４の他端側とを押圧固定する。この
構成により、ベース基板１の電極１Ａ、半導体ペレット
３の電極３Ｃのうち、半導体ペレット３の電極３Ｃがバ
ンプ電極４に対して固着固定されていないので、ベース
基板１の電極１Ｃと半導体ペレット３の電極３Ｃとの位
置関係を平面方向にずらすことができる。この結果、製
品完成後の環境試験である温度サイクル時や実装基板に
半導体装置を実装する実装時の熱処理工程において、ベ
ース基板１、半導体ペレット３の夫々の熱膨張係数の差
に起因する熱応力をベース基板１の電極１Ａと半導体ペ
レット３の電極３Ｃとの位置ずれで緩和することができ
るので、ベース基板１の電極１Ａと半導体ペレット３の
電極３Ｃとを電気的に接続するバンプ電極４の破損を防
止し、熱に対する半導体装置の信頼性を高めることがで
きる。(1) In the semiconductor device in which the electrode 1A of the base substrate 1 and the electrode 1C of the semiconductor pellet 3 are electrically connected via the bump electrode 4, the electrode 1A of the base substrate 1 and the bump electrode 4 are connected. The electrode 3 of the semiconductor pellet 3 is fixed by a pressing force of a pressing member 7 that is fixedly fixed to one end side and presses the semiconductor pellet 3 toward the base substrate 1.
C and the other end of the bump electrode 4 are pressed and fixed. With this configuration, of the electrode 1A of the base substrate 1 and the electrode 3C of the semiconductor pellet 3, the electrode 3C of the semiconductor pellet 3 is not fixedly fixed to the bump electrode 4, so that the electrode 1C of the base substrate 1 and the semiconductor pellet 3 are not fixed. The positional relationship with the electrode 3C can be shifted in the plane direction. As a result, in the heat treatment process during the temperature cycle which is an environmental test after the product is completed or when the semiconductor device is mounted on the mounting substrate, the thermal stress caused by the difference in thermal expansion coefficient between the base substrate 1 and the semiconductor pellet 3 is caused. Can be mitigated by the positional deviation between the electrode 1A of the base substrate 1 and the electrode 3C of the semiconductor pellet 3, so that the bump electrode 4 that electrically connects the electrode 1A of the base substrate 1 and the electrode 3C of the semiconductor pellet 3 can be reduced. It is possible to prevent damage and improve reliability of the semiconductor device with respect to heat.
【００２９】また、ベース基板１、半導体ペレット３の
夫々の熱膨張係数の差に起因する熱応力をベース基板１
の電極１Ａと半導体ペレット３の電極３Ｃとの位置ずれ
で緩和することができるので、ベース基板１を半導体ペ
レット３の熱膨張係数に近い材料からなるセラミックス
基板で形成する必要がなく、ベース基板１をセラミック
ス基板に比べて部品コストの低い樹脂基板で形成するこ
とができる。この結果、ベース基板１の部品コストに相
当する分、半導体装置の製造コストを低減することがで
きる。Further, the thermal stress caused by the difference in thermal expansion coefficient between the base substrate 1 and the semiconductor pellet 3 is applied to the base substrate 1
Since it can be relaxed by the positional deviation between the electrode 1A of the semiconductor pellet 3 and the electrode 3C of the semiconductor pellet 3, it is not necessary to form the base substrate 1 with a ceramic substrate made of a material having a thermal expansion coefficient close to that of the semiconductor pellet 3, and the base substrate 1 Can be formed of a resin substrate whose component cost is lower than that of a ceramic substrate. As a result, the manufacturing cost of the semiconductor device can be reduced by an amount corresponding to the component cost of the base substrate 1.
【００３０】また、ベース基板１の電極１Ａ、半導体ペ
レット３の電極３Ｃのうち、半導体ペレット３の電極３
Ｃがバンプ電極４に対して押圧固定されているので、ベ
ース基板１と半導体ペレット３との熱膨張係数の整合性
を問わずにベース基板１の電極１Ａと半導体ペレット３
の電極３Ｃとをバンプ電極４で電気的に接続することが
できる。Of the electrode 1A of the base substrate 1 and the electrode 3C of the semiconductor pellet 3, the electrode 3 of the semiconductor pellet 3 is used.
Since C is pressed and fixed to the bump electrode 4, the electrode 1A of the base substrate 1 and the semiconductor pellet 3 are irrespective of the matching of the thermal expansion coefficients of the base substrate 1 and the semiconductor pellet 3.
The electrode 3C can be electrically connected by the bump electrode 4.
【００３１】また、ベース基板１の電極１Ａ、半導体ペ
レット３の電極３Ｃのうち、半導体ペレット３の電極３
Ｃがバンプ電極４に対して押圧固定されているので、ベ
ース基板１の電極１Ａ、半導体ペレット３の電極３Ｃの
うち、半導体ペレット３の電極３Ｃとバンプ電極４との
間に介在される下地金属膜を廃止することができる。こ
の結果、下地金属膜の廃止に相当する分、半導体装置の
製造コストを低減することができる。Of the electrode 1A of the base substrate 1 and the electrode 3C of the semiconductor pellet 3, the electrode 3 of the semiconductor pellet 3 is used.
Since C is pressed and fixed to the bump electrode 4, of the electrode 1A of the base substrate 1 and the electrode 3C of the semiconductor pellet 3, a base metal interposed between the electrode 3C of the semiconductor pellet 3 and the bump electrode 4. The membrane can be abolished. As a result, the manufacturing cost of the semiconductor device can be reduced by the amount corresponding to the elimination of the underlying metal film.
【００３２】（２）前記押圧部材７を、前記ベース基板
１に固定された保護キャップ５と前記半導体ペレット３
との間に配置することにより、半導体ペレット３の占有
面積内において、半導体ペレット３の電極３Ｃとバンプ
電極４の他端側とを押圧固定することができるので、半
導体装置の平面方向の外形サイズを縮小することができ
る。(2) The pressing member 7, the protective cap 5 fixed to the base substrate 1 and the semiconductor pellet 3
Since the electrode 3C of the semiconductor pellet 3 and the other end of the bump electrode 4 can be pressed and fixed within the area occupied by the semiconductor pellet 3, the external size of the semiconductor device in the plane direction Can be reduced.
【００３３】（３）前記バンプ電極４を、前記ベース基
板の電極上にリフトオフ法で形成することにより、各バ
ンプ電極４の高さを均一にすることができるので、半導
体ペレット３の各電極３Ｃと各バンプ電極との押圧固定
を確実に行うことができる。(3) Since the bump electrodes 4 are formed on the electrodes of the base substrate by the lift-off method, the heights of the bump electrodes 4 can be made uniform, so that the electrodes 3C of the semiconductor pellet 3 can be formed. With this, it is possible to surely press and fix the bump electrodes.
【００３４】なお、前記保護キャップ５はエポキシ樹
脂、ポリイミド樹脂等で形成してもよい。The protective cap 5 may be made of epoxy resin, polyimide resin or the like.
【００３５】また、前記押圧部材７であるコイル形状の
バネ部材を半導体ペレット３の裏面をほぼ均一に押圧す
るように大きく形成し、このコイル形状のバネ部材を１
つ配置した構成にしてもよい。The coil-shaped spring member, which is the pressing member 7, is formed large so as to press the back surface of the semiconductor pellet 3 substantially uniformly.
You may make it the structure arrange | positioned.
【００３６】（実 施 例 ２）図２は本発明の実施例２
である半導体装置の断面図である。Example 2 FIG. 2 shows Example 2 of the present invention.
FIG. 3 is a cross-sectional view of the semiconductor device of FIG.
【００３７】図２に示すように、本実施例の半導体装置
は、ベース基板１の主面のペレット塔載領域上にフェー
スダウン方式で半導体ペレット３を塔載し、この半導体
ペレット３をベース基板１及び保護キャップ５で形成さ
れるキャビティ内に気密封止した構造で構成される。As shown in FIG. 2, in the semiconductor device of this embodiment, the semiconductor pellets 3 are mounted on the pellet mounting area of the main surface of the base substrate 1 by a face-down method, and the semiconductor pellets 3 are mounted on the base substrate. 1 and the protective cap 5 are hermetically sealed in the cavity.
【００３８】前記半導体ペレット３の主面にはその外周
縁に沿って複数の電極３Ｃが配置される。前記ベース基
板１の主面のペレット塔載領域には半導体ペレット３の
電極３Ｃと対向する位置に複数の電極１Ａが配置され
る。On the main surface of the semiconductor pellet 3, a plurality of electrodes 3C are arranged along the outer peripheral edge thereof. In the pellet mounting region on the main surface of the base substrate 1, a plurality of electrodes 1A are arranged at positions facing the electrodes 3C of the semiconductor pellet 3.
【００３９】前記ベース基板１の電極１Ａと半導体ペレ
ット３の電極３Ｃとはバンプ電極４で電気的に接続され
ている。バンプ電極４は、その一端側が下地金属膜２を
介在してベース基板１の電極１Ａに固着固定され、その
他端側が半導体ペレット３の電極３Ｃに押圧固定され
る。なお、半導体ペレット３の電極３Ｃとバンプ電極４
との間に介在される下地金属膜は廃止されている。The electrode 1A of the base substrate 1 and the electrode 3C of the semiconductor pellet 3 are electrically connected by the bump electrode 4. One end of the bump electrode 4 is fixed and fixed to the electrode 1A of the base substrate 1 with the underlying metal film 2 interposed therebetween, and the other end of the bump electrode 4 is pressed and fixed to the electrode 3C of the semiconductor pellet 3. The electrode 3C of the semiconductor pellet 3 and the bump electrode 4
The underlying metal film interposed between and is abolished.
【００４０】前記バンプ電極４の他端側と半導体ペレッ
ト３の電極３Ｃとの押圧固定はベース基板１に向って半
導体ペレット３を押圧する押圧部材７の押圧力で行なわ
れる。本実施例の押圧部材７は、弾性力を有する波形状
のバネ部材で形成され、ベース基板１に固定された保護
キャップ５と半導体ペレット３との間に配置される。The other end of the bump electrode 4 and the electrode 3C of the semiconductor pellet 3 are pressed and fixed by the pressing force of the pressing member 7 which presses the semiconductor pellet 3 toward the base substrate 1. The pressing member 7 of this embodiment is formed of a wave-shaped spring member having elastic force, and is arranged between the protective cap 5 fixed to the base substrate 1 and the semiconductor pellet 3.
【００４１】前記ベース基板１と半導体ペレット３との
間の中央領域には熱伝達部材９が配置される。熱伝達部
材９は、例えばエポキシ系樹脂で形成され、半導体ペレ
ット３に塔載された回路システムの動作で発生する熱を
半導体ペレット３からベース基板１に伝達する。A heat transfer member 9 is arranged in the central region between the base substrate 1 and the semiconductor pellet 3. The heat transfer member 9 is formed of, for example, an epoxy resin, and transfers the heat generated by the operation of the circuit system mounted on the semiconductor pellet 3 from the semiconductor pellet 3 to the base substrate 1.
【００４２】このように、本実施例によれば、前述の実
施例１と同様の効果が得られると共に、半導体ペレット
３に塔載された回路システムの動作で発生する熱を半導
体ペレット３からベース基板１に伝達することができの
で、半導体装置の放熱効率を高めることができる。As described above, according to this embodiment, the same effect as that of the above-described first embodiment can be obtained, and the heat generated by the operation of the circuit system mounted on the semiconductor pellet 3 is generated from the semiconductor pellet 3 to the base. Since it can be transmitted to the substrate 1, the heat dissipation efficiency of the semiconductor device can be improved.
【００４３】（実 施 例 ３）図３は本発明の実施例３
である半導体装置の断面図である。Example 3 FIG. 3 shows Example 3 of the present invention.
FIG. 3 is a cross-sectional view of the semiconductor device of FIG.
【００４４】図３に示すように、本実施例の半導体装置
は、ベース基板１の主面のペレット塔載領域上にフェー
スダウン方式で半導体ペレット３を塔載し、この半導体
ペレット３をベース基板１及び保護キャップ５で形成さ
れるキャビティ内に気密封止した構造で構成される。As shown in FIG. 3, in the semiconductor device of this embodiment, the semiconductor pellets 3 are mounted on the pellet mounting area on the main surface of the base substrate 1 in a face-down manner, and the semiconductor pellets 3 are mounted on the base substrate. 1 and the protective cap 5 are hermetically sealed in the cavity.
【００４５】前記半導体ペレット３の主面には複数の電
極３Ｃが行列状に配置される。前記ベース基板１の主面
のペレット塔載領域には複数の電極１Ａが行列状に配置
される。A plurality of electrodes 3C are arranged in a matrix on the main surface of the semiconductor pellet 3. A plurality of electrodes 1A are arranged in a matrix in the pellet mounting region on the main surface of the base substrate 1.
【００４６】前記ベース基板１の電極１Ａと半導体ペレ
ット３の電極３Ｃとはバンプ電極４で電気的に接続され
ている。バンプ電極４は、その一端側が下地金属膜２を
介在してベース基板１の電極１Ａに固着固定され、その
他端側が半導体ペレット３の電極３Ｃに押圧固定され
る。なお、半導体ペレット３の電極３Ｃとバンプ電極４
との間に介在される下地金属膜は廃止されている。The electrode 1A of the base substrate 1 and the electrode 3C of the semiconductor pellet 3 are electrically connected by the bump electrode 4. One end of the bump electrode 4 is fixed and fixed to the electrode 1A of the base substrate 1 with the underlying metal film 2 interposed therebetween, and the other end of the bump electrode 4 is pressed and fixed to the electrode 3C of the semiconductor pellet 3. The electrode 3C of the semiconductor pellet 3 and the bump electrode 4
The underlying metal film interposed between and is abolished.
【００４７】前記バンプ電極４の他端側と半導体ペレッ
ト３の電極３Ｃとの押圧固定は、ベース基板１に向って
半導体ペレット３を押圧する押圧部材７の押圧力で行な
われる。本実施例の押圧部材７は、弾性力を有し、更に
熱伝達率が高い弾性膜で形成される。弾性膜は、例えば
エポキシ系樹脂やシリコン接着剤で形成され、半導体ペ
レット３に塔載された回路システムの動作で発生する熱
を半導体ペレット３から保護キャップ５に伝達する。The other end of the bump electrode 4 and the electrode 3C of the semiconductor pellet 3 are pressed and fixed by the pressing force of the pressing member 7 which presses the semiconductor pellet 3 toward the base substrate 1. The pressing member 7 of this embodiment is formed of an elastic film having an elastic force and a high heat transfer coefficient. The elastic film is formed of, for example, an epoxy resin or a silicon adhesive, and transfers the heat generated by the operation of the circuit system mounted on the semiconductor pellet 3 from the semiconductor pellet 3 to the protective cap 5.
【００４８】このように、本実施例によれば、前述の実
施例１と同様の効果が得られると共に、ベース基板１に
向って半導体ペレット３を押圧する押圧部材７を、弾性
力を有し、更に熱伝達率が高い弾性膜で形成することに
より、半導体ペレット３に塔載された回路システムの動
作で発生した熱を半導体ペレット３から保護キャップ５
に伝達することができので、半導体装置の放熱効率を高
めることができる。As described above, according to this embodiment, the same effect as that of the above-described first embodiment can be obtained, and the pressing member 7 for pressing the semiconductor pellet 3 toward the base substrate 1 has an elastic force. By forming the elastic film having a higher heat transfer coefficient, the heat generated by the operation of the circuit system mounted on the semiconductor pellet 3 is transferred from the semiconductor pellet 3 to the protective cap 5.
Therefore, the heat dissipation efficiency of the semiconductor device can be improved.
【００４９】（実 施 例 ４）図４は本発明の実施例４
である半導体装置の要部断面図である。Example 4 FIG. 4 shows Example 4 of the present invention.
FIG. 3 is a cross-sectional view of essential parts of a semiconductor device that is
【００５０】図４に示すように、本実施例の半導体装置
は、ベース基板１の主面のペレット塔載領域上にフェー
スダウン方式で半導体ペレット３を塔載し、この半導体
ペレット３をベース基板１及び保護キャップ５で形成さ
れるキャビティ内に気密封止した構造で構成される。As shown in FIG. 4, in the semiconductor device of this embodiment, the semiconductor pellets 3 are mounted on the pellet mounting area of the main surface of the base substrate 1 by the face-down method, and the semiconductor pellets 3 are mounted on the base substrate. 1 and the protective cap 5 are hermetically sealed in the cavity.
【００５１】前記半導体ペレット３の主面には複数の電
極３Ｃが行列状に配置される。前記ベース基板１の主面
のペレット塔載領域には複数の電極１Ａが行列状に配置
される。A plurality of electrodes 3C are arranged in a matrix on the main surface of the semiconductor pellet 3. A plurality of electrodes 1A are arranged in a matrix in the pellet mounting region on the main surface of the base substrate 1.
【００５２】前記ベース基板１の電極１Ａと半導体ペレ
ット３の電極３Ｃとはバンプ電極４で電気的に接続され
ている。バンプ電極４は、その一端側がベース基板１の
電極１Ａに押圧固定され、その他端側が下地金属膜(Ｂ
ＬＭ：Ｂall Ｌimiting Ｍetallization)２を介在して
半導体ペレット３の電極３Ｃに固着固定される。下地金
属膜２は、バンプ電極４との濡れ性を高める目的として
半導体ペレット３の電極３Ｃ上に配置される。下地金属
膜２は、これに限定されないが、例えば半導体ペレット
３の電極３Ｃの表面側からＣｒ膜(又はＴｉ膜)、Ｃｕ膜
(又はＮｉ膜)、Ａｕ膜の夫々を順次積層した積層膜で形
成される。なお、ベース基板１の電極１Ａとバンプ電極
４との間に介在される下地金属膜は廃止されている。The electrode 1A of the base substrate 1 and the electrode 3C of the semiconductor pellet 3 are electrically connected by the bump electrode 4. One end side of the bump electrode 4 is pressed and fixed to the electrode 1A of the base substrate 1, and the other end side thereof is a base metal film (B).
It is fixedly fixed to the electrode 3C of the semiconductor pellet 3 via an LM (Ball Limiting Metallization) 2. The base metal film 2 is arranged on the electrode 3C of the semiconductor pellet 3 for the purpose of improving the wettability with the bump electrode 4. The base metal film 2 is not limited to this.
(Or Ni film) and Au film are sequentially laminated. The base metal film interposed between the electrode 1A of the base substrate 1 and the bump electrode 4 is omitted.
【００５３】前記バンプ電極４は、半導体ペレット３の
電極３Ｃ上の下地金属膜２の表面上にリフトオフ法でＳ
ｎ−Ａｇ合金膜を形成することにより形成される。バン
プ電極４は、熱処理によってその形状を球形状に成形す
る工程、所謂ウエットバック処理が施されていない。即
ち、バンプ電極１４の形状は、円錐台形状で形成され、
その縦方向の断面形状は台状に形成される。このように
構成されるバンプ電極４はウエットバック処理が施され
ていないので、ウエットバック処理が施された球形状の
バンプ電極並びに下地金属膜２の表面上にボール供給法
で供給された球形状のバンプ電極に比べて各バンプ電極
４の高さを均一にすることができる。The bump electrode 4 is formed on the surface of the base metal film 2 on the electrode 3C of the semiconductor pellet 3 by the lift-off method.
It is formed by forming an n-Ag alloy film. The bump electrode 4 is not subjected to a so-called wet-back process of forming the bump electrode 4 into a spherical shape by heat treatment. That is, the bump electrode 14 is formed in a truncated cone shape,
The cross-sectional shape in the vertical direction is trapezoidal. Since the bump electrode 4 configured in this manner is not subjected to wet back processing, the spherical bump electrode subjected to wet back processing and the spherical shape supplied on the surface of the underlying metal film 2 by the ball supply method. It is possible to make the height of each bump electrode 4 more uniform than that of the bump electrode.
【００５４】前記バンプ電極４の一端側とベース基板１
の電極１Ａとの押圧固定は、ベース基板１に向って半導
体ペレット３を押圧する押圧部材７の押圧力で行なわれ
る。本実施例の押圧部材７は、弾性力を有し、更に熱伝
達率の高い弾性膜で形成され、ベース基板１に固定され
た保護キャップ５と半導体ペレット３との間に配置され
る。One end of the bump electrode 4 and the base substrate 1
The pressure fixing with the electrode 1A is performed by the pressing force of the pressing member 7 that presses the semiconductor pellet 3 toward the base substrate 1. The pressing member 7 of this embodiment is formed of an elastic film having an elastic force and a high heat transfer coefficient, and is arranged between the protective cap 5 fixed to the base substrate 1 and the semiconductor pellet 3.
【００５５】このように、ベース基板１の電極１Ａと半
導体ペレット３の電極１Ｃとをバンプ電極４を介在して
電気的に接続する半導体装置において、前記半導体ペレ
ット３の電極３Ｃと前記バンプ電極４の他端側とを固着
固定し、前記ベース基板１に向って前記半導体ペレット
３を押圧する押圧部材７の押圧力で前記ベース基板１の
電極１Ａと前記バンプ電極４の一端側とを押圧固定す
る。この構成により、ベース基板１の電極１Ａ、半導体
ペレット３の電極３Ｃのうち、ベース基板１の電極１Ａ
がバンプ電極４に対して固着固定されていないので、ベ
ース基板１の電極１Ｃと半導体ペレット３の電極３Ｃと
の位置関係を平面方向にずらすことができる。この結
果、製品完成後の環境試験である温度サイクル時や実装
基板に半導体装置を実装する実装時の熱処理工程におい
て、ベース基板１、半導体ペレット３の夫々の熱膨張係
数の差に起因する熱応力をベース基板１の電極１Ａと半
導体ペレット３の電極３Ｃとの位置ずれで緩和すること
ができるので、ベース基板１の電極１Ａと半導体ペレッ
ト３の電極３Ｃとを電気的に接続するバンプ電極４の破
損を防止し、熱に対する半導体装置の信頼性を高めるこ
とができる。As described above, in the semiconductor device in which the electrode 1A of the base substrate 1 and the electrode 1C of the semiconductor pellet 3 are electrically connected via the bump electrode 4, the electrode 3C of the semiconductor pellet 3 and the bump electrode 4 are connected. Of the bump electrode 4 and the electrode 1A of the base substrate 1 are pressed and fixed by the pressing force of the pressing member 7 that presses the semiconductor pellet 3 toward the base substrate 1. To do. With this configuration, of the electrode 1A of the base substrate 1 and the electrode 3C of the semiconductor pellet 3, the electrode 1A of the base substrate 1
Is not fixedly fixed to the bump electrode 4, it is possible to shift the positional relationship between the electrode 1C of the base substrate 1 and the electrode 3C of the semiconductor pellet 3 in the plane direction. As a result, in the heat treatment process during the temperature cycle which is an environmental test after the product is completed or when the semiconductor device is mounted on the mounting substrate, the thermal stress caused by the difference in thermal expansion coefficient between the base substrate 1 and the semiconductor pellet 3 is caused. Can be mitigated by the positional deviation between the electrode 1A of the base substrate 1 and the electrode 3C of the semiconductor pellet 3, so that the bump electrode 4 that electrically connects the electrode 1A of the base substrate 1 and the electrode 3C of the semiconductor pellet 3 can be reduced. It is possible to prevent damage and improve reliability of the semiconductor device with respect to heat.
【００５６】また、ベース基板１、半導体ペレット３の
夫々の熱膨張係数の差に起因する熱応力をベース基板１
の電極１Ａと半導体ペレット３の電極３Ｃとの位置ずれ
で緩和することができるので、ベース基板１を半導体ペ
レット３の熱膨張係数に近い材料からなるセラミックス
基板で形成する必要がなく、ベース基板１をセラミック
ス基板に比べて部品コストの低い樹脂基板で形成するこ
とができる。この結果、ベース基板１の部品コストに相
当する分、半導体装置の製造コストを低減することがで
きる。Further, the thermal stress caused by the difference in the thermal expansion coefficient between the base substrate 1 and the semiconductor pellet 3 is applied to the base substrate 1
Since it can be relaxed by the positional deviation between the electrode 1A of the semiconductor pellet 3 and the electrode 3C of the semiconductor pellet 3, it is not necessary to form the base substrate 1 with a ceramic substrate made of a material having a thermal expansion coefficient close to that of the semiconductor pellet 3, and the base substrate 1 Can be formed of a resin substrate whose component cost is lower than that of a ceramic substrate. As a result, the manufacturing cost of the semiconductor device can be reduced by an amount corresponding to the component cost of the base substrate 1.
【００５７】また、ベース基板１の電極１Ａ、半導体ペ
レット３の電極３Ｃのうち、ベース基板１の電極１Ａが
バンプ電極４に対して押圧固定されているので、ベース
基板１と半導体ペレット３との熱膨張係数の整合性を問
わずにベース基板１の電極１Ａと半導体ペレット３の電
極３Ｃとをバンプ電極４で電気的に接続することができ
る。Of the electrode 1A of the base substrate 1 and the electrode 3C of the semiconductor pellet 3, the electrode 1A of the base substrate 1 is pressed and fixed to the bump electrode 4, so that the base substrate 1 and the semiconductor pellet 3 are separated from each other. The electrode 1A of the base substrate 1 and the electrode 3C of the semiconductor pellet 3 can be electrically connected by the bump electrode 4 regardless of the matching of the thermal expansion coefficients.
【００５８】また、ベース基板１の電極１Ａ、半導体ペ
レット３の電極３Ｃのうち、ベース基板１の電極１Ａが
バンプ電極４に対して押圧固定されているので、ベース
基板１の電極１Ａ、半導体ペレット３の電極３Ｃのう
ち、ベース基板１の電極１Ａとバンプ電極４との間に介
在される下地金属膜を廃止することができる。この結
果、下地金属膜の廃止に相当する分、半導体装置の製造
コストを低減することができる。Since the electrode 1A of the base substrate 1 among the electrodes 1A of the base substrate 1 and the electrode 3C of the semiconductor pellet 3 is pressed and fixed to the bump electrode 4, the electrode 1A of the base substrate 1 and the semiconductor pellet are fixed. Of the three electrodes 3C, the base metal film interposed between the electrode 1A of the base substrate 1 and the bump electrode 4 can be eliminated. As a result, the manufacturing cost of the semiconductor device can be reduced by the amount corresponding to the elimination of the underlying metal film.
【００５９】（実 施 例 ５）図５は本発明の実施例５
である半導体装置の要部断面図である。Example 5 FIG. 5 shows Example 5 of the present invention.
FIG. 3 is a cross-sectional view of essential parts of a semiconductor device that is
【００６０】図５に示すように、本実施例の半導体装置
は、ベース基板１の主面のペレット塔載領域上にフェー
スダウン方式で半導体ペレット３を塔載し、この半導体
ペレット３をベース基板１及び保護キャップ５で形成さ
れるキャビティ内に気密封止した構造で構成される。As shown in FIG. 5, in the semiconductor device of this embodiment, the semiconductor pellets 3 are mounted face down on the pellet mounting region on the main surface of the base substrate 1, and the semiconductor pellets 3 are mounted on the base substrate. 1 and the protective cap 5 are hermetically sealed in the cavity.
【００６１】前記半導体ペレット３の主面には複数の電
極３Ｃが行列状に配置される。前記ベース基板１の主面
のペレット塔載領域には複数の電極１Ａが行列状に配置
される。A plurality of electrodes 3C are arranged in a matrix on the main surface of the semiconductor pellet 3. A plurality of electrodes 1A are arranged in a matrix in the pellet mounting region on the main surface of the base substrate 1.
【００６２】前記ベース基板１の電極１Ａと半導体ペレ
ット３の電極３Ｃとはバンプ電極４で電気的に接続され
ている。バンプ電極４は、その一端側が下地金属膜２を
介在してベース基板１の電極１Ａに固着固定され、その
他端側が半導体ペレット３の電極３Ｃに押圧固定され
る。下地金属膜２は、バンプ電極４との濡れ性を高める
目的としてベース基板１の電極１Ａ上に配置される。下
地金属膜２は、これに限定されないが、例えばベース基
板１の電極１Ａの表面側からＡｕ膜、Ｎｉ膜の夫々を順
次積層した積層膜で形成される。なお、半導体ペレット
３の電極３Ｃとバンプ電極４との間に介在される下地金
属膜は廃止されている。The electrode 1A of the base substrate 1 and the electrode 3C of the semiconductor pellet 3 are electrically connected by the bump electrode 4. One end of the bump electrode 4 is fixed and fixed to the electrode 1A of the base substrate 1 with the underlying metal film 2 interposed therebetween, and the other end of the bump electrode 4 is pressed and fixed to the electrode 3C of the semiconductor pellet 3. The base metal film 2 is arranged on the electrode 1A of the base substrate 1 for the purpose of improving the wettability with the bump electrode 4. Although not limited to this, the base metal film 2 is formed of, for example, a laminated film in which an Au film and a Ni film are sequentially laminated from the surface side of the electrode 1A of the base substrate 1. The base metal film interposed between the electrode 3C of the semiconductor pellet 3 and the bump electrode 4 is omitted.
【００６３】前記バンプ電極４は、ベース基板１の電極
１Ａ上の下地金属膜２の表面上にリフトオフ法でＳｎ−
Ａｇ合金膜を形成することにより形成される。バンプ電
極４は、熱処理によってその形状を球形状に成形する工
程、所謂ウエットバック処理が施されている。即ち、バ
ンプ電極１４の形状は球形状で形成される。The bump electrode 4 is Sn-formed by the lift-off method on the surface of the base metal film 2 on the electrode 1A of the base substrate 1.
It is formed by forming an Ag alloy film. The bump electrode 4 is subjected to a so-called wet-back process of forming the bump electrode 4 into a spherical shape by heat treatment. That is, the bump electrode 14 is formed in a spherical shape.
【００６４】前記バンプ電極４の他端側と半導体ペレッ
ト３の電極３Ｃとの押圧固定は、ベース基板１に向って
半導体ペレット３を押圧する押圧部材７の押圧力で行な
われる。本実施例の押圧部材７は、弾性力を有し、更に
熱伝達率が高い弾性膜で形成される。The pressing and fixing of the other end of the bump electrode 4 and the electrode 3C of the semiconductor pellet 3 is performed by the pressing force of the pressing member 7 which presses the semiconductor pellet 3 toward the base substrate 1. The pressing member 7 of this embodiment is formed of an elastic film having an elastic force and a high heat transfer coefficient.
【００６５】なお、バンプ電極４は、実装基板１の電極
１Ａ上の下地金属膜２の表面上にボール供給法で供給し
てもよい。The bump electrode 4 may be supplied on the surface of the base metal film 2 on the electrode 1A of the mounting substrate 1 by the ball supply method.
【００６６】このように、本実施例によれば、前述の実
施例３と同様の効果が得られる。As described above, according to this embodiment, the same effect as that of the above-mentioned third embodiment can be obtained.
【００６７】以上、本発明者によってなされた発明を、
前記実施例に基づき具体的に説明したが、本発明は、前
記実施例に限定されるものではなく、その要旨を逸脱し
ない範囲において種々変更可能であることは勿論であ
る。As described above, the invention made by the present inventor is:
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.
【００６８】[0068]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
【００６９】ベース基板の電極と半導体ペレットの電極
とを電気的に接続するバンプ電極の破損を防止し、熱に
対する半導体装置の信頼性を高めることができる。It is possible to prevent the bump electrode electrically connecting the electrode of the base substrate and the electrode of the semiconductor pellet from being damaged, and improve the reliability of the semiconductor device against heat.
【００７０】また、前記半導体装置の製造コストを低減
することができる。Further, the manufacturing cost of the semiconductor device can be reduced.
【図１】本発明の実施例１である半導体装置の断面図で
ある。FIG. 1 is a cross-sectional view of a semiconductor device that is Embodiment 1 of the present invention.
【図２】本発明の実施例２である半導体装置の断面図で
ある。FIG. 2 is a cross-sectional view of a semiconductor device that is Embodiment 2 of the present invention.
【図３】本発明の実施例３である半導体装置の断面図で
ある。FIG. 3 is a cross-sectional view of a semiconductor device that is Embodiment 3 of the present invention.
【図４】本発明の実施例４である半導体装置の要部断面
図である。FIG. 4 is a cross-sectional view of essential parts of a semiconductor device that is Embodiment 4 of the present invention.
【図５】本発明の実施例５である半導体装置の要部断面
図である。FIG. 5 is a cross-sectional view of essential parts of a semiconductor device according to a fifth embodiment of the present invention.
１…ベース基板、１Ａ，１Ｂ…電極、２…下地金属膜、
３…半導体ペレット、３Ａ…Ｓｉ基板、３Ｂ…配線層、
３Ｃ…電極、４…バンプ電極、５…保護キャップ、６…
ろう材、７…押圧部材、８…バンプ電極、９…熱伝達部
材。1 ... Base substrate, 1A, 1B ... Electrode, 2 ... Base metal film,
3 ... Semiconductor pellet, 3A ... Si substrate, 3B ... Wiring layer,
3C ... Electrode, 4 ... Bump electrode, 5 ... Protective cap, 6 ...
Brazing material, 7 ... pressing member, 8 ... bump electrode, 9 ... heat transfer member.
Claims (5)
極とをバンプ電極を介在して電気的に接続する半導体装
置において、前記ベース基板の電極又は前記半導体ペレ
ットの電極と前記バンプ電極の一端側とを固着固定し、
前記ベース基板に向って前記半導体ペレットを押圧する
押圧部材の押圧力で前記半導体ペレットの電極又は前記
ベース基板の電極と前記バンプ電極の他端側とを押圧固
定したことを特徴とする半導体装置。1. A semiconductor device in which an electrode of a base substrate and an electrode of a semiconductor pellet are electrically connected via a bump electrode, and an electrode of the base substrate or an electrode of the semiconductor pellet and one end side of the bump electrode. Firmly fixed,
A semiconductor device, wherein an electrode of the semiconductor pellet or an electrode of the base substrate and the other end of the bump electrode are pressed and fixed by a pressing force of a pressing member that presses the semiconductor pellet toward the base substrate.
された保護キャップと前記半導体ペレットとの間に配置
されることを特徴とする請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein the pressing member is arranged between a protective cap fixed to the base substrate and the semiconductor pellet.
材又は弾性膜で構成されることを特徴とする請求項２に
記載の半導体装置。3. The semiconductor device according to claim 2, wherein the pressing member is composed of a spring member or an elastic film having an elastic force.
含浸させた樹脂基板で構成されることを特徴とする請求
項１乃至請求項３のうちいずれか１項に記載の半導体装
置。4. The semiconductor device according to claim 1, wherein the base substrate is a resin substrate in which glass fiber is impregnated with a resin.
極上又は前記半導体ペレットの電極上にリフトオフ法で
形成されることを特徴とする請求項１乃至請求項４のう
ちいずれか１項に記載の半導体装置。5. The bump electrode is formed on an electrode of the base substrate or an electrode of the semiconductor pellet by a lift-off method, according to any one of claims 1 to 4. Semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7218477A JPH0964096A (en) | 1995-08-28 | 1995-08-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7218477A JPH0964096A (en) | 1995-08-28 | 1995-08-28 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0964096A true JPH0964096A (en) | 1997-03-07 |
Family
ID=16720551
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7218477A Pending JPH0964096A (en) | 1995-08-28 | 1995-08-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0964096A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001127113A (en) * | 1999-10-26 | 2001-05-11 | Nec Corp | Mounting structure for surface mount semiconductor device |
-
1995
- 1995-08-28 JP JP7218477A patent/JPH0964096A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001127113A (en) * | 1999-10-26 | 2001-05-11 | Nec Corp | Mounting structure for surface mount semiconductor device |
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