JPH03171744A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH03171744A JPH03171744A JP1311365A JP31136589A JPH03171744A JP H03171744 A JPH03171744 A JP H03171744A JP 1311365 A JP1311365 A JP 1311365A JP 31136589 A JP31136589 A JP 31136589A JP H03171744 A JPH03171744 A JP H03171744A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- substrate
- metal film
- semiconductor device
- back surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 239000002184 metal Substances 0.000 claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 21
- 239000011889 copper foil Substances 0.000 abstract description 21
- 230000005855 radiation Effects 0.000 abstract description 2
- 238000001816 cooling Methods 0.000 abstract 2
- 230000017525 heat dissipation Effects 0.000 description 19
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 239000010931 gold Substances 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000005496 eutectics Effects 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000010348 incorporation Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910015363 Au—Sn Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的コ
（産業上の利用分野）
本発明は、半導体素子チップを絶縁性基板に実装した半
導体装置及びその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Objective of the Invention (Industrial Application Field) The present invention relates to a semiconductor device in which a semiconductor element chip is mounted on an insulating substrate, and a method for manufacturing the same.
（従来の技術）
従来、フィルムキャリアを用いた半導体素子チップの組
み立て技術は、接続技術又はバッケージング技術の一つ
として利用されている。フィルムキャリアを用いた組み
立て技術の利点として、電極パッドの多ピン化，パッケ
ージの薄型化，組み立て時間の短縮，良好な高周波特性
等があげられるが、パッド数の増加に伴う高発熱化に対
しては十分な配慮はされていない。(Prior Art) Conventionally, a technique for assembling semiconductor element chips using a film carrier has been used as one of connection techniques or packaging techniques. Advantages of assembly technology using film carriers include increased number of electrode pad pins, thinner package, shorter assembly time, and better high-frequency characteristics. has not been given sufficient consideration.
第６図に、従来から行われているフィルムキャリアの典
型的な実装形態を示す。この図において、１は半導体素
子チップ、２はバンプ、３は絶縁性基板（フイルム）、
４は配線リード、５は実装ボードを示している。図から
判るように、半導体素子チップ１から発熱した熱は熱伝
導では配線リード４によって移動し、それ以外の熱伝達
ではチップ表面から輻射や対流により拡散することにな
る。チップが樹脂封止されている場合は、樹脂内の熱伝
導と樹脂表面からの熱伝達により熱は拡散する。FIG. 6 shows a typical mounting form of a conventional film carrier. In this figure, 1 is a semiconductor element chip, 2 is a bump, 3 is an insulating substrate (film),
4 indicates a wiring lead, and 5 indicates a mounting board. As can be seen from the figure, the heat generated from the semiconductor element chip 1 is transferred by the wiring leads 4 by thermal conduction, and by other heat transfer, it is diffused from the chip surface by radiation or convection. When the chip is sealed with resin, heat is diffused by heat conduction within the resin and heat transfer from the resin surface.
しかしながら、配線リードが細いこと、チップが小さい
こと、又は樹脂の熱伝導率が小さいことにより、十分な
放熱は行われず、チップの発熱がＩＷを越すような場合
には、特別な放熱手段を考える必要があった。放熱の有
効な手段としては、チップ裏面に放熱フィン又はヒート
シンクと呼ばれる金属体を装着する方法があるが、これ
らは占有面積の増大を招き、実装ボード又は実装ボード
への組み込みに利限を与えてしまい、特定の実装ボード
や組み立て技術を′必要とする。However, if the wiring leads are thin, the chip is small, or the thermal conductivity of the resin is low, sufficient heat dissipation is not achieved, and if the heat generated by the chip exceeds the IW, consider special heat dissipation methods. There was a need. An effective means of heat dissipation is to attach a metal body called a heat dissipation fin or heat sink to the back of the chip, but these increase the occupied area and limit the mounting board or incorporation into the mounting board. They require specific mounting boards and assembly techniques.
（発明が解決しようとする課題）
このように従来、フィルムキャリア等の絶縁性基板に半
導体素子チップを実装した場合、チップの放熱は配線リ
ードを介しての熱伝導が主であり、チップの放熱が不十
分であった。また、チップ裏面に放熱フィンやヒートシ
ンク等を装着すると、実装ボードへの組み込みに制限を
与える問題があった。(Problem to be Solved by the Invention) Conventionally, when a semiconductor element chip is mounted on an insulating substrate such as a film carrier, heat dissipation from the chip is mainly carried out through the wiring leads; was insufficient. Furthermore, if a heat dissipation fin or a heat sink is attached to the back surface of the chip, there is a problem in that it limits the incorporation into a mounting board.
本発明は、上記事情を考慮してなされたもので、その目
的とするところは、半導体素子チップの裏面に放熱フィ
ンやヒートシンク等を装着することなく、半導体素子チ
ップの高い放熱性を得ることのできる半導体装置及びそ
の製造方法を提供することにある。The present invention has been made in consideration of the above-mentioned circumstances, and its purpose is to obtain high heat dissipation performance of a semiconductor element chip without attaching heat dissipation fins, heat sinks, etc. to the back surface of the semiconductor element chip. An object of the present invention is to provide a semiconductor device that can be used and a method for manufacturing the same.
〔発明の構成１
（課題を解決するための手段）
本発明の骨子は、半導体素子チップの放熱特性向上をは
かるため、チップの裏面と絶縁性基板の裏面とを金属膜
で接続することにより、熱伝導による放熱を増大するこ
とにある。[Structure 1 of the Invention (Means for Solving the Problem) The gist of the present invention is to improve the heat dissipation characteristics of a semiconductor element chip by connecting the back surface of the chip and the back surface of an insulating substrate with a metal film. The purpose is to increase heat dissipation through thermal conduction.
即ち本発明は、表裏面を貫通する開口部が形成され、表
面側に該開口部に一部突出する配線リードが設けられた
絶縁性基板と、表面側に電極パッド又はバンプが設けら
れた半導体素子チップとを備え、チップの電極又はパッ
ドを基板のリードに直接接合してなる半導体装置におい
て、基板の裏面側に金属膜を被着すると共に、チップの
裏面側に該裏面より外方向に突出するよう金属膜を被着
し、チップ裏面の金属膜を基板裏面の金属膜に直接接合
するようにしたものである。That is, the present invention provides an insulating substrate in which an opening passing through the front and back surfaces is formed, a wiring lead is provided on the front side that partially projects into the opening, and a semiconductor is provided with an electrode pad or bump on the front side. In a semiconductor device comprising an element chip and in which electrodes or pads of the chip are directly bonded to leads of a substrate, a metal film is deposited on the back side of the substrate, and a metal film is attached to the back side of the chip and protrudes outward from the back side. A metal film is deposited on the backside of the chip, and the metal film on the backside of the chip is directly bonded to the metal film on the backside of the substrate.
また本発明は、上記構造の半導体装置の製造方法におい
て、半導体素子チップを絶縁性基板に設けられた開口部
に配置し、チップの表面側に設けられた電極パッド又は
バンプを、基板の表面側に設けられ一部が該開口部に突
出した配線リードに直接接合し、次いでチップの裏面側
に被着された金属膜を基板の裏面側に被着された金属膜
に直接接合するようにした方法である。The present invention also provides a method for manufacturing a semiconductor device having the above structure, in which a semiconductor element chip is placed in an opening provided in an insulating substrate, and an electrode pad or bump provided on the front side of the chip is placed on the front side of the substrate. The metal film attached to the back side of the chip is directly bonded to the wiring lead provided on the chip and a part of which protrudes into the opening. It's a method.
（作用）
本発明によれば、半導体素子チップの発熱は配線リード
と共に、チップ裏面に被着した金属膜を介して絶縁性基
板の裏面に被着した金属膜に熱伝導によって伝わる。金
属膜の幅は配線リードの幅よりも格段に広いものであり
、このため熱伝導による放熱特性が著しく向上する。ま
た、金属膜を被着しても実質的な占有体積の増大はなく
、実装ボードへの組み込みに制限を与えることもない。(Function) According to the present invention, heat generated by the semiconductor element chip is transmitted by thermal conduction to the metal film deposited on the back surface of the insulating substrate through the metal film deposited on the back surface of the chip together with the wiring leads. The width of the metal film is much wider than the width of the wiring lead, and therefore the heat dissipation characteristics due to heat conduction are significantly improved. Further, even if a metal film is applied, there is no substantial increase in the occupied volume, and there is no restriction on incorporation into a mounting board.
より一層の放熱を期待する場合には、外部にフィンやヒ
ートシンクを装着してもよいが、この場合も従来構造よ
り有利である。また、フィルムキャリアの全体が表裏で
対称構造に近くなるので、温度変化に対する低応力化を
はかることも可能である。If further heat dissipation is expected, fins or heat sinks may be attached to the outside, but this is also more advantageous than the conventional structure. Furthermore, since the entire film carrier has a nearly symmetrical structure on the front and back sides, it is also possible to reduce stress against temperature changes.
（大施例） 以下、本発明の詳細を図示の実施例によって説明する。(Major example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.
第１図は本発明の一実施例に係わる半導体装置の概略構
成を示す平面図、第２図（ａ）は第１図のＡ−Ａ方向矢
視図、第２図（ｂ）は第１図の矢視１３−Ｂ断面図であ
る。図中１０はフィルムキャリアとなるポリイミド等の
絶縁性基板であり、この基板１０の表面には配線リード
１１が選択的に設けられている。配線リード１１の一部
は、基板１０に設けられた開口部１０ａに一部突出して
いる。基板１０の裏面の全面には、銅箔（第１の金属膜
）１２が被着されている。FIG. 1 is a plan view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention, FIG. 2(a) is a view taken along arrow A-A in FIG. It is a sectional view taken along arrow 13-B in the figure. In the figure, 10 is an insulating substrate made of polyimide or the like that serves as a film carrier, and wiring leads 11 are selectively provided on the surface of this substrate 10. A portion of the wiring lead 11 partially protrudes into an opening 10a provided in the substrate 10. A copper foil (first metal film) 12 is adhered to the entire back surface of the substrate 10 .
半導体素子チップ２０は、基板１０の開口部１０ａ内に
配置され、チップ２０の表面に設けられたバンプ２１が
配線リード１１の突出部１１ａに接続されている。また
、チップ２０の裏面には銅箔（第２の金属膜）１３が被
着され、この銅箔１３の周辺部は基板１０の裏面の銅箔
１２に接続されている。なお、チップ２０のバンプ２１
は必ずしも必要なく、チップ２０の電極端子を配線リー
ド１１の突出部１１ａに直接接合してもよい。The semiconductor element chip 20 is placed in the opening 10a of the substrate 10, and the bumps 21 provided on the surface of the chip 20 are connected to the protrusions 11a of the wiring leads 11. Further, a copper foil (second metal film) 13 is adhered to the back surface of the chip 20, and the peripheral portion of this copper foil 13 is connected to the copper foil 12 on the back surface of the substrate 10. Note that the bump 21 of the chip 20
is not necessarily necessary, and the electrode terminals of the chip 20 may be directly joined to the protruding portions 11a of the wiring leads 11.
次に、上記構成の半導体装置の製造方法について説明す
る。Next, a method for manufacturing the semiconductor device having the above structure will be described.
まず、第３図（ａ）に示す如く、ポリイミド等のフィル
ム１０の表裏面に接着剤１４をそれぞれ塗布する。続い
て、第３図（ｂ）に示す如く、フィルム１０の裏面に接
着剤１４を介して銅箔１２を接着する。その後、第３図
（ｅ）に示す如く、フィルム１０に開口部１０ａを開け
る。First, as shown in FIG. 3(a), adhesive 14 is applied to the front and back surfaces of a film 10 made of polyimide or the like. Subsequently, as shown in FIG. 3(b), a copper foil 12 is bonded to the back surface of the film 10 via an adhesive 14. Thereafter, as shown in FIG. 3(e), an opening 10a is opened in the film 10.
次いで、第３図（ｄ）に示す如くフィルム１０の表面に
接着剤１４を介して銅箔１１′を接青する。続いて、銅
箔１１′を所望パターンにエッチングして前記第１図に
示す如き配線リード１１を形戊する。その後、フィルム
１０の表面にソルダーレジスト１５を塗布する。これに
よって、フィルムキャリアが形或される。Next, as shown in FIG. 3(d), a copper foil 11' is attached to the surface of the film 10 via an adhesive 14. Subsequently, the copper foil 11' is etched into a desired pattern to form the wiring leads 11 as shown in FIG. After that, a solder resist 15 is applied to the surface of the film 10. This forms the film carrier.
一方、第４図（ａ）に示す如く、半導体素子チップ１０
の裏面に厚さ３５μｍ程度のオンス銅箔１３をダイボン
ディングにより接着する。ダイボンディング法としては
、共晶，樹脂接合のいずれを用いてもよいが、共品接合
の方が放熱性は良い。このとき、ダイボンディングする
銅箔１３は、第５図に示す如くチップ裏面全体に接触す
る矩形部と、この矩形の各辺から外方向に伸びた４つの
延長部を有するものとする。On the other hand, as shown in FIG. 4(a), the semiconductor element chip 10
An ounce copper foil 13 having a thickness of approximately 35 μm is adhered to the back surface of the substrate by die bonding. As the die bonding method, either eutectic bonding or resin bonding may be used, but eutectic bonding has better heat dissipation. At this time, the copper foil 13 to be die-bonded has a rectangular part that contacts the entire back surface of the chip and four extension parts extending outward from each side of this rectangle, as shown in FIG.
次いで、第４図（ｂ）に示す如く、フィルムキャリアの
開口部１０ａに下側からチップ２０を挿入し、チップ２
０のバンプ２１と配線リード１１の突出部１１ａとを位
置合わせする。この状態で通常のＩ Ｌ Ｂ （ Ｉｎ
ｎｅｒ Ｌｅａｄ Ｂｏｎｄｉｎｇ）法により、配線リ
ード１１とバンプ２１とを接続する。即ち、配線リード
１１に上方からＩＬＢツール３１を押し付け、加熱・加
圧することにより配線リード１１とバンプ２１と配線リ
ード１１とを接合する。Next, as shown in FIG. 4(b), the chip 20 is inserted into the opening 10a of the film carrier from below, and the chip 20 is inserted into the opening 10a of the film carrier.
The bump 21 of No. 0 and the protruding portion 11a of the wiring lead 11 are aligned. In this state, normal IL B (In
The wiring lead 11 and the bump 21 are connected by the ner lead bonding method. That is, the ILB tool 31 is pressed against the wiring lead 11 from above, and the wiring lead 11, the bump 21, and the wiring lead 11 are joined by applying heat and pressure.
次いで、第４図＜ｃ＞に示す如く、ＩＬＢツ−ル３２を
用いてチップ裏面の銅箔〕３をフィルム裏面の銅箔１２
に熱圧着により接合する。これにより、前記第１図及び
第２図に示す構造が実現されることになる。ここで、銅
箔１２，１３の接合は、Ａｕ−Ａｕ又はＡｕ−Ｓｎによ
る熱圧着や共晶接合が望ましいので、一方にＡｕメッキ
を、他方にＡｕ又はＳｎメッキを施すのが望ましい。Next, as shown in FIG.
It is joined by thermocompression bonding. As a result, the structure shown in FIGS. 1 and 2 is realized. Here, it is desirable to bond the copper foils 12 and 13 by thermocompression bonding or eutectic bonding using Au-Au or Au-Sn, so it is desirable to plate one of them with Au and plate the other with Au or Sn.
加熱・加圧はツール３２を用いて行うが、ツール温度４
００〜５００℃で接合部を３５０℃程度として、単位接
合面積当り５〜１０ ｋｇ／ｍｍ２の荷重により良好な
接合が行える。Heating and pressurization are performed using the tool 32, but the tool temperature is 4.
Good bonding can be achieved with a temperature of 00 to 500° C. and a temperature of about 350° C. at the joint, and a load of 5 to 10 kg/mm 2 per unit bonding area.
このようにして作成した半導体装置では、従来と同様な
実装ボードへの搭載（第６図に示すような搭載）であっ
ても、１０％程度の放熱性の向上が見込まれる。素子サ
イズ，フィルムサイズによりその効果は異なるが、両者
のサイズに差があるほど高い効果が得られる。In the semiconductor device produced in this manner, it is expected that the heat dissipation performance will be improved by about 10% even when mounted on a conventional mounting board (mounting as shown in FIG. 6). Although the effect differs depending on the element size and film size, the greater the difference between the two sizes, the higher the effect can be obtained.
かくして本実施例によれば、基板裏面及びチップ裏面に
銅箔１２，１３を接着し、これらの銅箔１２，１３を接
合しているので、銅箔１２，１３を介しての熱伝導が大
きくなり、これにリチップ２０の放熱性の向上をはかる
ことがきる。そしてこの場合、チップ裏面に放熱フン等
を設ける構造とは異なり、占有体積の増は実質的になく
、従って実装に制限を与えるの不都合は生じない。また
、銅箔１２，１３接合することにより、チップ２０の基
板１０対するマウント強度の向上をはかることもでる。Thus, according to this embodiment, since the copper foils 12 and 13 are bonded to the back surface of the board and the back surface of the chip, heat conduction through the copper foils 12 and 13 is increased. Therefore, the heat dissipation of the rechip 20 can be improved. In this case, unlike a structure in which a heat dissipation fan or the like is provided on the back surface of the chip, there is substantially no increase in the occupied volume, and therefore there is no inconvenience in limiting the mounting. Further, by bonding the copper foils 12 and 13, it is possible to improve the mounting strength of the chip 20 to the substrate 10.
なお、本発明は上述した実施例に限定されものではない
。例えば、前記配線リードや金１膜として用いる材料は
銅箔に限定されるもの゜はなく、熱伝導及び電気伝導の
良好な金属で２ればよい。さらに、金属膜を形成する方
広とては接着の代わりに、蒸着やスパッタを利用１るこ
とも，可能である。また、基板はボリイミフィルム等の
可撓性を有する材料に限るものコはなく、絶縁体であれ
ば用いることができる。Note that the present invention is not limited to the embodiments described above. For example, the material used for the wiring leads and the gold film is not limited to copper foil, and may be any metal with good thermal and electrical conductivity. Furthermore, it is also possible to use vapor deposition or sputtering instead of adhesion for forming the metal film. Further, the substrate is not limited to a flexible material such as a polyimide film, and any insulating material can be used.
その他、本発明の要旨を逸脱しない範囲で、ｆ々変形し
て実施することができる。In addition, numerous modifications can be made without departing from the gist of the present invention.
［発明の効果］
以上詳述したように本発明によれば、チップの裏面と絶
縁性基板の裏面とを金属膜で接続することにより、熱伝
導による放熱を増大させることができ、実装ボードへの
装着法とは無関係に、単一パッケージ体としても半導体
素子チップの高い放熱性を得ることのできる半導体装置
を実現することが可能となる。[Effects of the Invention] As detailed above, according to the present invention, by connecting the back surface of the chip and the back surface of the insulating substrate with a metal film, heat dissipation due to thermal conduction can be increased, and heat dissipation to the mounting board can be increased. Regardless of the mounting method, it is possible to realize a semiconductor device that can obtain high heat dissipation performance of a semiconductor element chip even as a single package.
第１図本発明の一実施例に係わる半導体装置の概略構造
を示す平面図、第２図（ａ）は第１図のＡ−Ａ方向矢視
図、第２図（ｂ）は第１図の矢視Ｂ−８断面図、第３図
はフィルムキャリアの製造工程を示す断面図、第４図は
チップの実装工程を示す断面図、第５図はチップ裏面に
被着する銅箔の形状を示す斜視図、第６図は従来装置の
問題点を説明するための断面図である。
１０・・・ポリイミドフィルム（絶縁性基板）、１１・
・・配線リード、
１２・・・銅箔（第１の金属膜）、
３・・・銅箔（第２の金属膜）
０・・・半導体素子チップ、
１・・・バンプ、
１，３２・・・ＩＬＢツール。FIG. 1 is a plan view showing a schematic structure of a semiconductor device according to an embodiment of the present invention; FIG. 2(a) is a view taken along the arrow A-A in FIG. 1; FIG. Figure 3 is a cross-sectional view showing the film carrier manufacturing process, Figure 4 is a cross-sectional view showing the chip mounting process, and Figure 5 is the shape of the copper foil adhered to the back of the chip. FIG. 6 is a sectional view for explaining the problems of the conventional device. 10... Polyimide film (insulating substrate), 11.
...Wiring lead, 12...Copper foil (first metal film), 3...Copper foil (second metal film) 0...Semiconductor element chip, 1...Bump, 1,32... ...ILB tool.
Claims (3)
開口部に一部突出する配線リードが設けられると共に、
裏面側に金属膜が被着された絶縁性基板と、表面側に電
極パッド又はバンプが設けられると共に、裏面側に該裏
面より外方向に突出するよう金属膜が被着された半導体
素子チップとを具備し、 前記チップの電極又はパッドは前記基板のリードに直接
接合され、前記チップ裏面の金属膜は前記基板裏面の金
属膜に直接接合されてなることを特徴とする半導体装置
。(1) An opening that penetrates the front and back surfaces is formed, and a wiring lead that partially projects into the opening is provided on the front side, and
An insulating substrate having a metal film adhered to the back side, an electrode pad or bump provided to the front side, and a semiconductor element chip having a metal film adhered to the back side so as to protrude outward from the back side. A semiconductor device comprising: electrodes or pads of the chip are directly bonded to leads of the substrate, and a metal film on the back surface of the chip is directly bonded to a metal film on the back surface of the substrate.
接する矩形状のチップ接触部と、該チップ接触部の各辺
からそれぞれ外側に突出され前記基板裏面の金属膜に直
接接合される４つの延長部とからなるものであることを
特徴とする請求項１記載の半導体装置。(2) The metal film on the back surface of the chip has a rectangular chip contact portion in contact with the back surface of the chip, and 4 which protrudes outward from each side of the chip contact portion and is directly bonded to the metal film on the back surface of the substrate. 2. The semiconductor device according to claim 1, wherein the semiconductor device comprises two extension portions.
体装置の製造方法において、 前記チップを前記基板に設けられた開口部に配置し、前
記チップの表面側に設けられた電極パッド又はバンプを
、前記基板の表面側に設けられ一部が該開口部に突出し
た配線リードに直接接合する工程と、前記チップの裏面
側に被着された金属膜を前記基板の裏面側に被着された
金属膜に直接接合する工程とを含むことを特徴とする半
導体装置の製造方法。(3) In a method for manufacturing a semiconductor device in which a semiconductor element chip is mounted on an insulating substrate, the chip is placed in an opening provided in the substrate, and electrode pads or bumps provided on the front side of the chip are arranged. , a step of directly bonding to a wiring lead provided on the front side of the substrate and partially protruding into the opening, and a step of attaching a metal film attached to the back side of the chip to the back side of the substrate. 1. A method for manufacturing a semiconductor device, comprising the step of directly bonding to a metal film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1311365A JPH03171744A (en) | 1989-11-30 | 1989-11-30 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1311365A JPH03171744A (en) | 1989-11-30 | 1989-11-30 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03171744A true JPH03171744A (en) | 1991-07-25 |
Family
ID=18016291
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1311365A Pending JPH03171744A (en) | 1989-11-30 | 1989-11-30 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03171744A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6365980B1 (en) * | 1999-02-26 | 2002-04-02 | Texas Instruments Incorporated | Thermally enhanced semiconductor ball grid array device and method of fabrication |
| JP2006196885A (en) * | 2005-01-14 | 2006-07-27 | Internatl Business Mach Corp <Ibm> | Method and device for heat dissipation in semiconductor modules |
| CN100461392C (en) * | 2004-07-14 | 2009-02-11 | 三星电子株式会社 | Semiconductor package |
-
1989
- 1989-11-30 JP JP1311365A patent/JPH03171744A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6365980B1 (en) * | 1999-02-26 | 2002-04-02 | Texas Instruments Incorporated | Thermally enhanced semiconductor ball grid array device and method of fabrication |
| CN100461392C (en) * | 2004-07-14 | 2009-02-11 | 三星电子株式会社 | Semiconductor package |
| JP2006196885A (en) * | 2005-01-14 | 2006-07-27 | Internatl Business Mach Corp <Ibm> | Method and device for heat dissipation in semiconductor modules |
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