JPH0955888A - Solid-state image pickup element and image pickup device using this element - Google Patents

Solid-state image pickup element and image pickup device using this element

Info

Publication number
JPH0955888A
JPH0955888A JP7205551A JP20555195A JPH0955888A JP H0955888 A JPH0955888 A JP H0955888A JP 7205551 A JP7205551 A JP 7205551A JP 20555195 A JP20555195 A JP 20555195A JP H0955888 A JPH0955888 A JP H0955888A
Authority
JP
Japan
Prior art keywords
signal
output
image pickup
solid
state image
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7205551A
Other languages
Japanese (ja)
Other versions
JP3680366B2 (en
Inventor
Kazuya Yonemoto
和也 米本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP20555195A priority Critical patent/JP3680366B2/en
Priority to KR1019960033319A priority patent/KR100431233B1/en
Publication of JPH0955888A publication Critical patent/JPH0955888A/en
Application granted granted Critical
Publication of JP3680366B2 publication Critical patent/JP3680366B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70SSIS architectures; Circuits associated therewith
    • H04N25/76Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/771Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/148Charge coupled imagers
    • H01L27/14806Structural or functional details thereof
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50Control of the SSIS exposure
    • H04N25/57Control of the dynamic range

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

PROBLEM TO BE SOLVED: To extend the dynamic range of the output signal quantity to incident light quantity. SOLUTION: For example, two load capacities 18 and 19 are provided for one vertical signal line 13, and signals outputted from picture elements in plural rows different by storage times are read out through vertical signal lines 13 by MOS transistors 16 and 17 as operation switched and are stored in load capacities 18 and 19. Meanwhile, signals stored in load capacities 18 and 19 are led out from output terminals 25 and 26 through horizontal signal lines 22 and 23 by MOS transistors 20 and 21.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、固体撮像素子およ
びこれを用いた撮像装置に関し、特に光電変換によって
得られる画素情報を画素単位で読み出すことが可能なX
‐Yアドレス型固体撮像素子およびこれを用いた撮像装
置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device and an image pickup apparatus using the same, and more particularly, it is possible to read pixel information obtained by photoelectric conversion in pixel units.
The present invention relates to a Y-address type solid-state imaging device and an imaging device using the same.

【0002】[0002]

【従来の技術】X‐Yアドレス型固体撮像素子の一種で
ある増幅型固体撮像素子では、画素そのものに増幅機能
を持たせるために、MOS構造等の能動素子(MOSト
ランジスタ)を用いて画素を構成している。この増幅型
固体撮像素子の従来例を図8に示す。図8において、画
素トランジスタ81が行列状に多数配列され、各画素ト
ランジスタ81のゲート電極が行単位で垂直選択線82
に接続され、各ソース電極が列単位で垂直信号線83に
接続され、さらに各ドレイン電極には電源電圧VDが印
加されている。各垂直選択線82は、垂直スキャナ84
の出力端に接続されている。
2. Description of the Related Art In an amplification type solid-state image sensor, which is a type of XY address type solid-state image sensor, an active element (MOS transistor) having a MOS structure or the like is used to form a pixel so that the pixel itself has an amplification function. I am configuring. A conventional example of this amplification type solid-state imaging device is shown in FIG. In FIG. 8, a large number of pixel transistors 81 are arranged in a matrix, and the gate electrodes of the respective pixel transistors 81 are arranged in rows in units of vertical selection lines 82.
, Each source electrode is connected to the vertical signal line 83 in column units, and the power supply voltage VD is applied to each drain electrode. Each vertical selection line 82 has a vertical scanner 84.
Connected to the output end of the

【0003】各垂直信号線83は、動作スイッチである
NchMOSトランジスタ85のドレイン電極に接続さ
れている。このMOSトランジスタ85のソース電極
は、負荷容量86の一端に接続されるとともに、水平ス
イッチであるNchMOSトランジスタ87のドレイン
電極に接続され、そのゲート電極には、動作パルスφO
Pが印加される。負荷容量86の他端は接地されてい
る。MOSトランジスタ87のソース電極は水平信号線
88に接続され、そのゲート電極は水平走査回路89の
出力端に接続されている。水平信号線88の一端は、出
力端子90に接続されている。
Each vertical signal line 83 is connected to the drain electrode of an NchMOS transistor 85 which is an operation switch. The source electrode of the MOS transistor 85 is connected to one end of the load capacitance 86 and also to the drain electrode of the NchMOS transistor 87 which is a horizontal switch, and its gate electrode has an operation pulse φO.
P is applied. The other end of the load capacitance 86 is grounded. The source electrode of the MOS transistor 87 is connected to the horizontal signal line 88, and the gate electrode thereof is connected to the output terminal of the horizontal scanning circuit 89. One end of the horizontal signal line 88 is connected to the output terminal 90.

【0004】上記構成の増幅型固体撮像素子において、
入射光は画素トランジスタ81にてその光量に応じた電
荷量の信号電荷に光電変換される。画素トランジスタ8
1からの入射光量に応じた信号は、垂直信号線83を経
て動作スイッチであるMOSトランジスタ85を介して
負荷容量86に保持される。この保持された信号は、水
平走査回路89によって制御される水平スイッチである
MOSトランジスタ87を介して水平信号線88に出力
され、さらにこの水平信号線88を通して出力端子90
から外部へ導出される。
In the amplification type solid-state image pickup device having the above structure,
The incident light is photoelectrically converted by the pixel transistor 81 into a signal charge having a charge amount corresponding to the light amount. Pixel transistor 8
A signal corresponding to the amount of incident light from 1 is held in the load capacitance 86 via the vertical signal line 83 and the MOS transistor 85 which is an operation switch. The held signal is output to the horizontal signal line 88 via the MOS transistor 87, which is a horizontal switch controlled by the horizontal scanning circuit 89, and the output terminal 90 is further passed through the horizontal signal line 88.
From the outside.

【0005】このような増幅型固体撮像素子では、光電
変換によって単位画素に蓄積された信号電荷に対してほ
ぼ線形な出力信号が得られ、単位画素の蓄積できる信号
電荷量によって撮像素子のダイナミックレンジが決定さ
れてしまう。図9は、撮像素子の入射光量と出力信号量
の関係を示す入出力特性図である。この入出力特性図か
ら明らかなように、撮像素子のダイナミックレンジは、
画素の飽和信号量とノイズレベルで決まってしまう。
In such an amplification type solid-state image pickup device, an output signal which is almost linear with respect to the signal charge accumulated in the unit pixel is obtained by photoelectric conversion, and the dynamic range of the image pickup device depends on the amount of signal charge that can be accumulated in the unit pixel. Will be decided. FIG. 9 is an input / output characteristic diagram showing the relationship between the amount of incident light and the amount of output signal of the image sensor. As is clear from this input / output characteristic diagram, the dynamic range of the image sensor is
It is determined by the saturation signal amount and noise level of the pixel.

【0006】[0006]

【発明が解決しようとする課題】上述したように、従来
の増幅型固体撮像素子では、単位画素の蓄積できる信号
電荷量は、単位画素の大きさに応じて限界があることか
ら、低輝度の被写体にカメラレンズの絞りを合わせると
高輝度の被写体の信号は飽和してしまい、逆に高輝度の
被写体にカメラレンズの絞りを合わせると低輝度の被写
体の信号はノイズに埋もれてしまうため、画像認識等に
要求されるダイナミックレンジを得ることができなかっ
た。
As described above, in the conventional amplification type solid-state image pickup device, the amount of signal charge that can be stored in a unit pixel is limited according to the size of the unit pixel, so that the brightness is low. If the aperture of the camera lens is adjusted to the subject, the signal of the high-luminance subject will be saturated, and if the aperture of the camera lens is adjusted to the high-luminance subject, the signal of the low-luminance subject will be buried in the noise. We could not obtain the dynamic range required for recognition.

【0007】本発明は、上記課題に鑑みてなされたもの
であり、その目的とするところは、入射光量対出力信号
量のダイナミックレンジを飛躍的に拡大することが可能
な固体撮像素子およびこれを用いた撮像装置を提供する
ことにある。
The present invention has been made in view of the above problems, and an object thereof is to provide a solid-state image pickup device capable of dramatically expanding the dynamic range of the incident light amount to the output signal amount and the solid-state image pickup device. An object is to provide an imaging device used.

【0008】[0008]

【課題を解決するための手段】本発明による固体撮像素
子では、同一列の画素を共通に接続した垂直信号線の各
々に対して複数の記憶手段を設け、蓄積時間が異なる複
数行の画素から出力される信号を垂直信号線を通して複
数の第1のスイッチ手段によって読み出して複数の記憶
手段に記憶させる一方、これらの記憶手段に記憶された
信号を複数の第2のスイッチ手段によって読み出して複
数の水平信号線を通して出力する構成となっている。
In the solid-state image pickup device according to the present invention, a plurality of storage means are provided for each vertical signal line to which pixels in the same column are commonly connected, and pixels from a plurality of rows with different storage times are provided. The output signals are read out by the plurality of first switch means through the vertical signal lines and stored in the plurality of storage means, while the signals stored in these storage means are read out by the plurality of second switch means and are stored in the plurality of storage means. It is configured to output through a horizontal signal line.

【0009】また、本発明による撮像装置では、蓄積時
間が異なる複数行の画素に基づく複数の出力信号を得る
固体撮像素子を用い、この固体撮像素子から出力される
複数の出力信号を信号処理回路で同時化しかつこれらを
加算して映像信号として出力する構成となっている。
Further, in the image pickup device according to the present invention, a solid-state image pickup device for obtaining a plurality of output signals based on a plurality of rows of pixels having different accumulation times is used, and a plurality of output signals output from the solid-state image pickup device are processed by a signal processing circuit. It is configured so that they are synchronized with each other and added to output them as a video signal.

【0010】[0010]

【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照して詳細に説明する。図1は、本発明によ
る固体撮像素子の一実施形態を示す構成図である。図1
において、画素トランジスタ(本例では、NchMOS
トランジスタを示す)11が行列状に多数配列され、各
画素トランジスタ11のゲート電極が行単位で垂直選択
線12に接続され、各ソース電極が列単位で垂直信号線
13に接続され、さらに各ドレイン電極には電源電圧V
Dが印加されている。各垂直選択線12は、垂直走査回
路14および電子シャッタ走査回路15の出力端に接続
されている。
BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a configuration diagram showing an embodiment of a solid-state image sensor according to the present invention. FIG.
, A pixel transistor (in this example, NchMOS
A large number of (indicated by transistors) 11 are arranged in a matrix, the gate electrode of each pixel transistor 11 is connected to a vertical selection line 12 in a row unit, each source electrode is connected to a vertical signal line 13 in a column unit, and each drain is further connected. Power supply voltage V for electrodes
D is applied. Each vertical selection line 12 is connected to the output terminals of the vertical scanning circuit 14 and the electronic shutter scanning circuit 15.

【0011】垂直走査回路14はシフトレジスタ等で構
成されており、垂直走査しつつ各ラインごとに画素情報
を順に読み出すために、各垂直選択線12に対して垂直
選択パルスφV(…,φVm,…,φVp,…)を与え
る。電子シャッタ走査回路15も同様にシフトレジスタ
等で構成されており、各ラインごとに画素の蓄積時間を
制御するためのものである。
The vertical scanning circuit 14 is composed of a shift register or the like, and in order to sequentially read pixel information for each line while performing vertical scanning, a vertical selection pulse φV (..., φVm, , ΦVp, ...) is given. The electronic shutter scanning circuit 15 is also composed of a shift register or the like, and is for controlling the pixel accumulation time for each line.

【0012】各垂直信号線13は、動作スイッチ(第1
のスイッチ手段)である例えば2つのNchMOSトラ
ンジスタ16,17の各ドレイン電極に接続されてい
る。これらMOSトランジスタ16,17は同一サイズ
に形成されており、その各ゲート電極には動作パルスφ
OP1,φOP2が印加される。MOSトランジスタ1
6,17の各ソース電極は、記憶手段である2つの負荷
容量18,19の各一端に接続されるとともに、水平ス
イッチ(第2のスイッチ手段)である2つのNchMO
Sトランジスタ20,21の各ドレイン電極に接続され
ている。負荷容量18,19の各他端は共に接地されて
いる。
Each vertical signal line 13 has an operation switch (first
Of the NchMOS transistors 16 and 17, which are the switching means of the above). These MOS transistors 16 and 17 are formed to have the same size, and the operation pulse φ is applied to each gate electrode thereof.
OP1 and φOP2 are applied. MOS transistor 1
Each of the source electrodes 6 and 17 is connected to one end of each of two load capacitors 18 and 19 which are storage means, and two NchMOs which are horizontal switches (second switch means).
The drain electrodes of the S transistors 20 and 21 are connected. The other ends of the load capacitors 18 and 19 are both grounded.

【0013】MOSトランジスタ20,21の各ソース
電極は水平信号線22,23にそれぞれ接続され、各ゲ
ート電極は水平走査回路24の出力端に共通に接続され
ている。この水平走査回路24はシフトレジスタ等で構
成され、MOSトランジスタ20,21を導通状態に
し、負荷容量18,19の各一端を水平信号線22,2
3に接続するために、MOSトランジスタ20,21の
各ゲート電極に対して水平走査パルスφH(…,φV
n,φVn+1,…)を与える。水平信号線22,23
の各一端は、出力端子25,26にそれぞれ接続されて
いる。以上により、増幅型固体撮像素子10が構成され
ている。
The source electrodes of the MOS transistors 20 and 21 are connected to the horizontal signal lines 22 and 23, respectively, and the gate electrodes are commonly connected to the output terminal of the horizontal scanning circuit 24. The horizontal scanning circuit 24 is composed of a shift register or the like, makes the MOS transistors 20 and 21 conductive, and connects one end of each of the load capacitors 18 and 19 to the horizontal signal lines 22 and 2.
3, the horizontal scanning pulse φH (..., φV) is applied to each gate electrode of the MOS transistors 20 and 21.
n, φVn + 1, ...) Is given. Horizontal signal lines 22, 23
One end of each is connected to the output terminals 25 and 26, respectively. The amplification type solid-state imaging device 10 is configured as described above.

【0014】次に、上記構成の増幅型固体撮像素子10
の動作について説明する。先ず、垂直走査期間にほぼ近
い時間だけ蓄積したφVm行の垂直選択線12の画素ト
ランジスタ11を、ある水平ブランキング期間に垂直信
号線13から動作スイッチであるMOSトランジスタ1
6を介して読み出して負荷容量18に信号電圧として保
持する。そして、読み出しが終わったφVm行の垂直選
択線12の画素トランジスタ11については、当該画素
トランジスタ11に蓄積した信号電荷をリセットする。
なお、画素の蓄積時間の制御は、電子シャッタ走査回路
15によって行われる。
Next, the amplification type solid-state image pickup device 10 having the above structure.
The operation of will be described. First, the pixel transistor 11 of the vertical selection line 12 of the φVm row, which has been accumulated for a time almost close to the vertical scanning period, is switched from the vertical signal line 13 to a MOS transistor 1 which is an operation switch during a certain horizontal blanking period.
It is read out via 6 and held as a signal voltage in the load capacitance 18. Then, with respect to the pixel transistor 11 of the vertical selection line 12 of the φVm row which has been read, the signal charge accumulated in the pixel transistor 11 is reset.
The electronic shutter scanning circuit 15 controls the pixel accumulation time.

【0015】次に、同じ水平ブランキング期間に例えば
1/1000秒前に一度読み出されてリセットされたφ
Vp行の垂直選択線12の画素トランジスタ11の信号
を、垂直選択線12からMOSトランジスタ17を介し
て負荷容量19に読み出して信号電圧として保持する。
読み出しが終わったφVp行の垂直選択線12の画素ト
ランジスタ11については、当該画素トランジスタ11
に蓄積した信号電荷をリセットする。すると、垂直走査
期間をいま仮に1/60秒であるとすると、負荷容量1
8,19にはそれぞれ(1/60−1/1000)秒と
1/1000秒の蓄積時間の信号が保持される。これら
の信号をそれぞれL信号、S信号と称することにする。
Next, in the same horizontal blanking period, φ read once and reset, for example, 1/1000 second before.
The signal of the pixel transistor 11 of the Vp row vertical selection line 12 is read from the vertical selection line 12 to the load capacitance 19 via the MOS transistor 17 and held as a signal voltage.
Regarding the pixel transistor 11 of the vertical selection line 12 of the φVp row for which reading has been completed,
The signal charge accumulated in is reset. Then, assuming that the vertical scanning period is 1/60 second, the load capacitance 1
Signals with storage times of (1 / 60-1 / 1000) seconds and 1/1000 seconds are stored in 8 and 19, respectively. These signals will be referred to as L signal and S signal, respectively.

【0016】この負荷容量18,19に保持されたL,
S信号は、水平スイッチであるMOSトランジスタ2
0,21を介して水平信号線22,23に出力され、さ
らに出力端子25,26を通して出力信号OUT1,O
UT2としてそれぞれ外部へ導出される。ここで、入射
光量に対する出力信号OUT1,OUT2の各信号量の
関係を図示すると図4に示すようになる。すなわち、出
力信号OUT1は従来例の場合と同等の入射光量R1で
飽和してしまうのに対し、もう一方の出力信号OUT2
は入射光量R2まで飽和しない。
L held in the load capacitors 18 and 19
The S signal is the MOS transistor 2 which is a horizontal switch.
0, 21 to the horizontal signal lines 22, 23, and output signals OUT1, O through output terminals 25, 26.
Each is derived to the outside as UT2. Here, FIG. 4 illustrates the relationship between the signal amounts of the output signals OUT1 and OUT2 with respect to the incident light amount. That is, the output signal OUT1 is saturated with the incident light amount R1 equivalent to that in the conventional example, while the other output signal OUT2 is used.
Does not saturate until the incident light amount R2.

【0017】このように、1本の垂直信号線13に対し
て例えば2つの負荷容量18,19を設け、蓄積時間が
異なる複数行の画素から出力される信号を、垂直信号線
13を通してMOSトランジスタ16,17によって読
み出して負荷容量18,19に記憶させる一方、負荷容
量18,19に記憶された信号をMOSトランジスタ2
0,21によって水平信号線22,23を通して出力す
る構成としたことで、単一の固体撮像素子10から同時
に蓄積時間の異なる出力信号OUT1,OUT2が得ら
れる。したがって、従来の固体撮像素子では画素が飽和
してコントラストの得られない映像信号がもう一方の端
子から出力され、別々の端子からではあるが非常に広い
範囲の入射光量に対してコントラストのある信号が得ら
れる。
In this way, for example, two load capacitors 18 and 19 are provided for one vertical signal line 13, and signals output from pixels in a plurality of rows with different storage times are supplied to the vertical signal line 13 through MOS transistors. The signals stored in the load capacitors 18 and 19 are read out by the 16 and 17 and stored in the load capacitors 18 and 19.
The output signals OUT1 and OUT2 having different accumulation times can be simultaneously obtained from the single solid-state image pickup device 10 by outputting the signals through the horizontal signal lines 22 and 23 by 0 and 21. Therefore, in the conventional solid-state imaging device, a pixel is saturated and a video signal for which contrast is not obtained is output from the other terminal, and a signal with contrast for a very wide range of incident light quantity from a separate terminal. Is obtained.

【0018】なお、本実施形態では、1本の垂直信号線
13に対して2つの負荷容量18,19を設けるとした
が、2つに限られるものではなく、3つ以上設けること
も可能である。この場合、動作スイッチおよび水平スイ
ッチについても同じ数だけ設ける必要がある。
In the present embodiment, the two load capacitors 18 and 19 are provided for one vertical signal line 13, but the number is not limited to two and three or more may be provided. is there. In this case, it is necessary to provide the same number of operation switches and horizontal switches.

【0019】また、図1の構成の固体撮像素子10にお
いては、出力信号OUT1,OUT2として、異なる行
の画素からの信号が同時に導出されることになるため、
表示や画像処理等をする場合に都合が悪い。これに対処
できるようにしたのが、本発明による撮像装置である。
Further, in the solid-state image pickup device 10 having the configuration of FIG. 1, since signals from pixels in different rows are simultaneously derived as the output signals OUT1 and OUT2,
It is not convenient for displaying and image processing. The image pickup apparatus according to the present invention can cope with this.

【0020】図3は、本発明による撮像装置の一実施形
態を示すブロック図である。図3において、固体撮像素
子10から出力される、後に走査される行の画素信号
(図1の説明では、出力信号OUT1)をFIFO(Fir
st In First Out)のN行分のラインメモリ31を通すこ
とにより、出力信号OUT1と同一の行でかつ出力信号
OUT1よりも遅れて出力される出力信号OUT2に時
間を合わせ(同時化)、その後この同時化された出力信
号OUT1,OUT2を加算器32で加算する構成の信
号処理回路30を用いる。
FIG. 3 is a block diagram showing an embodiment of the image pickup apparatus according to the present invention. In FIG. 3, a pixel signal (an output signal OUT1 in the description of FIG. 1) output from the solid-state image sensor 10 in a row to be scanned later is output to the FIFO (Fir)
By passing the line memory 31 for N rows (st In First Out), the time is adjusted (simultaneous) to the output signal OUT2 which is output in the same row as the output signal OUT1 and later than the output signal OUT1. The signal processing circuit 30 configured to add the synchronized output signals OUT1 and OUT2 by the adder 32 is used.

【0021】ここで、ラインメモリ22の容量として
は、図1の構成の場合は、(m−p)行分だけあれば良
い。このことは、図1で説明したように、蓄積時間を短
くしたφVp行について、蓄積時間の長いφVm行より
も先に走査されるように設定しておけば、メモリの容量
が少なくて済むことを意味している。何故ならば、φV
p行の蓄積時間はφVm行との行差と水平走査時間の積
で表されるため、先に走査されるφVp行の蓄積時間を
短く設定すればφVp行とφVm行との行差が少なくな
り、結果的にメモリの容量が少なくなるからである。
Here, in the case of the configuration of FIG. 1, the capacity of the line memory 22 may be (mp) rows. This means that, as described with reference to FIG. 1, if the φVp row with a short storage time is set to be scanned before the φVm row with a long storage time, the memory capacity can be reduced. Means Because φV
Since the accumulation time of the p row is represented by the product of the row difference from the φVm row and the horizontal scanning time, the row difference between the φVp row and the φVm row will be small if the accumulation time of the φVp row that is scanned first is set short. This is because the capacity of the memory is reduced as a result.

【0022】このように、後に走査される行の画素信号
であるL信号(出力信号OUT1)をラインメモリ22
に記憶し、もう一度同じ行の画素信号がS信号(出力信
号OUT2)として出力されたら、L信号とS信号を加
算して映像信号として出力することにより、図4に示す
ような入射光量対出力信号量の関係が得られる。その結
果、図4の入出力特性図から明らかなように、入射光量
R1を境に感度が変化して非線形の関係になるものの、
入射光としてのダイナミックレンジが飛躍的に拡大す
る。
In this way, the line memory 22 stores the L signal (output signal OUT1) which is the pixel signal of the row to be scanned later.
When the pixel signal of the same row is output as the S signal (output signal OUT2) again, the L signal and the S signal are added and output as a video signal, so that the incident light amount vs. output as shown in FIG. A signal quantity relationship is obtained. As a result, as is clear from the input / output characteristic diagram of FIG. 4, although the sensitivity changes at the boundary of the incident light amount R1, the relationship becomes non-linear.
The dynamic range of incident light is dramatically expanded.

【0023】ところで、どのような固体撮像素子におい
ても、画素の飽和信号量にバラツキがあることから、出
力信号OUT1と出力信号OUT2とを単純に加算する
と、図4の光量R1〜R2の範囲で画素の飽和信号量の
バラツキがそのまま映像に現れてしまう。すなわち、光
量R1〜R2の範囲では、出力信号OUT1は画素の飽
和信号量のバラツキとなるので、加算信号(OUT1+
OUT2)は出力信号OUT1の飽和信号量のバラツ
キ、即ち固定パターンノイズの上に出力信号OUT2が
重畳された非常にSN比の悪い信号となってしまう。
By the way, in any solid-state image pickup device, since the saturation signal amount of the pixel varies, if the output signal OUT1 and the output signal OUT2 are simply added, in the range of the light amounts R1 and R2 in FIG. The variation of the saturation signal amount of the pixel appears in the image as it is. That is, in the range of the light amounts R1 and R2, the output signal OUT1 has variations in the saturation signal amount of the pixel, and therefore the addition signal (OUT1 +
OUT2) becomes a signal with a very poor SN ratio in which the variation of the saturation signal amount of the output signal OUT1 is caused, that is, the output signal OUT2 is superimposed on the fixed pattern noise.

【0024】本発明による撮像装置の他の実施形態で
は、これに対処できるような構成となっている。図5は
その構成を示すブロック図であり、図中、図3と同等部
分には同一符号を付して示してある。この実施形態に係
る信号処理回路30では、上述した画素の飽和信号量の
バラツキを取り除くために、固体撮像素子10の出力信
号OUT1の出力端とラインメモリ31との間にクリッ
プ回路33を、さらに出力信号OUT2の出力端と加算
器32との間にクリップ回路34をそれぞれ挿入した構
成となっている。
In another embodiment of the image pickup apparatus according to the present invention, it is constructed so as to be able to cope with this. FIG. 5 is a block diagram showing the structure thereof. In the figure, the same parts as those in FIG. 3 are designated by the same reference numerals. In the signal processing circuit 30 according to this embodiment, a clipping circuit 33 is further provided between the output terminal of the output signal OUT1 of the solid-state imaging device 10 and the line memory 31 in order to remove the above-described variation in the saturation signal amount of the pixel. The clip circuit 34 is inserted between the output terminal of the output signal OUT2 and the adder 32.

【0025】ここに、クリップ回路33,34とは、あ
る一定以上の信号をその一定値で置き換える回路であ
り、そのある一定値としては、バラツキを持つ画素の飽
和信号量のうち最も小さい値よりも小さくとるように設
定する。なお、出力信号OUT2側にもクリップ回路3
4を挿入するとしたが、図4の入出力特性から明らかな
ように、出力信号OUT2については入射光量R2まで
は飽和レベルに達しないことから、それ以上のダイナミ
ックレンジを望まない場合には、クリップ回路34を省
略することも可能である。
Here, the clipping circuits 33 and 34 are circuits for replacing a signal of a certain level or more with the certain value, and the certain certain value is smaller than the smallest value of the saturated signal amounts of pixels having variations. Also set to take small. The clipping circuit 3 is also provided on the output signal OUT2 side.
4 is inserted, but as is clear from the input / output characteristics of FIG. 4, the output signal OUT2 does not reach the saturation level up to the incident light amount R2. It is also possible to omit the circuit 34.

【0026】図6に、クリップ回路33,34の入出力
特性を示す。かかる入出力特性を持つクリップ回路3
3,34を挿入することで、出力信号OUT1が画素の
飽和レベルに達しても、画素の飽和信号量よりも小さく
設定されたクリップレベルでクリップされるため、画素
の飽和信号量のバラツキ、即ち固定パターンノイズの影
響を受けることがなく、よってSN比の高い映像信号を
得ることができる。
FIG. 6 shows the input / output characteristics of the clip circuits 33 and 34. Clip circuit 3 having such input / output characteristics
By inserting 3, 34, even if the output signal OUT1 reaches the saturation level of the pixel, the output signal OUT1 is clipped at the clip level set to be smaller than the saturation signal amount of the pixel. It is possible to obtain a video signal with a high SN ratio without being affected by fixed pattern noise.

【0027】また、図6に示す線形の入出力特性に代え
て、図7に示す非線形の入出力特性をクリップ回路33
に持たせることで、図4の入出力特性における入射光量
R1での不自然な段差特性を解消し、その入出力特性を
滑らかにすることができる。その結果、自然な階調を持
つ映像信号を得ることができる。
Further, in place of the linear input / output characteristic shown in FIG. 6, the non-linear input / output characteristic shown in FIG.
In addition to the above, it is possible to eliminate the unnatural step characteristic at the incident light amount R1 in the input / output characteristic of FIG. 4 and smooth the input / output characteristic. As a result, a video signal having a natural gradation can be obtained.

【0028】[0028]

【発明の効果】以上説明したように、本発明による固体
撮像素子によれば、1本の垂直信号線に対して記憶手段
を複数設け、蓄積時間が異なる複数行の画素から出力さ
れる信号を垂直信号線を通して複数の記憶手段に記憶さ
せる一方、これらの記憶手段に記憶された信号を複数の
水平信号線を通して出力する構成としたことにより、画
素が飽和してコントラストの得られない映像信号の他
に、非常に広い範囲の入射光量に対してコントラストの
ある映像信号を得ることができるので、入射光量対出力
信号量のダイナミックレンジを飛躍的に拡大することが
できる。
As described above, according to the solid-state image pickup device of the present invention, a plurality of storage means are provided for one vertical signal line, and signals output from pixels in a plurality of rows having different storage times are stored. While the signals are stored in the plurality of storage means through the vertical signal lines and the signals stored in these storage means are output through the plurality of horizontal signal lines, a pixel signal is saturated and a video signal with no contrast is obtained. In addition, since it is possible to obtain a video signal having a contrast with respect to a very wide range of incident light quantity, it is possible to dramatically expand the dynamic range of the incident light quantity to the output signal quantity.

【0029】また、本発明による撮像装置によれば、蓄
積時間が異なる複数行の画素に基づく複数の出力信号を
得る固体撮像素子を用い、この固体撮像素子から出力さ
れる複数の出力信号を同時化しかつこれらを加算して映
像信号として出力する構成としたことにより、異なる行
の画素からの信号が同時に出力されるようなことはない
ため、表示や画像処理等をする場合にも支障を来すこと
のない映像信号を得ることができるとともに、入射光量
対出力信号量のダイナミックレンジを拡大することがで
きる。
Further, according to the image pickup device of the present invention, a solid-state image pickup device which obtains a plurality of output signals based on a plurality of rows of pixels having different accumulation times is used, and a plurality of output signals outputted from the solid-state image pickup device are simultaneously detected. The signals from pixels in different rows are not output at the same time because of the addition of these signals and the addition of these signals to output as a video signal.Therefore, there is a problem in displaying or image processing. It is possible to obtain a perfect video signal and expand the dynamic range of the amount of incident light versus the amount of output signal.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明による固体撮像素子の一実施形態を示す
構成図である。
FIG. 1 is a configuration diagram showing an embodiment of a solid-state image sensor according to the present invention.

【図2】本発明による固体撮像素子の入出力特性図であ
る。
FIG. 2 is an input / output characteristic diagram of the solid-state image sensor according to the present invention.

【図3】本発明による撮像装置の一実施形態を示す構成
図である。
FIG. 3 is a configuration diagram showing an embodiment of an imaging device according to the present invention.

【図4】本発明による撮像装置の入出力特性図である。FIG. 4 is an input / output characteristic diagram of the image pickup apparatus according to the present invention.

【図5】本発明による撮像装置の他の実施形態を示す構
成図である。
FIG. 5 is a configuration diagram showing another embodiment of the imaging device according to the present invention.

【図6】クリップ回路の一例の入出力特性図である。FIG. 6 is an input / output characteristic diagram of an example of a clip circuit.

【図7】クリップ回路の他の例の入出力特性図である。FIG. 7 is an input / output characteristic diagram of another example of the clip circuit.

【図8】従来例を示す構成図である。FIG. 8 is a configuration diagram showing a conventional example.

【図9】従来例の入出力特性図である。FIG. 9 is an input / output characteristic diagram of a conventional example.

【符号の説明】[Explanation of symbols]

10 固体撮像素子 11 画素トランジスタ 12 垂直選択線 13 垂直信号線 14 垂直走査回路 15 電子シャッタ走査回路 16,17 MOSトランジスタ(動作スイッチ) 18,19 負荷容量 20,21 MOSトランジスタ(水平スイッチ) 22,23 水平信号線 24 水平走査回路 25,26 出力端子 30 信号処理回路 31 ラインメモリ 32 加算器 33,34 クランプ回路 10 Solid-state image sensor 11 Pixel transistor 12 Vertical selection line 13 Vertical signal line 14 Vertical scanning circuit 15 Electronic shutter scanning circuit 16,17 MOS transistor (operation switch) 18,19 Load capacity 20,21 MOS transistor (horizontal switch) 22,23 Horizontal signal line 24 Horizontal scanning circuit 25, 26 Output terminal 30 Signal processing circuit 31 Line memory 32 Adder 33, 34 Clamp circuit

【手続補正書】[Procedure amendment]

【提出日】平成8年5月10日[Submission date] May 10, 1996

【手続補正1】[Procedure amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0013[Correction target item name] 0013

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【0013】MOSトランジスタ20,21の各ソース
電極は水平信号線22,23にそれぞれ接続され、各ゲ
ート電極は水平走査回路24の出力端に共通に接続され
ている。この水平走査回路24はシフトレジスタ等で構
成され、MOSトランジスタ20,21を導通状態に
し、負荷容量18,19の各一端を水平信号線22,2
3に接続するために、MOSトランジスタ20,21の
各ゲート電極に対して水平走査パルスφH(…,φH
n,φHn+1,…)を与える。水平信号線22,23
の各一端は、出力端子25,26にそれぞれ接続されて
いる。以上により、増幅型固体撮像素子10が構成され
ている。
The source electrodes of the MOS transistors 20 and 21 are connected to the horizontal signal lines 22 and 23, respectively, and the gate electrodes are commonly connected to the output terminal of the horizontal scanning circuit 24. The horizontal scanning circuit 24 is composed of a shift register or the like, makes the MOS transistors 20 and 21 conductive, and connects one end of each of the load capacitors 18 and 19 to the horizontal signal lines 22 and 2.
3, the horizontal scanning pulse φH (..., φH) is applied to each gate electrode of the MOS transistors 20 and 21.
n, φHn + 1, ...) Is given. Horizontal signal lines 22, 23
One end of each is connected to the output terminals 25 and 26, respectively. The amplification type solid-state imaging device 10 is configured as described above.

【手続補正2】[Procedure amendment 2]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0014[Correction target item name] 0014

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【0014】次に、上記構成の増幅型固体撮像素子10
の動作について、図10のタイミングチャートに基づい
て説明する。先ず、垂直走査期間にほぼ近い時間だけ蓄
積したφVm行の垂直選択線12の画素トランジスタ1
1を、ある水平ブランキング期間(HBLK)に垂直信
号線13から動作スイッチであるMOSトランジスタ1
6を介して読み出して負荷容量18に信号電圧として保
持する。そして、読み出しが終わったφVm行の垂直選
択線12の画素トランジスタ11については、当該画素
トランジスタ11に蓄積した信号電荷をリセットする。
なお、画素のリセットは、基板パルスφSUBが基板に
印加されることによって行われる。また、画素の蓄積時
間の制御は、電子シャッタ走査回路15によって行われ
る。
Next, the amplification type solid-state image pickup device 10 having the above structure.
The operation will be described based on the timing chart of FIG. First, the pixel transistor 1 of the vertical selection line 12 of the φVm row accumulated for a time almost close to the vertical scanning period.
1 from a vertical signal line 13 to a MOS transistor 1 which is an operation switch during a certain horizontal blanking period (HBLK).
It is read out via 6 and held as a signal voltage in the load capacitance 18. Then, with respect to the pixel transistor 11 of the vertical selection line 12 of the φVm row which has been read, the signal charge accumulated in the pixel transistor 11 is reset.
Note that the resetting of the pixels is performed by applying the substrate pulse φSUB to the substrate. The electronic shutter scanning circuit 15 controls the pixel accumulation time.

【手続補正3】[Procedure 3]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0015[Correction target item name] 0015

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【0015】次に、同じ水平ブランキング期間に例えば
1/1000秒前に一度読み出されてリセットされたφ
Vp行の垂直選択線12の画素トランジスタ11の信号
を、垂直信号線13からMOSトランジスタ17を介し
て負荷容量19に読み出して信号電圧として保持する。
読み出しが終わったφVp行の垂直選択線12の画素ト
ランジスタ11については、当該画素トランジスタ11
に蓄積した信号電荷をリセットする。すると、垂直走査
期間をいま仮に1/60秒であるとすると、負荷容量1
8,19にはそれぞれ(1/60−1/1000)秒と
1/1000秒の蓄積時間の信号が保持される。これら
の信号をそれぞれL信号、S信号と称することにする。
Next, in the same horizontal blanking period, φ read once and reset, for example, 1/1000 second before.
The signal of the pixel transistor 11 of the vertical selection line 12 of the Vp row is read from the vertical signal line 13 to the load capacitance 19 via the MOS transistor 17 and held as a signal voltage.
Regarding the pixel transistor 11 of the vertical selection line 12 of the φVp row for which reading has been completed,
The signal charge accumulated in is reset. Then, assuming that the vertical scanning period is 1/60 second, the load capacitance 1
Signals with storage times of (1 / 60-1 / 1000) seconds and 1/1000 seconds are stored in 8 and 19, respectively. These signals will be referred to as L signal and S signal, respectively.

【手続補正4】[Procedure amendment 4]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0022[Correction target item name] 0022

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【0022】このように、映像信号として後で走査され
る行の画素信号であるL信号(出力信号OUT1)をラ
インメモリ22に記憶し、もう一度同じ行の画素信号が
S信号(出力信号OUT2)として出力されたら、L信
号とS信号を加算して映像信号として出力することによ
り、図4に示すような入射光量対出力信号量の関係が得
られる。その結果、図4の入出力特性図から明らかなよ
うに、入射光量R1を境に感度が変化して非線形の関係
になるものの、入射光としてのダイナミックレンジが飛
躍的に拡大する。
In this way, the L signal (output signal OUT1) which is the pixel signal of the row to be scanned later as the video signal is stored in the line memory 22, and the pixel signal of the same row is again the S signal (output signal OUT2). Then, the L signal and the S signal are added and output as a video signal, whereby the relationship between the incident light amount and the output signal amount as shown in FIG. 4 is obtained. As a result, as is clear from the input / output characteristic diagram of FIG. 4, the sensitivity changes at the incident light amount R1 and becomes a non-linear relationship, but the dynamic range of the incident light is dramatically expanded.

【手続補正5】[Procedure Amendment 5]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】図10[Name of item to be corrected] Fig. 10

【補正方法】追加[Correction method] Added

【補正内容】[Correction contents]

【図10】本発明の動作説明のためのタイミングチャー
トである。
FIG. 10 is a timing chart for explaining the operation of the present invention.

【手続補正6】[Procedure correction 6]

【補正対象書類名】図面[Document name to be amended] Drawing

【補正対象項目名】図10[Name of item to be corrected] Fig. 10

【補正方法】追加[Correction method] Added

【補正内容】[Correction contents]

【図10】 [Figure 10]

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 行列状に配列されて入射光量に応じた信
号を出力する多数の画素と、 同一列の画素を共通に接続した垂直信号線の各々に対し
て設けられた複数の記憶手段と、 蓄積時間が異なる複数行の画素から出力される信号を垂
直信号線を通して読み出して前記複数の記憶手段に記憶
させる複数の第1のスイッチ手段と、 前記複数の記憶手段に記憶された信号を複数の水平信号
線を通して出力する複数の第2のスイッチ手段とを備え
たことを特徴とする固体撮像素子。
1. A large number of pixels arranged in a matrix and outputting a signal according to the amount of incident light, and a plurality of storage means provided for each of the vertical signal lines commonly connecting the pixels in the same column. A plurality of first switch means for reading signals output from pixels of a plurality of rows having different accumulation times through vertical signal lines and storing the signals in the plurality of storage means; and a plurality of signals stored in the plurality of storage means. And a plurality of second switch means for outputting through the horizontal signal line.
【請求項2】 画素の蓄積時間を電子シャッタを用いて
制御することを特徴とする請求項1記載の固体撮像素
子。
2. The solid-state image pickup device according to claim 1, wherein an accumulation time of pixels is controlled by using an electronic shutter.
【請求項3】 前記複数行の画素のうち映像信号として
先に走査される行の画素は、最も後に走査される行の画
素よりも蓄積時間が短く設定されたことを特徴とする請
求項1記載の固体撮像素子。
3. The pixel of the row scanned first as a video signal among the pixels of the plurality of rows is set to have a shorter accumulation time than the pixel of the row scanned last. The solid-state image sensor according to claim 1.
【請求項4】 蓄積時間が異なる複数行の画素に基づく
複数の出力信号を得る固体撮像素子と、 前記固体撮像素子からの複数の出力信号を同時化しかつ
これらを加算して映像信号として出力する信号処理回路
とを備えたことを特徴とする撮像装置。
4. A solid-state image sensor for obtaining a plurality of output signals based on pixels of a plurality of rows having different accumulation times, and a plurality of output signals from the solid-state image sensor are synchronized and added to output as a video signal. An image pickup apparatus comprising: a signal processing circuit.
【請求項5】 前記信号処理回路は、同時化した各出力
信号を線形または非線形入出力特性を有する回路を通し
た後に加算することを特徴とする請求項4記載の撮像装
置。
5. The image pickup apparatus according to claim 4, wherein the signal processing circuit adds the synchronized output signals after passing through a circuit having a linear or nonlinear input / output characteristic.
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