JP3988756B2 - Solid-state image sensor - Google Patents

Description

  The present invention relates to a solid-state imaging device, and more particularly to an XY address type solid-state imaging device capable of reading pixel information obtained by photoelectric conversion in units of pixels.

  In an amplification type solid-state imaging device which is a kind of XY address type solid-state imaging device, a pixel is configured using an active element (MOS transistor) such as a MOS structure in order to give the pixel itself an amplification function ( For example, see Patent Document 1). A conventional example of this amplification type solid-state imaging device is shown in FIG. In FIG. 9, a large number of pixel transistors 81 are arranged in a matrix, the gate electrodes of the pixel transistors 81 are connected to the vertical selection lines 82 in units of rows, the source electrodes are connected to the vertical signal lines 83 in units of columns, A power supply voltage VD is applied to each drain electrode. Each vertical selection line 82 is connected to the output end of the vertical scanner 84.

  Each vertical signal line 83 is connected to the drain electrode of an NchMOS transistor 85 which is an operation switch. The source electrode of the MOS transistor 85 is connected to one end of the load capacitor 86 and is connected to the drain electrode of the Nch MOS transistor 87 which is a horizontal switch, and an operation pulse φOP is applied to the gate electrode. The other end of the load capacitor 86 is grounded. The source electrode of the MOS transistor 87 is connected to the horizontal signal line 88, and its gate electrode is connected to the output terminal of the horizontal scanning circuit 89. One end of the horizontal signal line 88 is connected to the output terminal 90.

  In the amplification type solid-state imaging device having the above configuration, incident light is photoelectrically converted by the pixel transistor 81 into a signal charge having a charge amount corresponding to the light amount. A signal corresponding to the amount of incident light from the pixel transistor 81 is held in the load capacitor 86 via the vertical signal line 83 and the MOS transistor 85 which is an operation switch. The held signal is output to the horizontal signal line 88 through the MOS transistor 87 which is a horizontal switch controlled by the horizontal scanning circuit 89, and is further led out from the output terminal 90 through the horizontal signal line 88.

  In such an amplification type solid-state imaging device, an output signal that is almost linear with respect to the signal charge accumulated in the unit pixel by photoelectric conversion is obtained, and the dynamic range of the imaging device is determined by the amount of signal charge that can be accumulated in the unit pixel. End up. FIG. 10 is an input / output characteristic diagram showing the relationship between the incident light amount of the image sensor and the output signal amount. As is apparent from this input / output characteristic diagram, the dynamic range of the image sensor is determined by the saturation signal amount of the pixel and the noise level.

Japanese Patent Laid-Open No. 5-167928

  As described above, in the conventional amplifying solid-state imaging device, the amount of signal charge that can be stored in a unit pixel is limited depending on the size of the unit pixel. The signal of a high-brightness subject is saturated, and conversely, if the camera lens aperture is adjusted to a high-brightness subject, the signal of the low-brightness subject is buried in noise. Couldn't get.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a solid-state imaging device capable of dramatically expanding the dynamic range of incident light quantity versus output signal quantity. is there.

The solid-state imaging device according to the present invention includes a plurality of pixels arranged in a matrix and outputting a signal corresponding to the amount of incident light, and a plurality of vertical signal lines connected in common to pixels in the same column. Storage means, a plurality of first switch means for reading out signals output from pixels in a plurality of rows having different accumulation times through a vertical signal line and storing them in the plurality of storage means, and stored in the plurality of storage means A plurality of second switch means for outputting a signal through a plurality of horizontal signal lines , and among the pixels in the plurality of rows, pixels in a row having a short accumulation time are scanned before pixels in a row having a long accumulation time. It has a configuration.

According to the present invention, a plurality of storage units are provided for one vertical signal line, and signals output from a plurality of rows of pixels having different accumulation times are stored in the plurality of storage units through the vertical signal lines. Since the signal stored in the storage means is output through a plurality of horizontal signal lines, in addition to the video signal in which the pixel is saturated and the contrast cannot be obtained, the contrast of the incident light quantity in a very wide range is not obtained. Since a certain video signal can be obtained, the dynamic range of the incident light quantity versus the output signal quantity can be dramatically expanded , and among the pixels in a plurality of rows, the pixels in the short accumulation time are changed to the long accumulation time rows. By scanning before this pixel, the capacity of the memory used in the subsequent signal processing circuit can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a configuration diagram showing an embodiment of a solid-state imaging device according to the present invention. In FIG. 1, a large number of pixel transistors (in this example, NchMOS transistors are shown) 11 are arranged in a matrix, the gate electrode of each pixel transistor 11 is connected to the vertical selection line 12 in a row unit, and each source electrode is in a column unit. Are connected to the vertical signal line 13, and a power supply voltage VD is applied to each drain electrode. Each vertical selection line 12 is connected to the output terminals of the vertical scanning circuit 14 and the electronic shutter scanning circuit 15.

  The vertical scanning circuit 14 is composed of a shift register or the like, and in order to sequentially read out pixel information for each line while performing vertical scanning, a vertical selection pulse φV (..., ΦVm,..., ΦVp is applied to each vertical selection line 12. ,…)give. Similarly, the electronic shutter scanning circuit 15 is composed of a shift register or the like, and controls the pixel accumulation time for each line.

  Each vertical signal line 13 is connected to each drain electrode of, for example, two Nch MOS transistors 16 and 17 which are operation switches (first switch means). These MOS transistors 16 and 17 are formed in the same size, and operation pulses φOP1 and φOP2 are applied to their gate electrodes. The source electrodes of the MOS transistors 16 and 17 are connected to respective one ends of the two load capacitors 18 and 19 that are storage means, and the two Nch MOS transistors 20 and 21 that are horizontal switches (second switch means). Connected to each drain electrode. The other ends of the load capacitors 18 and 19 are both grounded.

  The source electrodes of the MOS transistors 20 and 21 are respectively connected to the horizontal signal lines 22 and 23, and the gate electrodes are commonly connected to the output terminal of the horizontal scanning circuit 24. The horizontal scanning circuit 24 is constituted by a shift register or the like. The MOS transistors 20 and 21 are connected to the horizontal signal lines 22 and 23 in order to make the MOS transistors 20 and 21 conductive and connect one ends of the load capacitors 18 and 19 to the horizontal signal lines 22 and 23. A horizontal scanning pulse φH (..., ΦHn, φHn + 1,...) Is applied to each gate electrode. One ends of the horizontal signal lines 22 and 23 are connected to output terminals 25 and 26, respectively. Thus, the amplification type solid-state imaging device 10 is configured.

Next, the operation of the amplification type solid-state imaging device 10 having the above configuration will be described with reference to the timing chart of FIG.
First, the pixel transistor 11 of the vertical selection line 12 in the φVm row that has been accumulated for a time substantially close to the vertical scanning period is read from the vertical signal line 13 through the MOS transistor 16 that is an operation switch during a certain horizontal blanking period, and the load capacitance is read. 18 is held as a signal voltage. Then, with respect to the pixel transistor 11 of the vertical selection line 12 in the φVm row that has been read, the signal charge accumulated in the pixel transistor 11 is reset. The pixel is reset by applying a substrate pulse φSUB to the substrate. Further, the electronic shutter scanning circuit 15 controls the pixel accumulation time.

  Next, the signal of the pixel transistor 11 of the vertical selection line 12 in the φVp row that has been read and reset once in the same horizontal blanking period, for example, 1/1000 second before, is transferred from the vertical signal line 13 through the MOS transistor 17. Read to the load capacitor 19 and hold it as a signal voltage. For the pixel transistor 11 of the vertical selection line 12 in the φVp row that has been read, the signal charge accumulated in the pixel transistor 11 is reset. Then, assuming that the vertical scanning period is 1/60 seconds, the load capacitors 18 and 19 hold signals of accumulation times of (1 / 60-1 / 1000) seconds and 1/1000 seconds, respectively. These signals will be referred to as L signal and S signal, respectively.

  The L and S signals held in the load capacitors 18 and 19 are output to the horizontal signal lines 22 and 23 through the MOS transistors 20 and 21 which are horizontal switches, and further output signals OUT1 and OUT2 through the output terminals 25 and 26. Are respectively derived to the outside. Here, the relationship between the signal amounts of the output signals OUT1 and OUT2 with respect to the amount of incident light is shown in FIG. That is, the output signal OUT1 is saturated with the incident light amount R1 equivalent to that in the conventional example, while the other output signal OUT2 is not saturated until the incident light amount R2.

  Thus, for example, two load capacitors 18 and 19 are provided for one vertical signal line 13, and signals output from pixels in a plurality of rows having different accumulation times are transmitted through the vertical signal line 13 to the MOS transistors 16 and 17. Is read out and stored in the load capacitors 18 and 19, while the signals stored in the load capacitors 18 and 19 are output through the horizontal signal lines 22 and 23 by the MOS transistors 20 and 21. Output signals OUT1 and OUT2 having different accumulation times are obtained from the element 10 simultaneously. Therefore, in a conventional solid-state imaging device, a pixel signal that is saturated and a contrast cannot be obtained is output from the other terminal, and a signal that has a contrast with respect to a very wide range of incident light quantity from a different terminal. Is obtained.

  In this embodiment, the two load capacitors 18 and 19 are provided for one vertical signal line 13, but the number is not limited to two, and three or more may be provided. In this case, it is necessary to provide the same number of operation switches and horizontal switches.

  Further, in the solid-state imaging device 10 having the configuration shown in FIG. 1, signals from pixels in different rows are derived simultaneously as the output signals OUT1 and OUT2, which is inconvenient for display and image processing. . The imaging apparatus described below can cope with this.

  FIG. 4 is a block diagram showing a configuration of an imaging apparatus using the solid-state imaging device 10 according to the present invention. In FIG. 4, pixel signals (in the description of FIG. 1, output signal OUT <b> 1 in the row to be scanned later) output from the solid-state imaging device 10 are lines for N rows of FIFO (First In First Out). By passing the memory 31, the time is synchronized (synchronized) with the output signal OUT2 that is output in the same row as the output signal OUT1 and later than the output signal OUT1, and then the synchronized output signals OUT1 and OUT2 are A signal processing circuit 30 configured to add by the adder 32 is used.

  Here, the capacity of the line memory 31 is sufficient for (mp) rows in the configuration of FIG. As described above with reference to FIG. 1, if the φVp row having a shorter accumulation time is set to be scanned before the φVm row having a longer accumulation time, the memory capacity can be reduced. Means. This is because the accumulation time of the φVp row is expressed by the product of the row difference from the φVm row and the horizontal scanning time, so if the accumulation time of the previously scanned φVp row is set short, the φVp row and φVm row This is because the line difference is reduced, resulting in a reduction in memory capacity.

  In this way, the L signal (output signal OUT1) which is a pixel signal of a row to be scanned later is stored in the line memory 31 as a video signal, and the pixel signal of the same row is output again as an S signal (output signal OUT2). Then, by adding the L signal and the S signal and outputting as a video signal, the relationship between the incident light quantity and the output signal quantity as shown in FIG. 5 is obtained. As a result, as apparent from the input / output characteristic diagram of FIG. 5, although the sensitivity changes with the incident light quantity R1 as a boundary and becomes a non-linear relationship, the dynamic range as incident light is dramatically expanded.

  By the way, in any solid-state imaging device, there is a variation in the saturation signal amount of the pixel. Therefore, when the output signal OUT1 and the output signal OUT2 are simply added, the saturation of the pixel is within the range of the light amounts R1 to R2 in FIG. The variation in signal amount appears in the video as it is. That is, in the range of the light amounts R1 to R2, the output signal OUT1 has a variation in the saturation signal amount of the pixel. Therefore, the addition signal (OUT1 + OUT2) has a variation in the saturation signal amount of the output signal OUT1, that is, the output signal on the fixed pattern noise. This results in a signal with a very poor SN ratio on which OUT2 is superimposed.

  Other imaging apparatuses are configured to cope with this. FIG. 6 is a block diagram showing the configuration. In FIG. 6, the same parts as those in FIG. In the signal processing circuit 30 in this other image pickup apparatus, in order to remove the above-described variation in the saturation signal amount of the pixel, a clip circuit 33 is provided between the output end of the output signal OUT1 of the solid-state image pickup device 10 and the line memory 31. Further, a clip circuit 34 is inserted between the output terminal of the output signal OUT2 and the adder 32.

  Here, the clipping circuits 33 and 34 are circuits that replace a signal having a certain value or more with the certain value, and the certain value is smaller than the smallest value among the saturation signal amounts of the pixels having variations. Set to take. Although the clip circuit 34 is also inserted on the output signal OUT2 side, as is clear from the input / output characteristics of FIG. 5, the output signal OUT2 does not reach the saturation level until the incident light amount R2, and therefore, more than that. If the dynamic range is not desired, the clip circuit 34 can be omitted.

  FIG. 7 shows input / output characteristics of the clip circuits 33 and 34. By inserting the clipping circuits 33 and 34 having such input / output characteristics, even if the output signal OUT1 reaches the saturation level of the pixel, the clipping is performed at the clip level set smaller than the saturation signal amount of the pixel. Therefore, it is possible to obtain a video signal having a high S / N ratio.

  Further, by providing the clip circuit 33 with the nonlinear input / output characteristics shown in FIG. 8 instead of the linear input / output characteristics shown in FIG. 7, an unnatural step in the incident light quantity R1 in the input / output characteristics of FIG. The characteristics can be eliminated and the input / output characteristics can be smoothed. As a result, a video signal having a natural gradation can be obtained.

It is a block diagram which shows one Embodiment of the solid-state image sensor by this invention. 3 is a timing chart for explaining the operation of the present invention. It is an input-output characteristic figure of the solid-state image sensor by this invention. 1 is a block diagram illustrating a configuration of an imaging apparatus using a solid-state imaging device according to the present invention. It is an input-output characteristic figure of an imaging device. It is a block diagram which shows the other structure of an imaging device. It is an input-output characteristic figure of an example of a clip circuit. It is an input-output characteristic figure of the other example of a clip circuit. It is a block diagram which shows a prior art example. It is an input-output characteristic figure of a prior art example.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Solid-state image sensor, 11 ... Pixel transistor, 12 ... Vertical selection line, 13 ... Vertical signal line, 14 ... Vertical scanning circuit, 15 ... Electronic shutter scanning circuit, 16, 17 ... MOS transistor (operation switch), 18, 19 ... Load capacity, 20, 21 ... MOS transistor (horizontal switch), 22,23 ... Horizontal signal line, 24 ... Horizontal scanning circuit, 25,26 ... Output terminal, 30 ... Signal processing circuit, 31 ... Line memory, 32 ... Addition , 33, 34 ... Clamp circuit

Claims (2)

A number of pixels arranged in a matrix and outputting a signal corresponding to the amount of incident light;
A plurality of storage means provided for each of the vertical signal lines in which pixels in the same column are connected in common;
A plurality of first switch means for reading out signals output from pixels in a plurality of rows having different accumulation times through a vertical signal line and storing the signals in the plurality of storage means;
A plurality of second switch means for outputting signals stored in the plurality of storage means through a plurality of horizontal signal lines ;
A solid-state imaging device, wherein pixels in a row having a short accumulation time among the pixels in the plurality of rows are scanned before pixels in a row having a long accumulation time . The solid-state imaging device according to claim 1, wherein the pixel accumulation time is controlled using an electronic shutter.

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