JP2004357329A - Solid-state imaging element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem that the extension of a dynamic range of an incident luminous quantity versus output signal quantity has a limit because of a limit of a signal electric charge amount storable in a unit pixel. <P>SOLUTION: For example, two load capacitors 18, 19 are provided to one vertical signal line 13, MOS transistors 16, 17 acting like operation switches read signals outputted from a plurality of rows of pixels whose storage time differs from each other through the vertical signal line 13 and stored in the load capacitors 18, 19, and the signals stored in the load capacitors 18, 19 are introduced from output terminals 25, 26 by MOS transistors 20, 21 acting like horizontal switches through horizontal signal lines 22, 23. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device, and more particularly, to an XY address type solid-state imaging device capable of reading out pixel information obtained by photoelectric conversion in pixel units.

  In an amplification type solid-state imaging device, which is a type of XY address type solid-state imaging device, a pixel is configured using an active device (MOS transistor) such as a MOS structure in order to give the pixel itself an amplification function ( For example, see Patent Document 1). FIG. 9 shows a conventional example of this amplification type solid-state imaging device. In FIG. 9, a large number of pixel transistors 81 are arranged in rows and columns, the gate electrode of each pixel transistor 81 is connected to a vertical selection line 82 in row units, and each source electrode is connected to a vertical signal line 83 in column units. A power supply voltage VD is applied to each drain electrode. Each vertical selection line 82 is connected to an output terminal of a vertical scanner 84.

  Each vertical signal line 83 is connected to a drain electrode of an NchMOS transistor 85 as an operation switch. The source electrode of the MOS transistor 85 is connected to one end of the load capacitor 86, and is connected to the drain electrode of an NchMOS transistor 87 which is a horizontal switch, and an operation pulse φOP is applied to its gate electrode. The other end of the load capacitance 86 is grounded. The source electrode of the MOS transistor 87 is connected to the horizontal signal line 88, and the gate electrode is connected to the output terminal of the horizontal scanning circuit 89. One end of the horizontal signal line 88 is connected to the output terminal 90.

  In the amplification type solid-state imaging device having the above configuration, the incident light is photoelectrically converted by the pixel transistor 81 into a signal charge having a charge amount corresponding to the light amount. A signal corresponding to the amount of incident light from the pixel transistor 81 is held in the load capacitance 86 via the vertical signal line 83 and the MOS transistor 85 as an operation switch. The held signal is output to a horizontal signal line 88 via a MOS transistor 87 which is a horizontal switch controlled by a horizontal scanning circuit 89, and is further led out from an output terminal 90 through the horizontal signal line 88.

  In such an amplification type solid-state imaging device, an output signal that is substantially linear with respect to the signal charge accumulated in the unit pixel by the photoelectric conversion is obtained, and the dynamic range of the imaging device is determined by the amount of signal charge that can be accumulated in the unit pixel. Would. FIG. 10 is an input / output characteristic diagram showing the relationship between the amount of incident light and the amount of output signal of the image sensor. As is apparent from the input / output characteristic diagram, the dynamic range of the image sensor is determined by the saturation signal amount and the noise level of the pixel.

JP-A-5-167928

  As described above, in the conventional amplification-type solid-state imaging device, the signal charge amount that can be stored in a unit pixel is limited according to the size of the unit pixel. The signal of a high-brightness subject is saturated, and conversely, if the aperture of the camera lens is adjusted to a high-brightness subject, the signal of a low-brightness subject will be buried in noise. I couldn't get it.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a solid-state imaging device capable of dramatically expanding a dynamic range of an incident light amount versus an output signal amount. is there.

  The solid-state imaging device according to the present invention includes a plurality of pixels arranged in a matrix and outputting signals according to the amount of incident light, and a plurality of pixels provided for each of the vertical signal lines commonly connected to the pixels in the same column. Storage means, a plurality of first switch means for reading out signals output from a plurality of rows of pixels having different accumulation times through a vertical signal line and storing the signals in the plurality of storage means, and a plurality of first switch means stored in the plurality of storage means. A plurality of second switch means for outputting a signal through a plurality of horizontal signal lines.

  According to the present invention, a plurality of storage means are provided for one vertical signal line, and signals output from a plurality of rows of pixels having different accumulation times are stored in the plurality of storage means through the vertical signal lines. By outputting the signal stored in the storage means through a plurality of horizontal signal lines, in addition to a video signal in which a pixel is saturated and a contrast cannot be obtained, a contrast of a very wide range of incident light amount can be obtained. Since a certain video signal can be obtained, the dynamic range of the amount of incident light versus the amount of output signal can be greatly expanded.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a configuration diagram showing one embodiment of a solid-state imaging device according to the present invention. In FIG. 1, a large number of pixel transistors (in this example, NchMOS transistors) 11 are arranged in rows and columns, the gate electrode of each pixel transistor 11 is connected to a vertical selection line 12 in a row unit, and each source electrode is connected in a column unit. Are connected to the vertical signal line 13, and a power supply voltage VD is applied to each drain electrode. Each vertical selection line 12 is connected to output terminals of a vertical scanning circuit 14 and an electronic shutter scanning circuit 15.

  The vertical scanning circuit 14 is composed of a shift register or the like. In order to sequentially read out pixel information for each line while performing vertical scanning, a vertical selection pulse φV (..., ΦVm,. ,…)give. The electronic shutter scanning circuit 15 is also formed of a shift register or the like, and controls the pixel accumulation time for each line.

  Each vertical signal line 13 is connected to each drain electrode of, for example, two NchMOS transistors 16 and 17 which are operation switches (first switch means). These MOS transistors 16 and 17 are formed in the same size, and operation pulses φOP1 and φOP2 are applied to their respective gate electrodes. Each source electrode of the MOS transistors 16 and 17 is connected to one end of each of two load capacitors 18 and 19 as storage means, and is connected to two NchMOS transistors 20 and 21 as horizontal switches (second switch means). It is connected to each drain electrode. The other ends of the load capacitors 18 and 19 are both grounded.

  The source electrodes of the MOS transistors 20 and 21 are connected to horizontal signal lines 22 and 23, respectively, and the gate electrodes are commonly connected to the output terminal of the horizontal scanning circuit 24. The horizontal scanning circuit 24 is composed of a shift register or the like, and turns on the MOS transistors 20 and 21 to connect the one ends of the load capacitors 18 and 19 to the horizontal signal lines 22 and 23. A horizontal scanning pulse φH (..., ΦHn, φHn + 1,...) Is applied to each gate electrode. One ends of the horizontal signal lines 22 and 23 are connected to output terminals 25 and 26, respectively. Thus, the amplification type solid-state imaging device 10 is configured.

Next, the operation of the amplification type solid-state imaging device 10 having the above configuration will be described with reference to the timing chart of FIG.
First, the pixel transistors 11 of the vertical selection line 12 of the φVm row accumulated for a time almost close to the vertical scanning period are read out from the vertical signal line 13 via the MOS transistor 16 which is an operation switch during a certain horizontal blanking period, and the load capacitance is read. 18 as a signal voltage. Then, for the pixel transistor 11 of the vertical selection line 12 of the φVm row from which the reading has been completed, the signal charges accumulated in the pixel transistor 11 are reset. The reset of the pixel is performed by applying the substrate pulse φSUB to the substrate. The control of the pixel accumulation time is performed by the electronic shutter scanning circuit 15.

  Next, in the same horizontal blanking period, for example, the signal of the pixel transistor 11 of the vertical selection line 12 of the φVp row that has been read and reset once 1/1000 second ago is sent from the vertical signal line 13 through the MOS transistor 17. The data is read out to the load capacitance 19 and held as a signal voltage. For the pixel transistor 11 of the vertical selection line 12 in the φVp row from which reading has been completed, the signal charges accumulated in the pixel transistor 11 are reset. Then, assuming that the vertical scanning period is 1/60 second, signals of accumulation times of (1 / 60-1 / 1000) second and 1/1000 second are held in the load capacitors 18 and 19, respectively. These signals will be referred to as an L signal and an S signal, respectively.

  The L and S signals held in the load capacitors 18 and 19 are output to horizontal signal lines 22 and 23 via MOS transistors 20 and 21 as horizontal switches, and further output signals OUT1 and OUT2 through output terminals 25 and 26. Respectively. FIG. 3 shows the relationship between the amount of incident light and the amount of each of the output signals OUT1 and OUT2. That is, the output signal OUT1 is saturated at the incident light amount R1 equivalent to that of the conventional example, while the other output signal OUT2 is not saturated up to the incident light amount R2.

  Thus, for example, two load capacitors 18 and 19 are provided for one vertical signal line 13, and signals output from a plurality of rows of pixels having different storage times are passed through the vertical signal line 13 to the MOS transistors 16 and 17. In this configuration, the signals stored in the load capacitors 18 and 19 are stored in the load capacitors 18 and 19, while the signals stored in the load capacitors 18 and 19 are output through the horizontal signal lines 22 and 23 by the MOS transistors 20 and 21. Output signals OUT1 and OUT2 having different accumulation times are simultaneously obtained from the element 10. Therefore, the conventional solid-state imaging device outputs a video signal from which a pixel is saturated and a contrast cannot be obtained from the other terminal, and a signal having a contrast with respect to an incident light amount in a very wide range from different terminals. Is obtained.

  In the present embodiment, two load capacitors 18 and 19 are provided for one vertical signal line 13, but the number is not limited to two, and three or more capacitors can be provided. In this case, it is necessary to provide the same number of operation switches and horizontal switches.

  In addition, in the solid-state imaging device 10 having the configuration shown in FIG. 1, since signals from pixels in different rows are derived simultaneously as the output signals OUT1 and OUT2, it is not convenient to perform display or image processing. . The imaging device described below can deal with this.

  FIG. 4 is a block diagram showing a configuration of an imaging device using the solid-state imaging device 10 according to the present invention. In FIG. 4, a pixel signal (output signal OUT1 in the description of FIG. 1) of a row which is output later from the solid-state image sensor 10 and is scanned as a video signal is converted into a line for N rows of FIFO (First In First Out). By passing the signal through the memory 31, the output signal OUT2 is output in the same row as the output signal OUT1 and is delayed (synchronized) with the output signal OUT1. A signal processing circuit 30 configured to add by an adder 32 is used.

  Here, the capacity of the line memory 31 only needs to be (mp) rows in the configuration of FIG. This is because, as described with reference to FIG. 1, the memory capacity can be reduced by setting the φVp row with the shorter storage time to be scanned before the φVm row with the longer storage time. Means Because the storage time of the φVp row is represented by the product of the row difference from the φVm row and the horizontal scanning time, if the storage time of the previously scanned φVp row is set to be short, the storage time between the φVp row and the φVm row is reduced. This is because the line difference is reduced, and as a result, the memory capacity is reduced.

  As described above, the L signal (output signal OUT1), which is a pixel signal of a row to be scanned later as a video signal, is stored in the line memory 31, and the pixel signal of the same row is output again as an S signal (output signal OUT2). Then, the relationship between the incident light amount and the output signal amount as shown in FIG. 5 is obtained by adding the L signal and the S signal and outputting the added signal as a video signal. As a result, as is apparent from the input / output characteristic diagram of FIG. 5, although the sensitivity changes at the boundary of the incident light amount R1 and a non-linear relationship is established, the dynamic range of the incident light is greatly expanded.

  By the way, in any solid-state imaging device, since the saturation signal amount of the pixel varies, simply adding the output signal OUT1 and the output signal OUT2 causes the saturation of the pixel in the range of the light amount R1 to R2 in FIG. The variation in the signal amount appears in the video as it is. That is, in the range of the light amounts R1 to R2, the output signal OUT1 has a variation in the saturation signal amount of the pixel. Therefore, the addition signal (OUT1 + OUT2) has a variation in the saturation signal amount of the output signal OUT1, that is, the output signal OUT1 OUT2 is superimposed on the signal having a very low SN ratio.

  Other imaging devices are configured to cope with this. FIG. 6 is a block diagram showing the configuration, and in the figure, the same parts as those in FIG. 4 are denoted by the same reference numerals. In the signal processing circuit 30 of this other imaging device, in order to remove the above-mentioned variation in the amount of saturation signal of the pixel, a clipping circuit 33 is provided between the output terminal of the output signal OUT1 of the solid-state imaging device 10 and the line memory 31. Further, a clip circuit 34 is inserted between the output terminal of the output signal OUT2 and the adder 32.

  Here, the clipping circuits 33 and 34 are circuits for replacing a signal having a certain value or more with the certain value, and the certain value is smaller than the smallest value among the saturation signal amounts of the pixels having the variation. Set to take. Although the clipping circuit 34 is also inserted on the output signal OUT2 side, as is apparent from the input / output characteristics of FIG. 5, the output signal OUT2 does not reach the saturation level up to the incident light amount R2. If a dynamic range is not desired, the clipping circuit 34 can be omitted.

  FIG. 7 shows the input / output characteristics of the clip circuits 33 and 34. By inserting the clip circuits 33 and 34 having such input / output characteristics, even if the output signal OUT1 reaches the saturation level of the pixel, the output signal OUT1 is clipped at the clip level set smaller than the saturation signal amount of the pixel. , Which is not affected by the fixed pattern noise, and thus a video signal having a high SN ratio can be obtained.

  Further, by providing the clipping circuit 33 with the non-linear input / output characteristics shown in FIG. 8 instead of the linear input / output characteristics shown in FIG. 7, an unnatural step at the incident light amount R1 in the input / output characteristics shown in FIG. The characteristics can be eliminated and the input / output characteristics can be smoothed. As a result, a video signal having a natural gradation can be obtained.

1 is a configuration diagram illustrating an embodiment of a solid-state imaging device according to the present invention. 5 is a timing chart for explaining the operation of the present invention. FIG. 3 is an input / output characteristic diagram of the solid-state imaging device according to the present invention. 1 is a block diagram illustrating a configuration of an imaging device using a solid-state imaging device according to the present invention. FIG. 3 is an input / output characteristic diagram of the imaging device. It is a block diagram showing other composition of an imaging device. FIG. 3 is an input / output characteristic diagram of an example of a clip circuit. FIG. 11 is an input / output characteristic diagram of another example of the clip circuit. FIG. 9 is a configuration diagram showing a conventional example. FIG. 11 is an input / output characteristic diagram of a conventional example.

Explanation of reference numerals

  DESCRIPTION OF SYMBOLS 10 ... Solid-state image sensor, 11 ... Pixel transistor, 12 ... Vertical selection line, 13 ... Vertical signal line, 14 ... Vertical scanning circuit, 15 ... Electronic shutter scanning circuit, 16, 17 ... MOS transistor (operation switch), 18, 19 ... Load capacitance, 20, 21 ... MOS transistor (horizontal switch), 22, 23 ... horizontal signal line, 24 ... horizontal scanning circuit, 25,26 ... output terminal, 30 ... signal processing circuit, 31 ... line memory, 32 ... addition , 33, 34… Clamp circuit

Claims (3)

A large number of pixels arranged in a matrix and outputting signals according to the amount of incident light,
A plurality of storage means provided for each of the vertical signal lines commonly connecting the pixels of the same column,
A plurality of first switch means for reading out signals output from a plurality of rows of pixels having different accumulation times through a vertical signal line and storing the signals in the plurality of storage means;
And a plurality of second switch means for outputting the signals stored in the plurality of storage means through a plurality of horizontal signal lines. The solid-state imaging device according to claim 1, wherein an accumulation time of the pixel is controlled using an electronic shutter. The solid-state imaging device according to claim 1, wherein, among the pixels in the plurality of rows, a pixel in a row that is scanned first as a video signal has a shorter accumulation time than a pixel in a row that is scanned last. .

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