JP2021022921A - Imaging element, imaging apparatus, and control method - Google Patents

Abstract

To provide an imaging element which can timely achieve a wide dynamic range in AD conversion and high resolution precision.SOLUTION: An imaging element has: a plurality of pixels arranged in a matrix, each having an FD part for converting electric charges of signals transferred from a photoelectric conversion part into a voltage and an FD expansion part that is connected to the FD part and functions as an expansion capacity of the FD part by being set to an ON state; and a plurality of column signal processing parts that are commonly connected to a plurality of pixel columns each including the plurality of pixels arranged in a column direction and perform AD conversion of pixel signals Vsig supplied from the pixels. The plurality of column signal processing parts start AD conversion of high-gain pixel signals VsH when the FD expansion part is in an OFF state and AD conversion of low-gain pixel signals VsL when the FD expansion part is in an ON state in parallel.SELECTED DRAWING: Figure 8

Description

The present invention relates to an image pickup element having a plurality of pixels arranged in a matrix, an image pickup device having an image pickup element, and a control method of the image pickup element.

In recent years, imaging devices such as digital still cameras and digital video cameras that acquire captured images by capturing a subject image using an image sensor have been widely used.

As an image pickup device used in the above image pickup apparatus, a CMOS (Complementary Metal Oxide Semiconductor) type image sensor (hereinafter, CMOS sensor) that reads a pixel signal from each pixel by an XY address method is exemplified. The CMOS sensor has advantages such as random access to the pixel signal, high-speed reading of the pixel signal, high sensitivity and low power consumption, and the like.

Generally, the pixel circuit of a CMOS sensor converts a charge signal from a photodiode, which is a photoelectric conversion element, into a potential signal of a vertical signal line by a source follower circuit in the pixel circuit and outputs the signal. When reading a signal, pixels are sequentially selected row by row, and the pixel signals in each column in the selected row are analog-digitally converted (hereinafter referred to as AD conversion) in parallel and digitized. A pixel signal is output.

For the pixel circuit of the CMOS sensor, for example, a single slope type AD conversion circuit is adopted. The above AD conversion circuit includes a comparator and a counter for comparing a ramp wave-shaped reference signal and a pixel signal that change in time series. The pixel signal is AD-converted based on the comparative elapsed time corresponding to the slope change of the lamp wave counted by the clock of the counter (for example, Patent Document 1).

In the AD conversion method as described above, the gentler the displacement slope (rate of change) of the reference signal, the smaller the displacement width per count, so that the quantization error is reduced and the resolution accuracy of the AD conversion is improved. To do. The above improvement in accuracy is particularly remarkable in AD conversion for a pixel signal with low illuminance.

On the other hand, under the condition that the number of counts executed by the counter is constant, the displacement amount (difference between the maximum value and the minimum value) of the reference signal becomes smaller as the displacement slope of the reference signal is made gentler. The imaging region (pixel signal) tends to be saturated. That is, the gentler the displacement slope of the reference signal, the narrower the dynamic range at the time of imaging.

Here, if the number of counts is increased in order to widen the dynamic range, the time for which the AD conversion is executed becomes long, so that the frame rate decreases.

Therefore, a technique has been proposed in which a charge signal from a photodiode is AD-converted by switching between two types of gains according to the ISO sensitivity (for example, Patent Document 2).

Japanese Unexamined Patent Publication No. 2005-323331 Japanese Unexamined Patent Publication No. 2015-226161

According to the technique of Patent Document 2 in which either low gain or high gain is used in one shooting, it takes twice as long to acquire two types of image signals, so that the frame rate is high. There is a problem of decreasing. In addition, when the dynamic range expansion processing is executed using the image signals obtained by low gain shooting and high gain shooting, there is also a problem that the image of a moving subject is blurred due to the difference in shooting time.

In view of the above circumstances, an object of the present invention is to provide an image pickup device, an image pickup device, and a control method capable of timely realizing a wide dynamic range and high resolution accuracy in AD conversion.

In order to achieve the above object, the image pickup device of the present invention is connected to an FD unit that converts the charge of the signal transferred from the photoelectric conversion unit into a voltage and the FD unit, and is set to the ON state. The FD expansion unit that functions as the expansion capacity of the FD unit is common to a plurality of pixels arranged in a matrix, each of which includes the FD expansion unit, and a plurality of pixel sequences each including the plurality of the pixels arranged in the column direction. An image pickup element including a plurality of column signal processing units that are connected to each other and AD-convert the pixel signals supplied from the pixels, and each of the column signal processing units determines that the pixel voltage of the pixel signal is a pixel voltage. A comparator for comparing with a voltage is provided, and when the pixel voltage is smaller than the determination voltage, the first AD conversion is executed for the high gain pixel signal which is the pixel signal when the FD extension unit is in the off state. When the pixel voltage is larger than the determination voltage, the second AD conversion is executed for the low gain pixel signal which is the pixel signal when the FD expansion unit is on, and the plurality of column signal processing units perform the second AD conversion. , The first AD conversion and the second AD conversion are started in parallel.

Further, another imaging element of the present invention is connected to an FD unit that converts the charge of the signal transferred from the photoelectric conversion unit into a voltage, and is connected to the FD unit and is set to an ON state to expand the FD unit. An FD expansion unit that functions as a capacitance is commonly connected to a plurality of pixels arranged in a matrix, each of which includes a plurality of pixels arranged in a row direction, and a plurality of pixel rows each including the plurality of pixels arranged in a row direction. An imaging element including a vertical scanning unit that controls the operation of pixels, the vertical scanning unit can switch between an on state and an off state of the FD expansion unit, and the FD expansion unit is off. It is characterized in that a first read operation for reading a high gain pixel signal from the pixel in a state and a second read operation for reading a low gain pixel signal from the pixel in which the FD extension unit is on are executed. ..

Further, another image pickup device of the present invention has an FD unit that converts the charge of the signal transferred from the photoelectric conversion unit into a voltage, and an FD connection unit and an FD extension unit that are connected to the FD unit as a capacitance. A plurality of pixels arranged in a matrix and a vertical scanning unit which is commonly connected to a plurality of pixel rows including each of the plurality of pixels arranged in the row direction and controls the operation of the pixels. The image sensor is provided, and the vertical scanning unit can switch between an on state and an off state of the FD connection unit, and reads a high gain pixel signal from the pixel in which the FD connection unit is in the off state. It is characterized in that the first read operation and the second read operation of reading a low gain pixel signal from the pixel in which the FD connection portion is on are executed.

Further, another imaging element of the present invention has an FD unit that converts the charge of the signal transferred from the photoelectric conversion unit into a voltage, and an FD connection unit and an FD extension unit that are connected to the FD unit as a capacitance. A plurality of pixels arranged in a matrix and a plurality of the pixels arranged in the column direction are commonly connected to a plurality of pixel sequences including each, and the pixel signals supplied from the pixels are converted to AD. An imaging element including a plurality of row signal processing units, each of which includes a comparator for comparing the pixel voltage of the pixel signal with the determination voltage, and the pixel voltage determines the determination. When the voltage is smaller than the voltage, the first AD conversion is executed on the high gain pixel signal which is the pixel signal when the FD connection portion is in the off state, and when the pixel voltage is larger than the determination voltage, the FD connection is performed. The second AD conversion is executed for the low gain pixel signal which is the pixel signal when the unit is on, and the plurality of column signal processing units start the first AD conversion and the second AD conversion in parallel. It is characterized by doing.

According to the present invention, a wide dynamic range and high resolution accuracy in AD conversion can be realized in a timely manner.

It is a block diagram which shows the structure of the image pickup apparatus which concerns on 1st Embodiment of this invention. It is a block diagram which shows the structure of the image pickup device which concerns on 1st Embodiment of this invention. It is a circuit diagram which shows the circuit structure of the pixel which concerns on 1st Embodiment of this invention. It is a circuit diagram which shows the circuit structure of the column signal processing part which concerns on 1st Embodiment of this invention. It is a timing chart which shows the photographing operation which the image pickup apparatus which concerns on 1st Embodiment of this invention performs. It is a timing chart which shows the operation of the pixel in the image sensor which concerns on 1st Embodiment of this invention. It is a schematic explanatory drawing of the pixel reading operation in the image sensor which concerns on 1st Embodiment of this invention. It is a timing chart about the column signal processing part which concerns on 1st Embodiment of this invention. It is explanatory drawing of the determination operation performed by the column signal processing unit which concerns on 1st Embodiment of this invention. It is a circuit diagram which shows the circuit structure of the column signal processing part which concerns on the modification of 1st Embodiment of this invention. It is a circuit diagram which shows the circuit structure of the pixel which concerns on 2nd Embodiment of this invention. It is a schematic explanatory drawing of the pixel reading operation in the image sensor which concerns on 2nd Embodiment of this invention. This is a part of a timing chart showing the operation of pixels in the image sensor according to the modified example of the second embodiment of the present invention. It is a part of the schematic explanatory drawing of the pixel reading operation in the image pickup device which concerns on the modification of the 2nd Embodiment of this invention. It is a circuit diagram which shows the circuit structure of the pixel which concerns on 3rd Embodiment of this invention. It is a timing chart about the column signal processing part which concerns on 3rd Embodiment of this invention. It is a part of the schematic explanatory drawing of the pixel reading operation in the image pickup device which concerns on the modification of the 3rd Embodiment of this invention. It is a circuit diagram which shows the circuit structure of the pixel which concerns on 4th Embodiment of this invention. It is a circuit diagram which shows the circuit structure of the column signal processing part which concerns on 4th Embodiment of this invention. It is a timing chart which shows the operation of the pixel in the image sensor which concerns on 4th Embodiment of this invention. It is a schematic explanatory drawing of the pixel reading operation in the image sensor which concerns on 4th Embodiment of this invention. It is a supplementary explanatory view of the pixel reading operation shown in FIG. It is a timing chart about the column signal processing part which concerns on 4th Embodiment of this invention. It is a circuit diagram which shows the circuit structure of the column signal processing part which concerns on 5th Embodiment of this invention. It is a timing chart about the column signal processing part which concerns on 5th Embodiment of this invention. It is explanatory drawing of the determination operation performed by the column signal processing unit which concerns on 5th Embodiment of this invention. It is a circuit diagram which shows the circuit structure of the column signal processing part which concerns on the modification of 5th Embodiment of this invention. It is a circuit diagram which shows the circuit structure of the pixel which concerns on 6th Embodiment of this invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Each of the embodiments described below is merely an example of a configuration in which the present invention can be realized. Each of the following embodiments can be appropriately modified or changed according to the configuration of the apparatus to which the present invention is applied and various conditions. Therefore, the scope of the present invention is not limited by the configurations described in the following embodiments. For example, a configuration in which a plurality of configurations described in the embodiment are combined can be adopted as long as there is no mutual contradiction.

<First Embodiment>
The first embodiment of the present invention will be described with reference to FIGS. 1 to 9. Generally, the image sensor 1 according to the first embodiment has a pixel including a floating diffusion unit (hereinafter, FD unit) that converts charge voltage and an FD extension unit FDext that adjusts the gain of charge voltage conversion. It has an element 12. By using the image sensor 12 as described above, the image sensor 1 can realize a wide dynamic range and high resolution accuracy in one shooting.

The imaging device 1 of the present embodiment can be applied to various electronic camera devices such as a digital still camera, a digital video camera, an industrial camera, and a medical camera. It is also possible to apply the image pickup device 1 of the present embodiment to various information processing devices having an image pickup function such as a smartphone and a tablet terminal. The same applies to other embodiments.

FIG. 1 is a block diagram showing a configuration of an image pickup apparatus 1 according to a first embodiment of the present invention. The image pickup apparatus 1 includes an image pickup optical system 11, an image pickup element 12, a signal processing unit 13, a compression / expansion unit 14, a synchronization control unit 15, an operation unit 16, an image display unit 17, and an image recording unit 18.

The image pickup optical system 11 is an optical lens barrel used for image pickup, and has a plurality of lens groups for forming a subject on the image pickup element 12, a lens drive mechanism for zooming and focusing, a mechanical shutter mechanism, an aperture mechanism, and the like. Has an element. The movable portion of the imaging optical system 11 is driven based on the control signal transmitted from the synchronous control unit 15.

The image sensor 12 is an XY address type CMOS sensor capable of reading out an image signal for each pixel. The image sensor 12 performs imaging operations such as exposure, signal reading, and pixel reset according to the control signal transmitted from the synchronization control unit 15. Further, the image sensor 12 converts an image signal into analog-digital by an analog-digital conversion circuit (hereinafter referred to as an AD conversion circuit), and outputs the digitized image signal to the signal processing unit 13.

Under the control of the synchronous control unit 15, the signal processing unit 13 performs signal processing such as white balance adjustment, color correction, and gamma correction on the digitized image signal input from the image sensor 12. In addition, the signal processing unit 13 detects control information such as AF (Auto Focus) and AE (Auto Exposure). The signal-processed image signal and the detected control information are output from the signal processing unit 13 to the synchronization control unit 15.

Under the control of the synchronization control unit 15, the compression / expansion unit 14 compresses and encodes the image signal signal-processed by the signal processing unit 13, and expands the coded data of the still image supplied from the synchronization control unit 15. Perform the decryption process. The compression / decompression unit 14 may execute the compression coding / decompression / decoding process of the moving image.

The synchronization control unit 15 is, for example, a microcontroller including elements such as a CPU (Central Processing Unit), a ROM (Read Only Memory), and a RAM (Random Access Memory). The synchronous control unit 15 comprehensively controls each unit of the image pickup apparatus 1 by executing the program stored in the ROM or the like.

The operation unit 16 has, for example, various operation keys such as a shutter release button, a lever, a dial, and the like, and outputs a control signal corresponding to an input operation from the user to the synchronous control unit 15.

The image display unit 17 includes a display device such as a liquid crystal display (LCD) and a corresponding interface circuit. The image display unit 17 generates a display image signal based on the image signal supplied from the synchronization control unit 15, and supplies the generated display image signal to the display device to display an image.

The image recording unit 18 uses, for example, an image signal compressed and encoded by the compression / decompression unit 14 and supplied from the synchronization control unit 15 to a connected portable recording medium (semiconductor memory or the like) as an image data file. Record. Further, the image recording unit 18 reads out the designated data based on the control signal from the synchronization control unit 15 and outputs the data to the synchronization control unit 15.

Next, the basic operation of the image pickup apparatus 1 in the present embodiment will be described. First, the still image recording operation will be described. Before capturing a still image, the image sensor 12 sequentially supplies an image signal by photoelectric conversion to the signal processing unit 13. The signal processing unit 13 performs signal processing on the image signal supplied from the image sensor 12. The signal processing unit 13 supplies the signal-processed image signal as a camera-through image signal to the image display unit 17 via the synchronization control unit 15. The image display unit 17 displays a camera-through image based on the supplied signal. The user can adjust the angle of view by looking at the displayed camera-through image.

As described above, the image information that can be output to the image display unit 17 or the like is acquired by the cooperation between the image sensor 12 and the signal processing unit 13.

When the shutter release button of the operation unit 16 is pressed while the camera-through image is displayed by the image display unit 17, the synchronization control unit 15 controls the image sensor 12 to signal an image signal for one frame. It is taken into the processing unit 13. The signal processing unit 13 performs signal processing on the image signal for one frame captured from the image sensor 12, and supplies the image signal after the signal processing to the compression / decompression unit 14. The compression / decompression unit 14 compresses and encodes the supplied image signal after signal processing to generate coded data, and supplies the coded data to the image recording unit 18 via the synchronization control unit 15. The image recording unit 18 records the coded data corresponding to the captured still image as a data file on the recording medium.

The reproduction operation of a still image will be described. When an instruction to play a still image data file recorded in the image recording unit 18 is input from the operation unit 16, the synchronization control unit 15 transfers the data file selected by the operation unit 16 from the recording medium to the image recording unit 18. Read through. The synchronization control unit 15 supplies the read data file to the compression / decompression unit 14 to execute the decompression / decoding process. The image signal decoded by the compression / decompression unit 14 is supplied to the image display unit 17 via the synchronization control unit 15. The image display unit 17 reproduces and displays a still image on a display device based on the supplied image signal.

The operation of recording a moving image will be described. The image sensor 12 sequentially supplies the pixel signals of the moving image to the signal processing unit 13. The signal processing unit 13 sequentially performs signal processing on the pixel signals of the moving image supplied from the image sensor 12. The pixel signal of the signal-processed moving image is supplied to the compression / decompression unit 14 via the synchronization control unit 15, and is subjected to compression coding processing. The coded data of the moving image generated by the compression / decompression unit 14 is sequentially transferred to the image recording unit 18 via the synchronization control unit 15. The image recording unit 18 records the encoded data of the transferred moving image on the recording medium.

The operation of reproducing a moving image will be described. The synchronization control unit 15 reads a moving image data file from the image recording unit 18 and supplies it to the compression / decompression unit 14. The compression / decompression unit 14 performs decompression / decoding processing on the supplied moving image data file. The pixel signal decoded by the compression / decompression unit 14 is supplied to the image display unit 17 via the synchronization control unit 15. The image display unit 17 reproduces and displays a moving image on the display device based on the supplied pixel signal.

FIG. 2 is a diagram illustrating the configuration of the image sensor 12 according to the first embodiment of the present invention. The image sensor (CMOS sensor) 12 includes a pixel region 201 having a plurality of pixels 200, a vertical scanning unit 202, a column signal processing unit 203, a horizontal scanning unit 207, an output unit 209, and a timing unit 211. The operation by each part of the image pickup device 12 described below is executed based on the control of the synchronization control unit 15.

The pixel area 201 is composed of pixels 200 of a CMOS sensor, which will be described later. The plurality of pixels 200 included in the pixel region 201 are arranged in a matrix (matrix) in the horizontal direction (row direction) and the vertical direction (column direction).

As shown in FIG. 2, the plurality of pixels 200 are designated as "P [row number] [column number]" (for example, the pixel 200 in the first row and the first column is represented as P11, 8). The pixel 200 in the sixth row and the sixth column is referred to as P86). The pixel area 201 in FIG. 2 is exemplified as having a 6 × 8 array (8 rows and 6 columns), but the number of rows and columns of the pixels 200 included in the pixel area 201 is not limited to this configuration. ..

The plurality of pixels 200 are arranged over the entire pixel area 201. With respect to the plurality of pixels 200, the R (red) filter and the G (green) filter are alternately and repeatedly arranged in the odd-numbered rows, and the G (green) filter and the B (blue) filter are alternately and repeatedly arranged in the even-numbered rows. There is. That is, the color filters are arranged so as to form a pattern that is repeated in units of 2 × 2 arrays (2 rows and 2 columns).

In the pixel region 201, the pixel control line 221 is commonly connected for each row (pixel row) of the pixel 200, and the vertical signal line 231 is commonly connected for each column (pixel column) of the pixel 200. The vertical scanning unit 202 selects the pixels 200 in the pixel area 201 line by line and transmits a drive control signal via the pixel control line 221 to drive and control the reset operation and the read operation of the selected pixel line. .. The pixel signal of the pixel line selected by the vertical scanning unit 202 via the pixel control line 221 is read out (output) to the vertical signal line 231 corresponding to each pixel 200. The column signal processing unit 203 provided for each of the plurality of vertical signal lines 231 performs column signal processing, which will be described later, on the row-by-row pixel signals supplied via the vertical signal lines 231 after processing. Store the pixel signal.

Each of the column signal processing units 203 is connected to the horizontal scanning unit 207 by a corresponding column selection line 251. The horizontal scanning unit 207 selects the column signal processing unit 203 for each column via the column selection line 251 so that the digitized pixel signal stored in the column signal processing unit 203 can be used for the horizontal output line 261. It is controlled so that it is transferred to the output unit 209 via. The output unit 209 outputs a digitized line-by-line pixel signal to the signal processing unit 13.

The timing unit 211 outputs signals such as various clock signals and control signals necessary for the operation of each unit of the image sensor 12 based on the control signal from the synchronization control unit 15. The timing unit 211 includes a signal line 271 that sends a signal to the vertical scanning unit 202, a control line 281 that sends a signal to the column signal processing unit 203, and a control line 285 that sends a signal to the horizontal scanning unit 207. It is connected.

FIG. 3 is a circuit diagram showing a circuit configuration of each pixel 200 of the image pickup device 100 according to the first embodiment of the present invention. In FIG. 3, one of the pixels 200 constituting the pixel region 201 is typically shown by a rectangular dotted line.

The pixel 200 is connected to another circuit by a pixel control line 221 and a vertical signal line 231. In FIG. 3, the pixel P11 is connected to the vertical signal line 231. The vertical signal line 231 is connected to the load circuit and the column signal processing unit 203, and is also commonly connected to a plurality of pixels 200 (vertical pixel array) arranged in one vertical row to transmit a pixel signal. The pixel control line 221 described above is connected to the vertical scanning unit 202 and is also commonly connected to a plurality of pixels 200 (horizontal pixel strings) arranged in one horizontal row. The vertical scanning unit 202 simultaneously controls the pixels in one horizontal row to read and reset the signal. Each pixel control line 221 includes a transfer control line pTX, an FD extended control line pFDext, a reset control line pRS, and a selection control line pSEL, which will be described later.

The photoelectric conversion element (photoelectric conversion unit) PD is a photodiode that converts light into electric charges and stores the converted electric charges. In the photoelectric conversion element PD, the P side of the PN junction is grounded, and the N side of the PN junction is connected to the source of the transfer transistor (transfer switch) TX.

In the transfer transistor TX, the gate is connected to the transfer control line pTX and the drain is connected to the FD capacitance CFD. The transfer transistor TX controls the transfer of electric charge from the photoelectric conversion element PD to the FD capacitance CFD.

One of the FD capacitance CFDs is grounded, and the electric charge is accumulated when the electric charge transferred from the photoelectric conversion element PD is converted into a voltage. Hereinafter, the connection point between the drain of the transfer transistor TX and the other side (non-grounded side) of the FD capacitance CFD will be referred to as an FD node 301.

The FD expansion transistor (FD expansion unit) FDext is a MOS transistor in which the gate is connected to the FD expansion control line pFDext, the source is connected to the FD capacitance CFD, and the drain is connected to the reset transistor (reset switch) RS.

In the reset transistor RS, the gate is connected to the reset control line pRS, the drain is connected to the power supply voltage Vdd, and the source is connected to the FD expansion transistor FDext.

By setting both the FD expansion transistor FDext and the reset transistor RS to the ON state, the potential of the FD node 301 is reset to the power supply voltage Vdd. On the other hand, when both the FD expansion transistor FDext and the reset transistor RS are in the off state, the electric charge transferred from the photoelectric conversion element PD is converted into a voltage in the FD capacitance CFD.

When the FD expansion transistor FDext is in the ON state and the reset transistor RS is in the OFF state, the FD expansion transistor FDext functions as a storage unit (that is, a storage capacity) capable of holding electric charges. The above storage capacity may be hereinafter referred to as FD expansion capacity Cex. At this time, since the storage capacity and the FD capacity CFD of the FD expansion transistor FDext are grounded in parallel with the substrate, the capacity seen from the FD node 301 is the capacity obtained by adding the FD expansion capacity Cex to the FD capacity CFD (FD). The additional capacity is CFDadd). Therefore, in the FD node 301, the electric charge transferred from the photoelectric conversion element PD is converted into a voltage by using the additional capacitance CFDadd which is the sum of the FD capacitance CFD and the FD expansion capacitance Cex.

The drive transistor (amplification unit) Tdrv is a transistor constituting an intra-pixel amplifier, in which the gate is connected to the FD capacitance CFD, the drain is connected to the power supply voltage Vdd, and the source is connected to the drain of the selection transistor SEL. .. Therefore, the drive transistor Tdrv outputs a voltage corresponding to the voltage of the FD capacitance CFD.

In the selection transistor SEL, the gate is connected to the selection control line pSEL and the source is connected to the vertical signal line 231. The selection transistor SEL outputs the output of the drive transistor Tdrv to the vertical signal line 231 as an output signal (pixel signal) of the pixel 200.

In the load transistor Trod of the load circuit provided for each vertical signal line, the gate and the source are grounded, and the drain is connected to the vertical signal line 231. The load transistor Trod constitutes a source follower circuit that functions as an intra-pixel amplifier together with the drive transistor Tdrv of the pixels 200 in the row connected by the vertical signal line 231. Normally, when the signal of the pixel 200 is output, the load transistor Trod is operated as a constant current source for grounding the gate.

In the present embodiment, the transistors other than the drive transistor Tdrv and the load transistor Trod act as switches, and the control line connected to the gate conducts when it is High (turns ON) and shuts off when it is Low (OFF state). Will be).

FIG. 4 is a circuit diagram showing a circuit configuration of the column signal processing unit 203 of the image pickup device 12 according to the present embodiment. The column signal processing unit 203 includes two switch circuits 400 and 401, a comparator 402, a counter circuit 403, a latch circuit 404, and an arithmetic circuit 405. As described below, the column signal processing unit 203 functions as an AD conversion circuit.

The switch circuit 400 has a sample hold operation of holding the pixel signal Vsig transmitted from the vertical signal line 231 in the sample hold capacitance CSH based on the control from the column signal processing unit 203 via the connected switch control line pSwS. To control. The switch circuit 400 conducts when the control signal supplied from the switch control line pSwS is High (turns on), and shuts off when the control signal is Low (turns off).

The switch circuit 401 controls the sample hold operation of holding the pixel signal Vsig transmitted from the vertical signal line 231 in the sample hold capacitance CSH based on the control from the comparator 402 via the connected switch control line pSwH. To do. The switch circuit 401 conducts when the control signal supplied from the switch control line pSwH is High (turns on), and shuts off when the control signal is Low (turns off).

The comparator 402 is an element that outputs a comparison result of two input signals. For example, when the magnitude relationship between the two input signals is reversed, the output signal is changed from High to Low. A sample hold capacitance CSH and a ramp wave signal line Vrmp are connected to the comparator 402 as two input signal sources. The lamp wave output by the timing unit 211 to the lamp wave signal line Vrmp is a triangular wave that gradually changes from the initial voltage. It is preferable that the amplitude of the above lamp wave has a sufficient margin with respect to the saturation amplitude of the pixel signal input to the comparator 402. The comparator 402 outputs the comparison result when the gradually changing lamp wave intersects the pixel signal.

Further, the comparator 402 can output a switching signal to the switch control line pSwH that controls the sample hold operation for each column based on the comparison result between the determination voltage Vjd and the pixel signal Vsig. In the present embodiment, the comparator 402 sets the switch circuit 401 to the off state if the voltage (pixel voltage) of the pixel signal Vsig is larger than the determination voltage Vjd. As a result, the pixel signal Vsig at the time of the comparison operation by the comparator 402 is held in the sample hold capacitance CSH. On the other hand, the comparator 402 sets the switch circuit 401 to the ON state if the pixel signal Vsig is smaller than the determination voltage Vjd. As a result, the pixel signal Vsig is maintained in a state in which it can be input. Details of the output of the switching signal with respect to the switch control line pSwH will be described later.

The counter circuit 403 operates the counter based on the clock supplied from the connected counter control line pCNT. The counter circuit 403 starts the counting operation in accordance with the start of the lamp wave, and outputs the count value at the time when the signal of the comparison result from the comparator 402 is received. The output count value (discrete value) corresponds to a digitized pixel signal received by the column signal processing unit 203 via the vertical signal line 231.

The latch circuit 404 temporarily holds the count value output by the counter circuit 403, and outputs the count value held based on the control via the connected latch control line pLTC.

The arithmetic circuit 405 stores the count value output by the latch circuit 404 as a pixel digital signal based on the control via the connected arithmetic control line pCAL. In addition, the arithmetic circuit 405 outputs the digital signal of the stored pixel to the digital output line DSig based on the control via the corresponding selection line pH.

As described above, the column signal processing unit 203 constitutes an AD conversion circuit using a comparator 402, a counter circuit 403, a latch circuit 404, and a ramp wave signal line Vrmp.

Further, as described above, the control line 281 connected from the timing unit 211 to the column signal processing unit 203 includes a switch control line pSwS, a ramp wave signal line Vrmp, a counter control line pCNT, a latch control line pLTC, and an arithmetic control line. Includes pCAL. The column selection line 251 connected from the horizontal scanning unit 207 to the column signal processing unit 203 corresponds to the selection line pH in FIG. The horizontal output line 261 connected from the column signal processing unit 203 to the output unit 209 corresponds to the digital output line DSig in FIG.

Next, the operation of the image pickup apparatus 1 according to the first embodiment of the present invention will be described below. The operation of the image pickup apparatus 1 is realized by driving each portion of the image pickup apparatus 1 based on the control by the synchronization control unit 15.

FIG. 5 is a timing chart showing a shooting operation executed by the imaging device 1. The horizontal axis (horizontal direction) indicates time, and the vertical axis (vertical direction) corresponds to all rows of the pixel region 201 of the image sensor 12.

The frame synchronization signal FSync is a synchronization signal for driving the image sensor 12, and is a signal that becomes effective when the image sensor 12 falls and triggers a predetermined operation to be executed for each frame. As shown in FIG. 5, the synchronization signals FSync are arranged at equal intervals in chronological order and fall at time s01, s04, s08, s12, and s16.

The diagonal line drawn by the solid line indicates the operation timing of the pixel region 201 of the image sensor 12 for each row. For example, the diagonal lines drawn from time s01 to s03 correspond to the operation of reading the pixel signal line by line, and the diagonal lines drawn from time s02 to s05 correspond to the charge of the photoelectric conversion element PD line by line. Corresponds to the reset operation. The above reset operation corresponds to the exposure start operation. The diagonal lines drawn from time s04 to s07 correspond to the operation of reading out the electric charge of the photoelectric conversion element PD line by line. The above reading operation corresponds to the exposure end operation and the pixel signal reading operation. As a result of the above operation, a signal corresponding to the subject image is acquired.

Similarly, the diagonal lines drawn starting from time s06 and time s10 correspond to the operations of charge reset and exposure start of the photoelectric conversion element PD. The diagonal lines drawn starting from the time s08 and the time s12 correspond to the operation of the end of exposure and the charge reading of the photoelectric conversion element PD.

As described above, continuous shooting can be performed by executing exposure control and pixel signal reading for each frame.

The pixel operation of the image pickup device 12 according to the first embodiment of the present invention will be described with reference to FIGS. 6 and 7. FIG. 6 is a timing chart showing the operation of the pixel 200 in the image sensor 12 according to the first embodiment of the present invention. The horizontal axis indicates time, and the vertical axis indicates signal on / off (high / low potential).

The line synchronization signal LSync is a synchronization signal for driving the image sensor 12, and is a signal that becomes effective when the image sensor 12 falls and triggers a predetermined pixel operation for each line. The line synchronization signal Lsync is supplied so that the pixels 200 in each line from the first line to the last line in the pixel area 201 operate synchronously within one period (one cycle) of the frame synchronization signal Fsync.

Further, FIG. 6 shows the operation timings of the transfer control line pTX, the FD extended control line pFDext, the reset control line pRS, and the selection control line pSEL included in the pixel control line 221.

FIG. 6A shows the transition of the control signal in one line for executing the charge reset of the photoelectric conversion element PD for the line-by-line reset operation starting from the times s02, s06, and s10 in FIG. Following the activation of the line synchronization signal Lsync, all the control lines other than the selection control line pSEL included in the pixel control line 221 are set to the ON state, so that the photoelectric conversion element PD, the FD capacitance CFD, and the FD are set to the ON state. The expansion capacity Cex is reset to the power supply voltage Vdd.

Next, the transfer control line pTX is set to the off state and the transfer transistor TX is cut off, so that the exposure is started. After that, the FD expansion control line pFDext and the reset control line pRS are sequentially set to the off state, and the FD expansion transistor FDext and the reset transistor RS are sequentially cut off, so that the FD capacitance reset operation is completed.

6 (b) to 6 (f) show the control signal in one line for executing the charge reading of the photoelectric conversion element PD for the pixel signal reading operation for each line starting from the times s04, s08, and s12 in FIG. Shows the transition. The charge reading operation of the photoelectric conversion element PD will be described below with reference to FIG. 7.

FIG. 7 is a schematic explanatory view of the reading operation of the pixel 200 in the image sensor 12 according to the first embodiment of the present invention.

FIG. 7A shows the circuit configuration of the pixel 200 as in FIG. 7 (b-1) to 7 (b-7) are potential distribution diagrams along the dotted line path shown in FIG. 7 (a). Since the P side of the PN junction of the photoelectric conversion element PD is grounded, electrons are accumulated on the N side with respect to the signal load. In FIGS. 7 (b-1) to 7 (b-7), the potential is expressed with reference to electrons (negative charges). Therefore, the more electrons are accumulated with respect to the power supply voltage Vdd, the more the potential value (in the figure). (Vertical position of) becomes higher. In the charge-voltage conversion using the FD capacitance of the present embodiment, it is preferable that the conversion operation is executed within a range in which linearity is maintained in the relationship between the voltage to be the pixel signal and the transferred charge. ..

Here, the amount of charge that saturates the photoelectric conversion element PD is defined as the PD capacitance, the amount of charge that saturates the FD portion is defined as the FD capacitance CFD, and the amount of charge that saturates the FD expansion portion is defined as the FD expansion capacitance Cex. In the present embodiment, the amount of charge capable of maintaining the linearity of charge-voltage conversion in the FD addition capacitance CFDadd, which is the sum of the FD capacitance CFD and the FD expansion capacitance Cex, is substantially equal to the PD capacitance in which the photoelectric conversion element PD is saturated. To set. The above setting state can be expressed as PD capacity: FD addition capacity = 1: 1. FD capacity Each capacity when expressed in a ratio based on CFD is set as FD capacity: FD expansion capacity: FD addition capacity: PD capacity = 1: 3: 4: 4. Further, the conversion gain of charge-voltage conversion in the FD capacitance CFD set as described above is hereinafter expressed as 1 time (or x1) as a standardized value. As described above, since the FD addition capacity CFDadd is four times the FD capacity CFD, the conversion gain of the charge-voltage conversion in the FD addition capacity CFDadd can be expressed as 1/4 times (or x1 / 4).

The set value of each capacity is not limited to the above-mentioned FD capacity: FD expansion capacity: FD addition capacity = 1: 3: 4, and the FD expansion capacity Cex may be set to 1 or more. For example, FD capacity: FD expansion capacity: FD addition capacity = 1: 7: 8 may be set. In the above case, the conversion gain of the charge-voltage conversion in the FD addition capacitance CFDadd is 1/8 times (or x1 / 8).

In the following description, the case of charge-voltage conversion using only the FD capacity CFD is referred to as "high gain conversion", and the case of charge-voltage conversion using the FD addition capacity (= FD capacity + FDE expansion capacity) is referred to as "low gain conversion". Refer to. Further, in the charge-voltage conversion, the voltage in a state where the FD capacitance and the FD addition capacitance are saturated is referred to as "FD saturation voltage". As described above, since the FD capacitance is included in the FD addition capacitance CFDadd, the saturation voltage of the FD capacitance and the saturation voltage of the FD addition capacitance are equal. Further, the voltage of the pixel signal corresponding to the "FD saturation voltage" is referred to as a "pixel saturation voltage".

FIG. 7 (b-1) shows the potential distribution in the exposure period after the reset operation described with reference to FIG. 6 (a). Each transistor conducts electrons when it is on, and blocks electrons as a barrier when it is off. In the exposure state shown in FIG. 7 (b-1), electrons are accumulated in the photoelectric conversion element PD, and the transfer transistor TX, the FD expansion transistor FDext, and the reset transistor RS are all set to the off state.

As described above, FIGS. 6 (b) to 6 (f) correspond to the pixel signal reading operation. FIG. 6B shows the transition of the control signal when the reset operation of the FD capacitance CFD is executed. Following the activation of the line synchronization signal Lsync, the selection transistor SEL is set to the ON state, so that the pixel signal is output to the vertical signal line 231. At the same time, the FD capacitance CFD is reset by setting the FD expansion transistor FDext and the reset transistor RS to the ON state.

FIG. 7 (b-2) shows the potential distribution when the FD capacitance CFD is reset to the potential of the power supply voltage Vdd by setting the FD expansion transistor FDext and the reset transistor RS to the ON state. Since the transfer transistor TX is maintained in the off state, the photoelectric conversion element PD maintains the state of holding the electric charge. After that, the FD expansion transistor FDext and the reset transistor RS are sequentially set to the off state, so that the reset operation of the FD capacitance CFD is completed.

FIG. 7 (b-3) shows the potential distribution when the FD expansion transistor FDext and the reset transistor RS are set to the off state and the reset operation of the FD capacitance CFD is completed. FIG. 7 (b-3) corresponds to a state of high gain conversion (that is, 1 times) in which charge voltage is converted only by the FD capacitance CFD. In the above high gain conversion state, the pixel signal output to the vertical signal line 231 is defined as the high gain reset signal VnH.

FIG. 6C shows the transition of the control signal when the gain changing operation in the FD unit is executed. The FD expansion capacitance Cex is generated by setting the FD expansion transistor FDext to the on state while the reset transistor RS is set to the off state. As a result, the FD capacity CFD and the FD expansion capacity Cex are added.

FIG. 7 (b-4) shows the potential distribution when the FD capacitance CFD and the FD expansion capacitance Cex are added by setting the FD expansion transistor FDext to the ON state. By the above addition operation, the state transitions to the low gain conversion (that is, 1/4 times) state in which the charge voltage is converted using the FD addition capacity CFDadd in which the FD capacity CFD and the FD expansion capacity Cex are added. In the above low gain conversion state, the pixel signal output to the vertical signal line 231 is defined as the low gain reset signal VnL.

FIG. 6D shows the transition of the control signal when the electric charge accumulated in the photoelectric conversion element PD is transferred to the FD unit. When the transfer transistor TX is set to the ON state, the signal charge is transferred from the photoelectric conversion element PD to the FD addition capacitance CFDadd of the FD unit. After the signal charge transfer is complete, the transfer transistor TX is set to the off state.

7 (b-5) and 7 (b-6) correspond to a state in which the transfer of the signal charge from the photoelectric conversion element PD to the FD addition capacitance CFDadd of the FD unit is completed. When the FD capacity: the FD addition capacity = 1: 4, the determination voltage Vjd is set to 1/4 of the saturation voltage of the pixels.

FIG. 7 (b-5) shows the potential distribution when the potential of the pixel signal after performing low gain charge-voltage conversion on the transferred signal charge is equal to or higher than the determination voltage Vjd. In the above state, the pixel signal output to the vertical signal line 231 is defined as a low gain high illuminance signal VsL_high. On the other hand, FIG. 7 (b-6) shows the potential distribution when the potential of the pixel signal after the transferred signal charge is subjected to low gain charge-voltage conversion is less than the determination voltage Vjd. In the above state, the pixel signal output to the vertical signal line 231 is defined as a low gain low illuminance signal VsL_low.

FIG. 6E shows the transition of the control signal when the gain changing operation is executed in the FD unit. When the FD expansion transistor FDext is set to the off state, the FD expansion capacitance Cex disappears. As a result, the state transitions to a state in which charges can be accumulated only in the FD capacitance CFD, that is, a high gain conversion (that is, 1 times) state in which the charge voltage is converted only by the FD capacitance CFD.

FIG. 7 (b-7) shows the potential distribution when the charge is accumulated only in the FD capacitance CFD by setting the FD expansion transistor FDext to the off state in the state of FIG. 7 (b-6). .. Since the reset transistor RS is maintained in the off state, when the FD expansion transistor FDext changes from the on state to the off state, the signal charge accumulated in the FD expansion capacitance Cex of the FD expansion transistor FDext returns to the FD capacitance CFD. Is added. As described above, since the FD capacity: FD addition capacity is set to 1: 4, if the signal charge accumulated in the FD addition capacity CFDadd is returned to the FD capacity CFD as it is, the potential value is quadrupled.

Since the voltage of the pixel signal in the state of FIG. 7 (b-6) is smaller than the determination voltage Vjd set to 1/4 of the saturation voltage of the pixel, the pixel signal in the state of FIG. 7 (b-7) is not saturated. As a result, a voltage four times that of the pixel signal in the state of FIG. 7 (b-6) is output. In the above state, the pixel signal output to the vertical signal line 231 is defined as a high gain low illuminance signal VsH_low.

On the other hand, the voltage of the pixel signal in the state of FIG. 7 (b-5) is equal to or higher than the determination voltage Vjd set to 1/4 of the saturation voltage of the pixels. Therefore, if the signal charge accumulated in the FD addition capacitance CFDadd is returned to the FD capacitance CFD as it is, it exceeds the FD capacitance CFD and overflows. Therefore, it is preferable to set the potential when the reset transistor RS and the FD expansion transistor FDext are set to the off state to be slightly lower (that is, to increase the voltage) than the potential when the transfer transistor TX is set to the off state. Is. By setting as described above, the FD capacitance CFD can have an overflow function, and the signal charge overflowing the FD capacitance CFD can be discharged to the power supply Vdd. The above overflow function is effective not only when the signal charge of the FD capacitance CFD overflows, but also when the signal charge of the FD addition capacitance CFDadd overflows. In the above state, the pixel signal output to the vertical signal line 231 is defined as a high-gain high-illuminance signal VsH_high. However, since the above high illuminance signal VsH_high is a voltage in an overflowed state and does not correctly correspond to the pixel potential, it is not used in the previous processing in this embodiment.

FIG. 6 (f) shows the transition of the control signal when the reset operation is executed for the photoelectric conversion element PD and the FD capacitance CFD. The photoelectric conversion element PD and the FD capacitance CFD are reset by setting the transfer transistor TX, the FD expansion transistor FDext, and the reset transistor RS to the ON state. After that, the transfer transistor TX, the FD expansion transistor FDext, and the reset transistor RS are sequentially set to the off state, so that the reset operation of the photoelectric conversion element PD and the FD capacitance CFD is completed. Next, by setting the selection transistor SEL to the off state, the readable pixel 200 and the vertical signal line 231 are electrically separated from each other.

As described above, the pixel signal reading operation for one line started from the activation of the line synchronization signal Lsync is executed. After that, the operation of reading the pixel signal of the next line is started, triggered by the line synchronization signal Lsync of the next line shown in FIG. 6 (f). In parallel with the pixel signal reading operation of the next row, the horizontal scanning unit 207 selects the column signal processing unit 203 for each column via the column selection line 251 and stores the digitized pixels. The signal is controlled to be transferred to the output unit 209 via the horizontal output line 261.

The pixel readout operation and the comparison operation of the image pickup device 12 according to the first embodiment of the present invention will be described with reference to FIGS. 8 and 9. FIG. 8 is a timing chart of the column signal processing unit 203 showing the reading operation and the comparison operation in the image sensor 12 according to the first embodiment of the present invention. FIG. 8 shows the operation of reading the pixel signal of one line in the operation of each line starting from the times s04, s08, and s12 of FIG. 5, and the transition of the pixel signal Vsig and the lamp wave Vrmp input to the comparator 402. Is shown. The horizontal axis (t direction) corresponds to the passage of time, and the vertical axis (V direction) corresponds to the potential based on the initial voltage of the lamp wave Vrmp.

In the period tr1, the operation of initializing the column signal processing unit 203 is executed. As the above initial setting, for example, clamping on the input signal of the comparator 402 is executed. More details are as follows. The output from the comparator 402 to the switch control line pSwH is set to High, and the switch control line pSwS is set to High. As a result, the two switch circuits 400 and 401 are set to the ON state, and the pixel signal Vsig, which is the initial state of the vertical signal line 231 is held in the sample hold capacitance CSH. At this time, in the comparator 402, the pixel signal Vsig and the lamp wave signal Vrmp, which are two input signals, are clamped as reference levels. The switch control line pSwH is maintained high until the determination period described later is reached.

In the period tt1, the FD capacitance CFD is reset and the gain of the charge-voltage conversion is set to a high gain (that is, 1 times) for performing the charge-voltage conversion using only the FD capacitance CFD. The control timing of the pixel operation at the time of reset is as described with reference to FIG. 6 (b), and the potential distributions of the pixel during reset and the pixel after reset are shown in FIG. 7 (b-2), respectively. And as described with reference to FIG. 7 (b-3). The period tt1 corresponds to the read-out period of the reset signal VnH after the FD capacitance CFD is reset and the reset transistor RS is set to the off state, and the signal stabilization period thereafter. The reset signal VnH as the pixel signal Vsig is input to the sample hold capacitance CSH and the comparator 402 via the vertical signal line 231. The reset signal VnH may be held in the sample hold capacitance CSH by setting the switch control line pSwS to Low and setting the switch circuit 400 to the off state. The switch control line pSwH is maintained high and the switch circuit 401 is maintained in the on state.

The lamp wave G1 is generated in the period tr2. The comparator 402 outputs a comparison signal indicating the result of comparing the reset signal VnH and the lamp wave G1. Then, the count value cnH at the timing when the comparison signal from the comparator 402 is inverted (the time when the period tnH has elapsed) is stored in the arithmetic circuit 405.

In the period tt2, the gain of the charge-voltage conversion is changed to a low gain (ie, 1/4 times) for performing the charge-voltage conversion using the FD addition capacitance CFDadd. The control timing of the pixel operation when the gain is changed is as described with reference to FIG. 6 (c), and the potential distribution of the pixel changed to the low gain is described with reference to FIG. 7 (b-4). As explained above. The period tt2 corresponds to a period in which the high gain reset signal VnH transitions to the low gain reset signal VnL and a subsequent signal stabilization period based on the change in the conversion gain of the FD unit from the high gain to the low gain. The reset signal VnL as the pixel signal Vsig is input to the sample hold capacitance CSH and the comparator 402 via the vertical signal line 231. When the switch control line pSwS is set to Low in the period tt1, it is set to High again in this period and the switch circuit 400 is set to the ON state. After the input of the reset signal VnL is started, the reset signal VnL may be held in the sample hold capacitance CSH by setting the switch control line pSwS to Low and setting the switch circuit 400 to the off state. The switch control line pSwH is maintained high and the switch circuit 401 is maintained in the on state.

The lamp wave G1 is generated in the period tr3. The comparator 402 outputs a comparison signal indicating the result of comparing the reset signal VnL and the lamp wave G1. Then, the count value cnL at the timing when the comparison signal from the comparator 402 is inverted (the time when the period tnL has elapsed) is stored in the arithmetic circuit 405. The rate of change (slope) and the generation period of the lamp wave G1 generated in the period tr3 are substantially equal to the rate of change and the generation period of the lamp wave G1 generated in the period tr2. Therefore, the AD conversion is executed under common conditions in the period tr2 and the period tr3.

In the period tt3, the electric charge accumulated in the photoelectric conversion element PD is transferred to the FD addition capacitance CFDadd of the FD unit. When the switch control line pSwS is set to Low first, the pixel signal Vsig of the vertical signal line 231 is set to the sample hold capacity CSH by setting the switch control line pSwS to High and setting the switch circuit 400 to the ON state. Set so that it can be held in. The control timing of the pixel operation during the above charge transfer is as described with reference to FIG. 6 (d), and the potential distributions of the high-light pixel and the low-light pixel after the charge transfer are shown in FIG. 7 (b), respectively. As described with reference to −5) and FIG. 7 (b-6). The period tt3 corresponds to the charge transfer period from the photoelectric conversion element PD to the FD addition capacitance CFDadd of the FD unit and the subsequent signal stabilization period. Since the FD section is set to low gain in this period, the low gain high illuminance signal VsL_high or the low gain low illuminance signal VsL_low is sent to the sample hold capacitance CSH and the comparator 402 via the vertical signal line 231 as the pixel signal Vsig. Is entered. By setting the switch control line pSwS to Low and setting the switch circuit 400 to the off state, the pixel signal having the above low gain may be held in the sample hold capacitance CSH. The switch control line pSwH is maintained high and the switch circuit 401 is maintained in the on state.

In the period tr4, the comparator 402 compares the determination voltage Vjd output to the ramp wave signal line Vrmp with the voltage of the low gain pixel signal Vsig (low gain high illuminance signal VsL_high or low gain low illuminance signal VsL_low). Judge the magnitude relationship. The period tr4 corresponds to the determination period. Hereinafter, the determination operation by the comparator 402 will be described with reference to FIG.

FIG. 9 is an explanatory diagram of a determination operation executed by the column signal processing unit 203 of the image pickup device 12 according to the first embodiment of the present invention. In FIG. 9, for explanation, the column signal processing unit 203 to which the vertical signal line 231 to which the high-intensity signal is output is connected is on the upper side, and the column signal processing unit 203 to which the vertical signal line 231 to which the low-intensity signal is output is connected. Is shown on the bottom. The high illuminance signal is a low gain high illuminance signal VsL_high or a high gain high illuminance signal VsH_high, and the low illuminance signal is a low gain low illuminance signal VsL_low or a high gain low illuminance signal VsH_low. In FIG. 9, elements other than the sample hold circuit S & H that executes the determination operation and the comparator Comp (comparator 402) are shown in a simplified manner.

FIG. 9A shows the state of the sample hold circuit S & H immediately before the period tr4 at which the determination voltage Vjd is output. In both sample hold circuits S & H, the switch control lines pSwS and pSwH are set to High, so that the switch circuits 400 and 401 are set to the ON state. Therefore, as described above for the period tt3, the low gain high illuminance signal VsL_high and the low gain low illuminance signal VsL_low are input to the sample hold capacitance CSH and the comparator 402, respectively.

FIG. 9B shows the state of the sample hold circuit S & H in the period tr4, which is the determination period. In FIG. 9B, the comparator 402 determines the magnitude relationship between the determination voltage Vjd output to the lamp wave signal line Vrmp and the low gain pixel signal Vsig (VsL_high, VsL_low). When the switch control line pSwS is set to Low, the switch circuit 400 is set to the off state, and the low gain pixel signal Vsig (VsL_high, VsL_low) is held in the sample hold capacitance CSH.

In the comparator 402 (upper side) to which the low-gain high-intensity signal VsL_high is input, the voltage of the low-gain high-intensity signal VsL_high is equal to or higher than the determination voltage Vjd, so that the comparison result by the comparator 402 is High. The comparator 402 outputs the inverted Low of the comparison result to the switch control line pSwH, and sets the switch circuit 401 to the off state.

On the other hand, in the comparator 402 (lower side) to which the low gain low illuminance signal VsL_low is input, the voltage of the low gain low illuminance signal VsL_low is smaller than the determination voltage Vjd, so the comparison result by the comparator 402 is Low. The comparator 402 outputs High in which the comparison result is inverted to the switch control line pSwH, and sets the switch circuit 401 in the ON state.

As described above, in the period tr4 which is the determination period, the comparator 402 (Comparator Comp) outputs a signal obtained by inverting the comparison result by the comparator 402 to the switch control line pSwH as a switching signal. In addition, the switch control line pSwH after the period tr4 is controlled to maintain the signal state (High or Low) until the column signal processing unit 203 is initialized in the period tr1 of the pixel signal reading of the next row. ..

When the period tr4 ends, the output of the determination voltage Vjd is stopped, so that the low gain pixel signal Vsig (VsL_high, VsL_low) exceeds the lamp wave signal Vrmp, so that the comparison result by the comparator 402 returns to High.

In period tt4, the gain of charge-voltage conversion is changed to a high gain (ie, 1x) to perform charge-voltage conversion using only the FD capacitance CFD. When the switch control line pSwS is set to Low first, the pixel signal Vsig of the vertical signal line 231 is set to the sample hold capacity CSH by setting the switch control line pSwS to High and setting the switch circuit 400 to the ON state. Set so that it can be held in. The control timing of the pixel operation when the gain is changed is as described with reference to FIG. 6 (e), and the potential distribution of the low-light pixel changed to the high gain is shown in FIG. 7 (b-7). As explained with reference. The period tt4 corresponds to a period during which the low-gain pixel signal Vsig transitions to the high-gain pixel signal Vsig and a subsequent signal stabilization period based on the change in the conversion gain of the FD unit from low gain to high gain.

Here, when the low gain high illuminance signal VsL_high is input to the comparator 402 during the period tr4 and the determination operation is executed (upper side), the switch circuit 401 is set to the off state as described above. Therefore, the high gain high illuminance signal VsH_high, which is the pixel signal Vsig obtained by the high gain charge-voltage conversion, is not input to the sample hold capacitance CSH and the comparator 402. On the other hand, when the low gain low illuminance signal VsL_low is input to the comparator 402 and the determination operation is executed (lower side) in the period tr4, the switch circuit 401 is set to the ON state as described above. Therefore, the high gain low illuminance signal VsH_low, which is the pixel signal Vsig obtained by the high gain charge-voltage conversion, is input to the sample hold capacitance CSH and the comparator 402.

FIG. 9C shows a state in which a high-gain pixel signal Vsig (VsH_high, VsH_low) is input to the sample hold circuit S & H via the vertical signal line 231 during the period tt4. As described above, in the period tt4, the switch control line pSwS is set to High and the switch circuit 400 is set to the ON state.

In the sample hold circuit S & H (upper side) to which the high gain high illuminance signal VsH_high is input, the switch circuit 401 is set to the off state. Therefore, the low gain high illuminance signal VsL_high held in the sample hold capacitance CSH is input to the comparator 402. On the other hand, in the sample hold circuit S & H (lower side) to which the high gain low illuminance signal VsH_low is input, the switch circuit 401 is set to the ON state. Therefore, the high gain low illuminance signal VsH_low input to the sample hold circuit S & H is held in the sample hold capacitance CSH and input to the comparator 402.

After the high gain pixel signal Vsig is input, the high gain low illuminance signal VsH_low is held in the sample hold capacitance CSH by setting the switch control line pSwS to Low and setting the switch circuit 400 to the off state. You may. When the switch circuit 400 is set to the off state, the high gain low illuminance signal VsH_low held in the sample hold capacitance CSH is electrically disconnected from the vertical signal line 231. As a result, the high gain is low as in the low gain high illuminance signal VsL_high (upper side of FIG. 9B) that is electrically disconnected from the vertical signal line 231 and held in the sample hold capacitance CSH in the previous determination period tr4. The illuminance signal VsH_low can be held.

The lamp wave G1 is generated in the period tr5. The low gain high illuminance signal VsL_high or the high gain low illuminance signal VsH_low held in the sample hold capacitance CSH is AD-converted by being compared with the generated lamp wave G1. Since the rate of change (slope) of the lamp wave G1 generated in the period tr5 is substantially equal to the rate of change of the lamp wave G1 generated in the period tr2 and tr3, the conditions common to the period tr2 and tr3 and the period tr5 are the same. AD conversion is executed. However, since the period tr5 has a sufficient margin with respect to the amplitude of the pixel signal, the generation period of the lamp wave G1 in the period tr5 is longer than the generation period of the lamp wave G1 in the periods tr2 and tr3. In the present embodiment, since the voltage when the low gain pixel signal VsL equal to the determination voltage Vjd is converted into the high gain pixel signal VsH is equal to the saturation voltage of the FD, the amplitude of the ramp wave G1 corresponds to the saturation voltage. It is generated until the saturation voltage of the pixel is reached.

The comparator 402 outputs a comparison signal indicating the result of comparing the pixel signal Vsig and the lamp wave G1 in the period tr5. Regarding the high gain low illuminance signal VsH_low, the count value csH_low at the timing when the comparison signal from the comparator 402 is inverted (the time when the period tsH_low has elapsed) is stored in the arithmetic circuit 405. Regarding the low gain high illuminance signal VsL_high, the count value csL_high at the timing when the comparison signal from the comparator 402 is inverted (the time when the period tsL_high has elapsed) is stored in the arithmetic circuit 405.

Next, the arithmetic circuit 405 acquires and stores the digital signal value of the pixel signal Vsig based on the above-mentioned count value. The arithmetic circuit 405 of the column signal processing unit 203 (lower side) to which the high gain low illuminance signal VsH_low is input subtracts the count value cnH of the high gain reset signal VnH from the count value csH_low of the high gain low illuminance signal VsH_low. The arithmetic circuit 405 stores the value obtained by the above subtraction in the arithmetic circuit 405 itself as a digital value of the high gain low illuminance signal VsH_low.

On the other hand, the arithmetic circuit 405 of the column signal processing unit 203 (upper side) to which the low-gain high-intensity signal VsL_high is input subtracts the low-gain reset signal VnL count value cnL from the low-gain high-intensity signal VsL_high count value csL_high. As described above, the gains of the low-gain high-intensity signal VsL_high and the low-gain high-intensity signal VsL_high at the time of charge-voltage conversion are 1/4 times. Therefore, the arithmetic circuit 405 multiplies the value obtained by the above subtraction by four and stores the low gain high illuminance signal VsL_high as a digital value converted to the equivalent of high gain in the arithmetic circuit 405 itself.

Since the magnitude relationship between the determination voltage Vjd and the pixel signal Vsig in the period tr4 is stored in the arithmetic circuit 405 as a comparison result, the arithmetic circuit 405 selects the high gain reset signal VnH and the low gain reset signal VnL. be able to.

In the period tt5, the photoelectric conversion element PD and the FD capacitance CFD are reset, and the signal reading operation of one line of pixels ends. The control timing of the pixel operation at the time of the above reset is as described with reference to FIG. 6 (f). The period tt5 corresponds to the reset period of the photoelectric conversion element PD and the FD capacitance CFD and the subsequent signal stabilization period. The low-gain high-intensity signal VsL_high or high-gain low-intensity signal VsH_low held in the sample hold capacitance CSH is the pixel signal Vsig, which is the initial state of the vertical signal line 231 due to the initial setting operation at the time of signal reading of the next line pixel. Is rewritten to.

According to the above configuration, the pixel signal obtained by charge-voltage conversion (dual gain processing) using either of the two types of gain is AD-converted. Therefore, as compared with the configuration using a single gain, A wide dynamic range and high resolution accuracy in AD conversion can be realized. Further, when the magnification ratio of the two types of gain is n times (for example, 4 times), an input / output characteristic is realized so that the output is n times the AD conversion accuracy with respect to the input of the saturation voltage of the pixel. Therefore, it is possible to acquire an image that has been subjected to n times high dynamic range (HDR) processing.

According to the above configuration, since the low-light signal and the high-light signal are AD-converted in parallel (preferably at the same time) using the same single slope, a good image signal with reduced signal unevenness is obtained. it can. Therefore, the image quality of the captured image can be improved. In addition, since the low-light signal and the high-light signal can be AD-converted in parallel (preferably at the same time) in one process, the frame rate can be improved and timely AD conversion can be realized.

In summary, in the configuration of the present embodiment, HDR processing by one AD conversion can be realized and the frame rate can be improved by dual gain processing in which the gain of charge-voltage conversion is selected according to the voltage level of the pixel signal. realizable.

Further, in the above configuration, when reading the reset signal of the FD unit, the high gain reset signal VnH is converted into the low gain reset signal VnL by the FD extension unit that controls the conversion gain of the FD unit. By performing the above conversion process, the reset signals corresponding to the two types of gain can be continuously read out. In addition, when reading out the pixel signal corresponding to the signal charge of the photoelectric conversion element PD, the low gain pixel signal VsL is converted into the high gain pixel signal VsH by the FD extension unit that controls the conversion gain of the FD unit. By performing the above conversion processing, pixel signals corresponding to the two types of gain can be continuously read out. As described above, since the reset signal and the pixel signal corresponding to the two types of gain can be read out in a common state, the image quality of the captured image can be further improved.

<Modified example of the first embodiment>
A modified example of the first embodiment of the present invention will be described with reference to FIG. FIG. 10 is a circuit diagram showing a circuit configuration of the column signal processing unit 203 of the image pickup device 12 according to the modified example of the first embodiment. In addition, in each modification and each embodiment illustrated below, for the element whose operation and function are equivalent to those in the first embodiment, the reference numerals referred to in the above description are used and the respective description is appropriately omitted. Sometimes.

The column signal processing unit 203 of the first embodiment (FIG. 4) has two switch circuits 400 and 401. The sample hold operation is realized by controlling the switch circuits 400 and 401 by the switch control lines pSwS and pSwH, respectively.

In contrast, the column signal processing unit 203 of this modification has only one switch circuit 401. The sample hold operation of this modification is realized by controlling the switch circuit 401 by the output of the AND circuit to which the switch control lines pSwS and pSwH are connected.

In the first embodiment, during the AD conversion in the period tr5, the sample hold capacitance CSH holding the low gain high illuminance signal VsL_high is electrically separated from the vertical signal line 231 by the switch circuit 401 (FIG. 4). .. Similarly, during the AD conversion in the period tr5, the sample hold capacitance CSH holding the high gain low illuminance signal VsH_low is electrically separated from the vertical signal line 231 by the switch circuit 400 (FIG. 4).

In contrast, in this modification, the sample hold capacitance CSH is separated from the vertical signal line 231 by a single switch circuit 401 during the AD conversion in the period tr5.

Therefore, according to the configuration of this modification, the state of the low gain high illuminance signal VsL_high and the state of the high gain low illuminance signal VsH_low held in the sample hold capacitance CSH as compared with the configuration of the first embodiment of FIG. Can be closer. As a result, adverse effects such as signal unevenness on the image can be further reduced.

It should be noted that this modification can also be applied to the second embodiment described later.

<Second Embodiment>
Hereinafter, the second embodiment of the present invention will be described with reference to FIGS. 11 and 12. The description of FIGS. 1, 2, 4 to 6, 8 and 9 according to the first embodiment is incorporated into the second embodiment. In each of the embodiments illustrated below, for elements having the same functions and functions as those in the above-described embodiment, the reference numerals referred to in the above-described description will be used and the respective description will be omitted as appropriate.

FIG. 11 is a circuit diagram showing a circuit configuration of pixels 200 of the image pickup device 12 according to the second embodiment of the present invention. As described above, in the pixel 200 of the first embodiment (FIG. 3), the FD extension transistor FDext is arranged between the FD node 301 of the FD section and the reset transistor RS. On the other hand, in the pixel 200 of the second embodiment, as shown in FIG. 11, the FD extension transistor FDext is arranged between the transfer transistor TX and the FD node 301. The other circuit configurations are the same as those in the first embodiment (FIG. 3).

FIG. 12 is a schematic explanatory view of the reading operation of the pixel 200 in the image sensor 12 according to the second embodiment of the present invention.

FIG. 12A shows the circuit configuration of the pixel 200 as in FIG. An FD extension unit FDext is arranged between the transfer transistor TX and the FD node 301. 12 (b-1) to 12 (b-7) are potential distribution maps along the dotted line path shown in FIG. 12 (a). The operation timing of this embodiment is the same as that described with reference to FIGS. 5, 6, and 8, and the determination operation of this embodiment is the same as that described with reference to FIG. Is.

FIG. 12 (b-1) shows the potential distribution during the exposure period after the reset operation described with reference to FIG. 6 (a).

In the exposure state shown in FIG. 12 (b-1), electrons are accumulated in the photoelectric conversion element PD, and the transfer transistor TX, the FD expansion transistor FDext, and the reset transistor RS are all set to the off state.

In the period tt1 of FIG. 8, the FD capacitance CFD is reset, and the gain of the charge-voltage conversion is set to a high gain (that is, 1 times) for executing the charge-voltage conversion using only the FD capacitance CFD. The control timing of the pixel operation at the time of reset is as described with reference to FIG. 6 (b), and the potential distributions of the pixel during reset and the pixel after reset are shown in FIG. 12 (b-2), respectively. And shown in FIG. 12 (b-3). Since the transfer transistor TX is set to the off state, the photoelectric conversion element PD maintains the state of holding the electric charge.

In the period tt2 of FIG. 8, the gain of the charge-voltage conversion is changed to a low gain (that is, 1/4 times) for performing the charge-voltage conversion using the FD addition capacitance CFDadd. The control timing of the pixel operation when the gain is changed is as described with reference to FIG. 6 (c), and the potential distribution of the pixel changed to the low gain is shown in FIG. 12 (b-4). .. The potential distribution in FIG. 12 (b-4) represents a state in which the FD capacitance CFD and the FD expansion capacitance Cex are added by setting the FD expansion transistor FDext to the ON state.

During the period tt3 of FIG. 8, the electric charge accumulated in the photoelectric conversion element PD is transferred to the FD addition capacitance CFDadd of the FD unit. The control timing of the pixel operation during the above charge transfer is as described with reference to FIG. 6 (d), and the potential distributions of the high-light pixel and the low-light pixel after the charge transfer are shown in FIG. 12 (b), respectively. -5) and FIG. 12 (b-6).

In the period tt4 of FIG. 8, the gain of the charge-voltage conversion is changed to a high gain (that is, 1 times) for performing the charge-voltage conversion using only the FD capacitance CFD. The control timing of the pixel operation when the gain is changed is as described with reference to FIG. 6 (e), and the potential distribution of the low-light pixel changed to the high gain is shown in FIG. 12 (b-7). Shown. Since the transfer transistor TX is set to the off state, when the FD expansion transistor FDext changes from the on state to the off state, the signal charge accumulated in the FD expansion capacitance Cex of the FD expansion transistor FDext is pushed out to the FD capacitance CFD. Is added.

In the present embodiment, the electric charge of the photoelectric conversion element PD is transferred to the FD unit by the operation of the transfer transistor TX, read out as a pixel signal, and discharged by being reset to the power supply voltage Vdd by the operation of the reset transistor RS. ..

In the period tt4 of the first embodiment, when the FD expansion transistor FDext changes from the on state to the off state, the signal charge accumulated in the FD expansion capacitance Cex of the FD expansion transistor FDext is returned to the FD capacitance CFD and added. Will be done. In contrast, in the period tt4 of the present embodiment, the signal charge accumulated in the FD expansion capacitance Cex is pushed out to the FD capacitance CFD and added as described above.

Since the pixel signal in FIG. 12 (b-5) is a high illuminance signal, if it is converted to a high gain, it will exceed the FD capacitance CFD and overflow. In the present embodiment, the FD expansion transistor FDext is arranged between the transfer transistor TX and the FD node 301. Therefore, for example, it is preferable to set only the potential when the reset transistor RS is set to the off state to be slightly lower (that is, to raise the voltage) than the potential when the transfer transistor TX is set to the off state. .. By setting as described above, the FD capacitance CFD can have an overflow function, and the signal charge overflowing the FD capacitance CFD can be discharged to the power supply Vdd.

In the period tt5 of FIG. 8, the photoelectric conversion element PD and the FD capacitance CFD are reset, and the signal reading operation of one line of pixels ends. The control timing of the pixel operation at the time of the above reset is as described with reference to FIG. 6 (f).

The following operations in this embodiment are the same as the operations described in the first embodiment.

-Reset operation of Fig. 6 (a) -Initial setting operation of period tr1 of Fig. 8-AD conversion of reset signal VnH of period tr2 of Fig. 8-AD conversion of reset signal VnL of period tr3 of Fig. 8-Period of Fig. Judgment operation of tr4 − AD conversion of low gain high illuminance signal VsL_high or high gain low illuminance signal VsH_low in the period tr5 of FIG. Since the charge flows only in the direction, it is less susceptible to factors such as traps that hinder the transfer of the signal charge, as compared to a configuration in which the charge returns. Therefore, a good image signal with further reduced signal unevenness can be obtained, and the image quality of the captured image can be improved.

<Modified example of the second embodiment>
A modified example of the second embodiment of the present invention will be described with reference to FIGS. 13 and 14.

FIG. 13 is a part of a timing chart showing the operation of the pixel 200 in the image sensor 12 according to the present modification, and corresponds to FIG. 6B. In FIG. 6B, the FD capacitance CFD is reset by setting the FD expansion transistor FDext and the reset transistor RS to the ON state at the same time.

In the present embodiment, since the FD expansion transistor FDext is arranged between the transfer transistor TX and the FD node 301, it is not necessary to operate the FD expansion transistor FDext when resetting the FD capacitance CFD. Therefore, in this modification, the operation is controlled as shown in FIG. 13 instead of FIG. 6 (b). That is, after the line synchronization signal Lsync becomes valid, the selection transistor SEL is turned on and the pixel signal is controlled to be output to the vertical signal line 231. At the same time, the FD capacitance CFD is reset by setting the reset transistor RS to the ON state. After that, by setting the reset transistor RS to the off state, the reset operation of the FD capacitance CFD is terminated.

FIG. 14 is a part of a schematic explanatory view of the reading operation of the pixel 200 in the image sensor 12 according to the present modification, and corresponds to FIG. 12 (b-2). In FIG. 12 (b-2), it is not necessary to set the FD expansion transistor FDext to the ON state when resetting the FD capacitance CFD.

Therefore, in this modification, the timing of pixel operation is controlled according to FIG. 13B described above in the period tt1 of FIG. That is, the FD expansion transistor FDext remains off. FIG. 14 (b-2) is a potential distribution diagram of the pixels at the time of resetting the FD capacitance CFD in the modified example. The potential distribution diagram of the pixels after the reset is shown in FIG. 12 (b-3) described in the second embodiment.

According to the above configuration, since the FD capacitance CFD is reset only by switching the reset transistor RS on / off, the operating time can be shortened and the frame rate can be improved.

It should be noted that this modification can also be applied to the third embodiment described later.

<Third Embodiment>
Hereinafter, a third embodiment of the present invention will be described with reference to FIGS. 15 to 17. The description of FIGS. 1 to 3 and 5 to 7 according to the first embodiment is incorporated into the third embodiment.

FIG. 15 is a circuit diagram showing a circuit configuration of the column signal processing unit 203 of the image pickup device 12 according to the third embodiment. In the column signal processing unit 203 of the first embodiment (FIG. 4), the sample hold operation is realized by the two switch circuits 400 and 401.

In contrast, the column signal processing unit 203 of the third embodiment does not have a sample hold circuit. Therefore, the pixel signal Vsig transmitted via the vertical signal line 231 is directly input to the comparator 402.

FIG. 16 is a timing chart of the column signal processing unit 203 showing the read operation and the comparison operation in the image sensor 12 according to the third embodiment of the present invention. FIG. 16 shows a pixel signal Vsig of one line in the line-by-line operation starting from the times s04, s08, and s12 of FIG. 5, as in FIG. 8, and is input to the comparator 402. And the transition of the ramp wave Vrmp are shown.

The operation from the period tr1 to the period tt3 is the same as that of the first embodiment. By the operation in the above period, AD conversion of the high gain reset signal VnH, AD conversion of the low gain reset signal VnL, and transfer of electric charge from the photoelectric conversion element PD to the FD addition capacitance CFDadd in the period tt3 are executed. Further, in the first embodiment, when the FD capacity: the FD addition capacity = 1: 4, the determination voltage Vjd is set to 1/4 of the saturation voltage of the pixels. In the present embodiment, the determination operation based on the determination voltage Vjd is not executed, but the high illuminance signal and the low illuminance signal are distinguished based on 1/4 (= determination voltage Vjd) of the saturation voltage of the pixels. The potential map of the high-light pixel holding the high-light signal and the potential map of the low-light pixel holding the low-light signal are FIGS. 7 (b-5) and 7 (b-6), respectively. ..

In the period tr51, the low gain pixel signal VsL is AD-converted. That is, the low gain low illuminance signal VsL_low or the low gain high illuminance signal VsL_high is AD-converted by being compared with the lamp wave G1 generated in the period tr51.

The comparator 402 outputs a comparison signal indicating the result of comparing the pixel signal Vsig and the lamp wave G1 in the period tr51. Regarding the low gain low illuminance signal VsL_low, the count value csL_low at the timing when the comparison signal from the comparator 402 is inverted (the time when the period tsL_low has elapsed) is input to the arithmetic circuit 405. Regarding the low gain high illuminance signal VsL_high, the count value csL_high at the timing when the comparison signal from the comparator 402 is inverted (the time when the period tsL_high has elapsed) is input to the arithmetic circuit 405.

As described above, the gains of the low gain pixel signal VsL and the low gain reset signal VnL at the time of charge-voltage conversion are 1/4 times. Therefore, the arithmetic circuit 405 multiplies the value obtained by subtracting the count value cnL of the low gain reset signal VnL from the count value csL_low of the low gain low illuminance signal VsL_low by four to make the low gain low illuminance signal equivalent to high gain. Store as a converted digital value. Similarly, the arithmetic circuit 405 divides the value obtained by subtracting the count value cnL of the low gain reset signal VnL from the count value csL_high of the low gain high illuminance signal VsL_high by four, and makes the low gain high illuminance signal equivalent to high gain. It is stored as a digital value converted to.

In the period tt4, as in the first embodiment, the gain of the charge-voltage conversion is changed to a high gain (ie, 1x) for performing the charge-voltage conversion using only the FD capacitance CFD. As a result, the pixel signal VsH converted from low gain to high gain is directly input to the comparator 402. The potential map of the high-light pixel holding the high-light signal and the potential map of the low-light pixel holding the low-light signal are FIGS. 17 (c-2) and 7 (b-7), respectively. ..

Here, FIG. 17 (c-1) corresponds to FIG. 7 (b-5), which is a potential diagram of a pixel holding the low gain high illuminance signal VsL_high. Further, FIG. 17 (c-2) shows a potential diagram of a pixel converted from low gain to high gain, that is, a potential diagram of a pixel holding a high gain high illuminance signal VsH_high.

In the period tr52, the high gain pixel signal VsH is AD-converted. That is, the high gain low illuminance signal VsH_low or the high gain high illuminance signal VsH_high is AD-converted by being compared with the lamp wave G1 generated in the period tr52.

The comparator 402 outputs a comparison signal indicating the result of comparing the pixel signal Vsig and the lamp wave G1 in the period tr52. Regarding the high gain low illuminance signal VsH_low, the count value csH_low at the timing when the comparison signal from the comparator 402 is inverted (the time when the period tsH_low has elapsed) is input to the arithmetic circuit 405. In contrast, the high gain, high illuminance signal VsH_high overflows the FD capacitance CFD, which is beyond the range in which the linearity of charge-voltage conversion is maintained.

In the present embodiment, the amplitude of the lamp wave G1 during the tr52 period is set to match the range in which the linearity of the charge-voltage conversion of the pixel signal is maintained. Therefore, the maximum value of the lamp wave G1 is lower than the value of the overflowed high gain high illuminance signal VsH_high. As a result, the counter circuit 403 continues counting on the high gain high illuminance signal VsH_high until the lamp wave G1 reaches the maximum amplitude. When the generation of the lamp wave G1 (period tsH_high) is completed, the counter circuit 403 outputs the count value csH_high corresponding to the amplitude of the lamp wave G1 to the latch circuit 404.

Next, the arithmetic circuit 405 acquires and stores the digital signal value of the pixel signal Vsig based on the above-mentioned count value. The arithmetic circuit 405 of the column signal processing unit 203 to which the high gain low illuminance signal VsH_low is input subtracts the count value cnH of the high gain reset signal VnH from the count value csH_low of the high gain low illuminance signal VsH_low. The arithmetic circuit 405 stores the value obtained by the above subtraction in the arithmetic circuit 405 itself as a digital value of the high gain low illuminance signal VsH_low. Similarly, the arithmetic circuit 405 of the column signal processing unit 203 to which the high-gain high-intensity signal VsH_high is input subtracts the high-gain reset signal VnH count value cnH from the high-gain high-intensity signal VsH_high count value csH_high. The arithmetic circuit 405 stores the value obtained by the above subtraction in the arithmetic circuit 405 itself as a digital value of the high gain high illuminance signal VsH_high.

As described above, the AD conversion of the low gain pixel signal VsL and the high gain pixel signal VsH is executed.

In the period tt5, the photoelectric conversion element PD and the FD capacitance CFD are reset, and the signal reading operation of one line of pixels ends. In parallel with the operation of reading the pixel signal of the next row, the horizontal scanning unit 207 selects the column signal processing unit 203 for each column via the column selection line 251 to obtain the stored digitized pixel signal. It is controlled so that it is transferred to the output unit 209 via the horizontal output line 261.

Hereinafter, the signal value output from each pixel 200 will be examined.

In the first embodiment and the second embodiment, the signal value for each pixel 200 is either a high gain low illuminance signal VsH_low digital signal value or a high gain equivalent low gain high illuminance signal VsL_high digital signal value. .. The arithmetic circuit 405 of the column signal processing unit 203 outputs one of the above two digital signal values for one read pixel 200.

Therefore, in the first embodiment and the second embodiment, the high gain low illuminance signal VsH_low and the low gain high illuminance signal VsL_high corresponding to the high gain are classified based on the digital signal value corresponding to the amplitude of the lamp wave Vrmp. Combined. The high gain low illuminance signal VsH_low is a high-precision digital signal in an AD-converted state, while the low gain high illuminance signal VsL_high corresponding to high gain is a processed digital signal whose value is quadrupled. As a result, an image subjected to HDR processing four times the AD conversion accuracy is acquired.

In contrast, in the third embodiment, the signal value for each pixel 200 is both a digital signal value of the high gain pixel signal VsH and a digital signal value of the low gain pixel signal VsL corresponding to the high gain. The arithmetic circuit 405 of the column signal processing unit 203 stores both of the above two digital signal values for one read pixel 200.

Therefore, it is preferable that the arithmetic circuit 405 of the third embodiment executes at least one of the first to third HDR processes shown below.

The first HDR processing will be described. When the digital signal value of the high gain pixel signal VsH is smaller than the digital signal value corresponding to the amplitude of the high gain lamp wave, the arithmetic circuit 405 is the signal of the pixel 200 corresponding to the digital signal value of the high gain low illumination signal VsH_low. Store as a value.

On the other hand, when the digital signal value of the high gain pixel signal VsH is the digital signal value corresponding to the amplitude of the high gain ramp wave, the signal of the pixel 200 corresponding to the digital signal value of the low gain high illuminance signal VsL_high corresponding to the high gain. Store as a value. According to the above configuration, the HDR-processed image is acquired as in the first embodiment and the second embodiment.

The second HDR process will be described. Each arithmetic circuit 405 adds the digital signal value of the high gain pixel signal VsH and the digital signal value of the low gain pixel signal VsL corresponding to the high gain. In the case of this example, if the slope of the input / output characteristic in the high gain pixel signal VsH is 1 times, the slope of the input / output characteristic in the low gain pixel signal VsL is 1/4 times. Further, regarding the input / output characteristics of this example, the output for the input of 1/4 of the saturation voltage of the pixel corresponding to the determination voltage Vjd is twice the AD conversion accuracy, so that it reaches 1/4 of the saturation voltage of the pixel. The inclination to is doubled. Then, since the output with respect to the input of the saturation voltage of the pixel is five times the AD conversion accuracy, the inclination after 1/4 of the saturation voltage of the pixel is one times. According to the above configuration, an image subjected to HDR processing having 5 times the AD conversion accuracy is acquired.

The third HDR process will be described. Each arithmetic circuit 405 adds the digital signal value of the high gain pixel signal VsH and the digital signal value of the low gain pixel signal VsL. The digital signal value of the low gain pixel signal VsL is not multiplied by four. Regarding the input / output characteristics of this example, the output for an input of 1/4 of the saturation voltage of the pixel is 5/4 times the AD conversion accuracy, so the slope up to 1/4 of the saturation voltage of the pixel is 5 /. It will be quadrupled. Then, since the output with respect to the input of the saturation voltage of the pixel is twice the AD conversion accuracy, the inclination after 1/4 of the saturation voltage of the pixel is 1/4 times. According to the above configuration, an image subjected to HDR processing having twice the AD conversion accuracy is acquired.

When the arithmetic circuit 405 executes any of the HDR processing described above, the output from the arithmetic circuit 405 corresponding to the read pixels 200 becomes one.

Alternatively, the signal processing unit 13 of the image pickup apparatus 1 may execute the HDR processing. In the case of this example, the arithmetic circuit 405 outputs the digital signal value of the high gain pixel signal VsH and the digital signal value of the low gain pixel signal VsL. The signal processing unit 13 executes the above-mentioned first or second HDR processing after multiplying the digital signal value of the low gain pixel signal VsL by four. Alternatively, the signal processing unit 13 executes the above-mentioned third HDR processing without quadrupling the digital signal value of the low gain pixel signal VsL. When the signal processing unit 13 executes the first or second HDR processing, the arithmetic circuit 405 may output the digital signal value of the low gain high illuminance signal VsL_high corresponding to the high gain to the signal processing unit 13.

According to the above configuration, a wide dynamic range and high resolution accuracy in AD conversion can be realized as in the above-described embodiment. Further, since the low-light signal and the high-light signal are AD-converted using a single slope having the same waveform, a good image signal with reduced signal unevenness can be obtained, and the image quality of the captured image can be improved. ..

Further, in the above configuration, the pixel signals corresponding to the two types of gains can be continuously read out by performing the gain conversion process by the FD extension unit as in the above-described embodiment. As described above, since the reset signal and the pixel signal corresponding to the two types of gain can be read out in a common state, the image quality of the captured image can be further improved.

<Modified example of the third embodiment>
Hereinafter, a modified example of the third embodiment of the present invention will be described. In this modification, the FD extension transistor FDext is arranged between the transfer transistor TX and the FD node 301 as in the second embodiment (FIGS. 11 and 12). The circuit configuration of the pixel 200 and the pixel reading operation of this modification conform to the second embodiment. The circuit configuration of the column signal processing unit 203 and the operation of the column signal processing unit 203 of this modification conform to the third embodiment (FIGS. 15 and 16).

In the period tt4 of FIG. 16, the potential diagram of the high-intensity pixel and the low-intensity pixel when the gain of the charge-voltage conversion is changed to a high gain (that is, 1 times) for executing the charge-voltage conversion using only the FD capacitance CFD The potential diagrams are FIG. 17 (d-2) and FIG. 12 (b-7), respectively.

Here, FIG. 17 (d-1) corresponds to FIG. 12 (b-5), which is a potential diagram of a pixel holding the low gain high illuminance signal VsL_high. Further, FIG. 17 (d-2) shows a potential diagram of a pixel converted from a low gain to a high gain, that is, a potential diagram of a pixel holding a high gain high illuminance signal VsH_high.

In this modification, as described with reference to FIG. 12 (b-7) of the second embodiment, the signal charge accumulated in the FD expansion capacitance Cex of the FD expansion transistor FDext is extruded into the FD capacitance CFD. Is added. The high-gain high-illuminance signal VsH_high shown in FIG. 17 (d-2) is in a state of overflowing in excess of the FD capacitance CFD, as in the second embodiment.

As described above, the pixel signal Vsig (low gain low illuminance signal VsL_low, low gain high illuminance signal VsL_high, high gain low illuminance signal VsH_low, high gain high illuminance signal VsH_high) is read out. The arithmetic circuit 405 subtracts the corresponding reset signals VnL and VnH from the read pixel signal Vsig. After the above subtraction processing, the low gain pixel signal VsL (VsL_low, VsL_high) and the high gain pixel signal VsH (VsH_low, VsH_high) corresponding to the high gain are stored in the arithmetic circuit 405 as in the third embodiment.

According to the above configuration of the present modification, the technical effect described in the third embodiment is achieved. Further, in the pixel 200, since the electric charge flows from the photoelectric conversion element PD toward the power supply voltage Vdd in only one direction, the influence from the trap or the like that hinders the transfer of the signal charge is compared with the configuration in which the electric charge returns. Hard to receive. Therefore, a good image signal with further reduced signal unevenness can be obtained, and the image quality of the captured image can be improved.

<Fourth Embodiment>
Hereinafter, a fourth embodiment of the present invention will be described with reference to FIGS. 18 to 23. The description of FIGS. 1, 2, and 5 according to the first embodiment is incorporated into the fourth embodiment.

Generally, the image sensor 1 according to the fourth embodiment of the present invention includes an FD unit that converts a charge voltage, an FD extension unit FDext that adjusts the gain of charge voltage conversion, and an FD unit and an FD extension unit FDext. The image sensor 12 has a pixel including an FD connection portion TFD for connecting the above. By using the image sensor 12 as described above, the image sensor 1 can realize a wide dynamic range and high resolution accuracy in one shooting.

The signal processing unit 13 (FIG. 1, etc.) according to the fourth embodiment of the present invention can execute HDR processing. More specifically, for example, the signal processing unit 13 synthesizes the signal of the low-light exposure pixel and the signal of the high-light exposure pixel by using the gain value for compensating the sensitivity ratio and the weighting coefficient according to the brightness. You can do it. Alternatively, the signal processing unit 13 may select either the signal of the low-light exposure pixel or the signal of the high-light exposure pixel according to the brightness.

FIG. 18 is a circuit diagram showing a circuit configuration of pixels 200 of the image pickup device 12 according to the fourth embodiment of the present invention. As described above, in the pixel 200 of the first embodiment (FIG. 3), the FD extension transistor FDext is arranged between the FD node 301 of the FD section and the reset transistor RS. In the pixel 200 of the fourth embodiment, as shown in FIG. 18, the FD connection transistor (FD connection portion) TFD and the FD expansion transistor FDext are arranged between the FD node 301 of the FD unit and the reset transistor RS. There is.

Each pixel control line 221 of the present embodiment includes an FD connection control line pTFD in addition to the transfer control line pTX, the FD extended control line pFDext, the reset control line pRS, and the selection control line pSEL.

The FD connection transistor (FD connection) TFD is a MOS transistor in which the gate is connected to the FD connection control line pTFD, the source is connected to the FD capacitance CFD, and the drain is connected to the FD expansion transistor (FD expansion) FDext. ..

The FD expansion transistor (FD expansion unit) FDext is a MOS transistor in which the gate is connected to the FD expansion control line pFDext, the source is connected to the FD connection transistor TFD, and the drain is connected to the reset transistor (reset switch) RS.

As can be understood from the above, the pixel 200 of the present embodiment has a circuit configuration in which the FD connection transistor TFD is inserted between the FD capacitance CFD of the pixel 200 of the first embodiment and the FD expansion transistor FDext. Other circuit configurations and operations are the same as in the first embodiment (FIG. 3).

When the FD connection transistor TFD, the FD expansion transistor FDext, and the reset transistor RS are all set to the ON state, the potential of the FD node 301 is reset to the power supply voltage Vdd. On the other hand, when the FD connection transistor, the FD expansion transistor FDext, and the reset transistor RS are all in the off state, the electric charge transferred from the photoelectric conversion element PD is converted into a voltage in the FD capacitance CFD.

When the FD connection transistor TFD and the FD expansion transistor FDext are on and the reset transistor RS is off, the FD connection transistor TFD and the FD expansion transistor FDext function as a storage unit (that is, a storage capacity) capable of holding an electric charge. To do. The storage capacity obtained by adding the FD connection transistor TFD and the FD expansion transistor FDext may be hereinafter referred to as the FD expansion capacity Cex. At this time, since the above storage capacity (FD expansion capacity Cex) and FD capacity CFD are grounded in parallel with the substrate, the capacity seen from the FD node 301 is obtained by adding the FD expansion capacity Cex to the FD capacity CFD. It becomes the capacity (FD addition capacity CFDadd). Therefore, in the FD node 301, the electric charge transferred from the photoelectric conversion element PD is converted into a voltage by using the additional capacitance CFDadd which is the sum of the FD capacitance CFD and the FD expansion capacitance Cex.

FIG. 19 is a circuit diagram showing a circuit configuration of the column signal processing unit 203 of the image pickup device 12 according to the fourth embodiment of the present invention. The column signal processing unit 203 includes a comparator 402, a counter circuit 403, a latch circuit 404, and an arithmetic circuit 405. As described below, the column signal processing unit 203 functions as an AD conversion circuit.

The comparator 402 is an element that outputs a comparison result of two input signals. For example, when the magnitude relationship between the two input signals is reversed, the output signal is changed from High to Low. In the comparator 402, a vertical signal line 231 for inputting a pixel signal Vsig and a lamp wave signal line Vrmp are connected as two input signal sources. The lamp wave output by the timing unit 211 to the lamp wave signal line Vrmp is a triangular wave that gradually changes from the initial voltage. It is preferable that the amplitude of the above lamp wave has a sufficient margin with respect to the saturation amplitude of the pixel signal input to the comparator 402. The comparator 402 outputs the comparison result when the gradually changing lamp wave intersects the pixel signal.

The counter circuit 403 operates the counter based on the clock supplied from the connected counter control line pCNT. The counter circuit 403 starts the counting operation in accordance with the start of the lamp wave, and outputs the count value at the time when the signal of the comparison result from the comparator 402 is received. The output count value (discrete value) corresponds to a digitized pixel signal received by the column signal processing unit 203 via the vertical signal line 231.

The latch circuit 404 temporarily holds the count value output by the counter circuit 403, and outputs the count value held based on the control via the connected latch control line pLTC.

The arithmetic circuit 405 stores the count value output by the latch circuit 404 as a pixel digital signal based on the control via the connected arithmetic control line pCAL. In addition, the arithmetic circuit 405 outputs the digital signal of the stored pixel to the digital output line DSig based on the control via the corresponding selection line pH.

As described above, the column signal processing unit 203 constitutes an AD conversion circuit using a comparator 402, a counter circuit 403, a latch circuit 404, and a ramp wave signal line Vrmp.

Further, as described above, the control line 281 connected from the timing unit 211 to the column signal processing unit 203 includes a ramp wave signal line Vrmp, a counter control line pCNT, a latch control line pLTC, and an arithmetic control line pCAL. The column selection line 251 connected from the horizontal scanning unit 207 to the column signal processing unit 203 corresponds to the selection line pH in FIG. The horizontal output line 261 connected from the column signal processing unit 203 to the output unit 209 corresponds to the digital output line DSig in FIG.

The timing chart showing the photographing operation executed by the image pickup apparatus 1 is the same as that of the first embodiment (FIG. 5).

The pixel operation of the image pickup device 12 according to the fourth embodiment of the present invention will be described with reference to FIGS. 20 to 22. FIG. 20 is a timing chart showing the operation of the pixel 200 in the image sensor 12 according to the fourth embodiment of the present invention. The horizontal axis indicates time, and the vertical axis indicates signal on / off (high / low potential).

The line synchronization signal LSync is a synchronization signal for driving the image sensor 12 as in the above-described embodiment, and is a signal that becomes effective when the image sensor 12 falls down and triggers a predetermined pixel operation for each line. Is. The line synchronization signal Lsync is supplied so that the pixels 200 in each line from the first line to the last line in the pixel area 201 operate synchronously within one period (one cycle) of the frame synchronization signal Fsync.

Further, FIG. 20 shows the operation timings of the transfer control line pTX, the FD connection control line pTFD, the FD extended control line pFDext, the reset control line pRS, and the selection control line pSEL included in the pixel control line 221.

FIG. 20A shows the transition of the control signal in one line for executing the charge reset of the photoelectric conversion element PD for the line-by-line reset operation starting from the times s02, s06, and s10 in FIG. Following the activation of the line synchronization signal Lsync, all control lines other than the selection control line pSEL included in the pixel control line 221 are set to the ON state. As a result, the photoelectric conversion element PD is reset, and the power supply voltage Vdd is performed for the FD unit, the FD connection unit TFD, and the FD extension unit FDext.

Next, the transfer control line pTX is set to the off state and the transfer transistor TX is cut off, so that the exposure is started. After that, the FD connection control line pTFD, the FD expansion control line pFDext, and the reset control line pRS are set to the off state in order, and the FD connection transistor TFD, the FD expansion transistor FDext, and the reset transistor RS are sequentially cut off. As a result, the reset operation for the FD unit ends.

The FD connection transistor TFD other than the transfer transistor TX, the FD expansion transistor FDext, and the reset transistor RS may be left in the ON state without being interrupted. In this case, the technical effect that the electric charge overflowing from the photoelectric conversion element PD beyond the transfer transistor TX set in the off state is easily discharged to the power supply Vdd is achieved.

20 (b) to 20 (f) show the control signal in one line for executing the charge reading of the photoelectric conversion element PD for the pixel signal reading operation for each line starting from the times s04, s08, and s12 in FIG. Shows the transition. The charge reading operation of the photoelectric conversion element PD will be described below with reference to FIG.

FIG. 21 is a schematic explanatory view of the reading operation of the pixel 200 in the image sensor 12 according to the fourth embodiment of the present invention.

FIG. 21A shows the circuit configuration of the pixel 200 as in FIG. 21 (b-1) to 21 (b-7) are potential distribution diagrams along the dotted line path shown in FIG. 21 (a). Since the P side of the PN junction of the photoelectric conversion element PD is grounded, electrons are accumulated on the N side with respect to the signal load. In FIGS. 21 (b-1) to 21 (b-7), the potential is expressed with reference to electrons (negative charges). Therefore, the more electrons are accumulated with respect to the power supply voltage Vdd, the more the potential value (in the figure). (Vertical position of) becomes higher. In the charge-voltage conversion using the FD capacitance of the present embodiment, it is preferable that the conversion operation is executed within a range in which linearity is maintained in the relationship between the voltage to be the pixel signal and the transferred charge. ..

Here, the amount of charge that saturates the photoelectric conversion element PD is defined as the PD capacitance, the amount of charge that saturates the FD portion is defined as the FD capacitance CFD, and the amount of charge that saturates the FD connection portion and the FD expansion portion is defined as the FD expansion capacitance Cex. The FD expansion capacitance Cex means the amount of electric charge that can be stored in the potential (on potential) generated when the FD connection transistor TFD and the FD expansion transistor FDext are in the ON state. In the present embodiment, the amount of charge capable of maintaining the linearity of charge-voltage conversion in the FD addition capacitance CFDadd, which is the sum of the FD capacitance CFD and the FD expansion capacitance Cex, is substantially equal to the PD capacitance in which the photoelectric conversion element PD is saturated. To set. The above setting state can be expressed as PD capacity: FD addition capacity = 1: 1. FD capacity Each capacity when expressed in a ratio based on CFD is set as FD capacity: FD expansion capacity: FD addition capacity: PD capacity = 1: 3: 4: 4. Further, the conversion gain of charge-voltage conversion in the FD capacitance CFD set as described above is hereinafter expressed as 1 time (or x1) as a standardized value. As described above, since the FD addition capacity CFDadd is four times the FD capacity CFD, the conversion gain of the charge-voltage conversion in the FD addition capacity CFDadd can be expressed as 1/4 times (or x1 / 4).

As in the above-described embodiment, the set value of each capacity is not limited to the above-mentioned FD capacity: FD expansion capacity: FD addition capacity = 1: 3: 4, and the FD expansion capacity CeX is set to 1 or more. It suffices if it is done.

Similar to the above-described embodiment, in the following description, the case of charge-voltage conversion using only the FD capacity CFD is referred to as "high gain conversion", and charge-voltage conversion is performed using the FD addition capacity (= FD capacity + FDE expansion capacity). The case is referred to as "low gain conversion". Further, in the charge-voltage conversion, the voltage in a state where the FD capacitance and the FD addition capacitance are saturated is referred to as "FD saturation voltage". As described above, since the FD capacitance is included in the FD addition capacitance CFDadd, the saturation voltage of the FD capacitance and the saturation voltage of the FD addition capacitance are equal. Further, the voltage of the pixel signal corresponding to the "FD saturation voltage" is referred to as a "pixel saturation voltage".

FIG. 21 (b-1) shows the potential distribution during the exposure period after the reset operation described with reference to FIG. 20 (a). Each transistor conducts electrons when it is on, and blocks electrons as a barrier when it is off.

As shown in the figure, the on potential of the FD connection transistor TFD, the FD expansion transistor FDext, and the reset transistor RS in the on state and the off potential in the off state are set to be substantially equal to each other.

The off potential of the transfer transistor TX is set higher than the off potential of the FD connection transistor TFD, the FD expansion transistor FDext, and the reset transistor RS (that is, lower as the actual voltage). For example, when the off potential of the reset transistor RS is the potential when the reset control line pRS is 0 V (ground voltage), the off potential of the transfer transistor TX is the potential when the transfer control line pTX is a negative voltage.

The potential (depletion potential) in the state where the signal charge is not accumulated in the photoelectric conversion element PD is set higher than the on potential of the transfer transistor TX (that is, lower as the actual voltage). As a result, the signal charge can be completely transferred from the photoelectric conversion element PD to the FD unit.

In the exposure state shown in FIG. 21 (b-1), electrons are accumulated in the photoelectric conversion element PD, and the transfer transistor TX, the FD connection transistor TFD, the FD expansion transistor FDext, and the reset transistor RS are all turned off. It is set.

As described above, FIGS. 20 (b) to 20 (f) correspond to the pixel signal reading operation. FIG. 20B shows the transition of the control signal when the reset operation of the FD unit is executed. Following the activation of the line synchronization signal Lsync, the selection transistor SEL is set to the ON state, so that the pixel signal is output to the vertical signal line 231. At the same time, the FD unit is reset by setting the FD connection transistor TFD, the FD expansion transistor FDext, and the reset transistor RS to the ON state.

FIG. 21 (b-2) shows the potential distribution when the FD unit is reset to the potential of the power supply voltage Vdd by setting the FD connection transistor TFD, the FD expansion transistor FDext, and the reset transistor RS to the ON state. It shows. Since the transfer transistor TX is maintained in the off state, the photoelectric conversion element PD maintains the state of holding the electric charge. After that, when the reset transistor RS is set to the off state, the reset operation of the FD unit ends.

In the configuration in which the FD connection transistor TFD, the FD expansion transistor FDext, and the reset transistor RS are maintained in the ON state in FIG. 20A, the potential distribution in FIG. 21B-2 has already been reached in the exposure state. There is.

FIG. 21 (b-3) shows the potential distribution when only the reset transistor RS is set to the off state and the reset operation of the FD unit, the FD connection unit TFD, and the FD extension unit FDext is completed. In this state, the FD capacity CFD and the FD expansion capacity Cex are added. FIG. 21 (b-3) corresponds to a low gain conversion (that is, 1/4 times) state in which the charge voltage is converted by the FD addition capacity CFDadd which is the sum of the FD capacity CFD and the FD expansion capacity Cex. In the above low gain conversion state, the pixel signal output to the vertical signal line 231 is defined as the low gain reset signal VnL.

FIG. 20C shows the transition of the control signal when the gain changing operation in the FD unit is executed. The FD capacitance CFD and the FD expansion capacitance Cex are separated by setting the FD connection transistor TFD to the off state while the reset transistor RS is set to the off state. As a result, the FD capacitance CFD functions independently.

FIG. 21 (b-4) shows the potential distribution when the FD capacitance CFD and the FD expansion capacitance Cex are separated by setting the FD connection transistor TFD to the off state. By the above separation operation, the state transitions to the high gain conversion (that is, 1 times) state in which the charge voltage is converted by using only the FD capacitance CFD. In the above high gain conversion state, the pixel signal output to the vertical signal line 231 is defined as the high gain reset signal VnH.

FIG. 20D shows the transition of the control signal when the electric charge accumulated in the photoelectric conversion element PD is transferred to the FD unit. When the transfer transistor TX is set to the ON state, the signal charge is transferred from the photoelectric conversion element PD to the FD unit (FD capacitance CFD). After the signal charge transfer is complete, the transfer transistor TX is set to the off state.

21 (b-5) and 21 (b-6) correspond to a state in which the transfer of the signal charge from the photoelectric conversion element PD to the FD portion in the high gain state is completed. The determination voltage Vjd is lower than the potential in the off state of the FD connection transistor TFD so that the linearity of charge-voltage conversion can be maintained with respect to the FD capacitance CFD (that is, the charge amount is small and the voltage is high). ) Set.

FIG. 21 (b-5) shows the potential distribution when the potential of the pixel signal after high-gain charge-voltage conversion is applied to the transferred signal charge is equal to or lower than the determination voltage Vjd. In the above state, the pixel signal output to the vertical signal line 231 is defined as a high gain low illuminance signal VsH_low. On the other hand, FIG. 21 (b-6) shows the potential distribution when the potential of the pixel signal after the transferred signal charge is subjected to high-gain charge-voltage conversion exceeds the determination voltage Vjd. In the above state, the pixel signal output to the vertical signal line 231 is defined as a high-gain high-illuminance signal VsH_high. As shown in FIG. 21 (b-6), the high-gain high-illuminance signal VsH_high may overflow, and is not used in the processing of the present embodiment.

As shown in FIGS. 21 (b-5) and 21 (b-6), the FD expansion transistor FDext is set to the ON state. Therefore, even if the signal charge transferred to the FD unit overflows beyond the potential of the FD connection transistor TFD in the off state, the overflowed signal charge is transferred to the FD extension unit FDext as shown in FIG. 21 (b-6). accumulate. Therefore, it is suppressed that the overflowed signal charge is discharged to the power supply Vdd.

FIG. 20E shows the transition of the control signal when the gain changing operation is executed in the FD unit. By setting the FD connection transistor TFD to the ON state, the FD capacitance CFD and the FD expansion capacitance Cex are connected. As a result, the state transitions to a state in which charges can be accumulated in the FD unit, the FD connection unit TFD, and the FD extension unit FDext, that is, a low gain conversion (that is, 1/4 times) state in which the charge voltage is converted by the FD addition capacity CFDadd. To do.

In FIG. 21 (b-7), when the FD connection transistor TFD is set to the ON state in the state of FIG. 21 (b-6), charges are accumulated in the FD unit, the FD connection unit TFD, and the FD extension unit FDext. The potential distribution at the time of this is shown. Since the reset transistor RS is maintained in the off state, when the FD connection transistor TFD changes from the off state to the on state, the signal charge accumulated in the FD capacitance CFD overflows and the signal accumulated in the FD extension unit FDext. Charges are added. As described above, since the FD capacity: FD addition capacity is set to 1: 4, the potentials in the FD unit, the FD connection unit TFD, and the FD extension unit FDext are all the signal charges transferred from the photoelectric conversion element PD. It is 1/4 times the potential when the charge voltage is converted by the FD capacitance CFD. In the above state, the pixel signal output to the vertical signal line 231 is defined as a low gain high illuminance signal VsL_high.

FIG. 22 is a supplementary explanatory view of the reading operation of the pixel 200 shown in FIG.

FIG. 22 (c-1) is the same as FIG. 21 (b-5), which is a potential diagram in a high gain and low illuminance state, and is presented for comparison with FIG. 22 (c-2). FIG. 22 (c-2) is a potential diagram after the high gain low illuminance state is changed to the low gain low illuminance state. Since the FD capacity: FD addition capacity is set to 1: 4, the potential shown in FIG. 22 (c-2) is 1/4 times the potential shown in FIG. 22 (c-1). The signal charge stored in the FD capacitance CFD of FIG. 22 (c-1) is directly stored in the FD addition capacitance CFDadd in FIG. 22 (c-2). In the above state, the pixel signal output to the vertical signal line 231 is defined as a low gain low illuminance signal VsL_low.

FIG. 22 (d-1) is the same as FIG. 21 (b-6), which is a potential diagram in a high gain and high illuminance state, and is presented for comparison with FIG. 22 (d-2). FIG. 22 (d-2) is a potential diagram of the state after the overflow in FIG. 21 (b-6) is completed. In the above state, the pixel signal output to the vertical signal line 231 is defined as a high-gain high-illuminance signal VsH_high. FIG. 22 (d-2) shows the voltage at the end of overflow. Therefore, in the signal stable state, a voltage higher than the high gain high illuminance signal VsH_high is not output.

FIG. 20 (f) shows the transition of the control signal when the reset operation is executed for the photoelectric conversion element PD and the FD unit. The control signal shown in FIG. 20 (f) sets the transfer transistor TX, the FD connection transistor TFD, the FD expansion transistor FDext, and the reset transistor RS to the ON state. As a result, the photoelectric conversion element PD is reset, and the power supply voltage Vdd is performed for the FD unit, the FD connection unit TFD, and the FD extension unit FDext. After that, the transfer transistor TX, the FD connection transistor TFD, the FD expansion transistor FDext, and the reset transistor RS are set to the off state in order, so that the reset operation of the photoelectric conversion element PD and the FD unit is completed. Next, by setting the selection transistor SEL to the off state, the readable pixel 200 and the vertical signal line 231 are electrically separated from each other.

As described above, the pixel signal reading operation for one line started from the activation of the line synchronization signal Lsync is executed. After that, the operation of reading the pixel signal of the next line is started, triggered by the line synchronization signal Lsync of the next line shown in FIG. 20 (f). In parallel with the pixel signal reading operation of the next row, the horizontal scanning unit 207 selects the column signal processing unit 203 for each column via the column selection line 251 and stores the digitized pixels. The signal is controlled to be transferred to the output unit 209 via the horizontal output line 261.

FIG. 23 is a timing chart of the column signal processing unit 203 showing the read operation and the comparison operation in the image sensor 12 according to the fourth embodiment of the present invention. FIG. 23 shows the pixel signal reading operation of one line in the line-by-line operation starting from the times s04, s08, and s12 of FIG. 5, as in the case of FIGS. 8 and 16, and is input to the comparator 402. The transition of the pixel signal Vsig and the lamp wave Vrmp is shown.

In the period tr1, the operation of initializing the column signal processing unit 203 is executed. As the above initial setting, for example, clamping on the input signal of the comparator 402 is executed. More specifically, in the comparator 402, the two input signals, the pixel signal Vsig and the ramp wave signal Vrmp, are clamped as reference levels.

In the period tt1, the FD unit is reset and the gain of the charge-voltage conversion is set to a low gain (that is, 1/4 times) for executing the charge-voltage conversion using the FD addition capacitance CFDadd. The control timing of the pixel operation at the time of reset is as described with reference to FIG. 20 (b), and the potential distributions of the pixel during reset and the pixel after reset are shown in FIG. 21 (b-2), respectively. And as described with reference to FIG. 21 (b-3). The period tt1 corresponds to a read-out period of the reset signal VnL after the FD unit is reset and the reset transistor RS is set to the off state, and a signal stabilization period thereafter. The low gain reset signal VnL is input to the comparator 402 via the vertical signal line 231.

The lamp wave G1 is generated in the period tr2. The comparator 402 outputs a comparison signal indicating the result of comparing the reset signal VnL and the lamp wave G1. Then, the count value cnL at the timing when the comparison signal from the comparator 402 is inverted (the time when the period tnL has elapsed) is stored in the arithmetic circuit 405.

In period tt2, the gain of charge-voltage conversion is changed to a high gain (ie, 1x) to perform charge-voltage conversion using only the FD capacitance CFD. The control timing of the pixel operation when the gain is changed is as described with reference to FIG. 20 (c), and the potential distribution of the pixel changed to a high gain is described with reference to FIG. 21 (b-4). As explained above. The period tt2 corresponds to a period during which the low gain reset signal VnL transitions to the high gain reset signal VnH and a subsequent signal stabilization period based on the change in the conversion gain of the FD unit from low gain to high gain. The high gain reset signal VnH is input to the comparator 402 via the vertical signal line 231.

The lamp wave G1 is generated in the period tr3. The comparator 402 outputs a comparison signal indicating the result of comparing the reset signal VnH and the lamp wave G1. Then, the count value cnH at the timing when the comparison signal from the comparator 402 is inverted (the time when the period tnH has elapsed) is stored in the arithmetic circuit 405. The rate of change (slope) and the generation period of the lamp wave G1 generated in the period tr3 are substantially equal to the rate of change and the generation period of the lamp wave G1 generated in the period tr2. Therefore, the AD conversion is executed under common conditions in the period tr2 and the period tr3.

In the period tt3, the electric charge accumulated in the photoelectric conversion element PD is transferred to the FD unit. The control timing of the pixel operation during the above charge transfer is as described with reference to FIG. 20 (d), and the potential distributions of the low-light pixel and the high-light pixel after the charge transfer are shown in FIG. 21 (b), respectively. As described with reference to −5) and FIG. 22 (d-2). The period tt3 corresponds to the charge transfer period from the photoelectric conversion element PD to the FD unit and the subsequent signal stabilization period. Since the FD unit is set to high gain in this period, the high gain low illuminance signal VsH_low or the high gain high illuminance signal VsH_high is input to the comparator 402 as the pixel signal Vsig via the vertical signal line 231.

In the period tr51, the high gain pixel signal VsH is AD-converted. That is, the high gain low illuminance signal VsH_low or the high gain high illuminance signal VsH_high is AD-converted by being compared with the lamp wave G1 generated in the period tr51.

The comparator 402 outputs a comparison signal indicating the result of comparing the pixel signal Vsig and the lamp wave G1 in the period tr52. Regarding the high gain low illuminance signal VsH_low, the count value csH_low at the timing when the comparison signal from the comparator 402 is inverted (the time when the period tsH_low has elapsed) is input to the arithmetic circuit 405. In contrast, the high gain, high illuminance signal VsH_high overflows the FD capacitance CFD and therefore exceeds the determination voltage Vjd, which is the range in which the linearity of the charge-voltage conversion is maintained.

In the present embodiment, the amplitude of the lamp wave G1 in the period tr51 is set to match the determination voltage Vjd, which is a range in which the linearity of the charge-voltage conversion of the pixel signal is maintained. Therefore, the maximum value of the lamp wave G1 is lower than the value of the overflowed high gain high illuminance signal VsH_high. As a result, the counter circuit 403 continues counting on the high gain high illuminance signal VsH_high until the lamp wave G1 reaches the maximum amplitude. When the generation of the lamp wave G1 (period tsH_high) is completed, the counter circuit 403 outputs the count value csH_high corresponding to the amplitude of the lamp wave G1 to the latch circuit 404. The count value csH_high is input from the latch circuit 404 to the arithmetic circuit 405. The AD conversion count value csH_high corresponding to the high gain high illuminance signal VsH_high is equal to the AD saturation count value cmaxAD corresponding to the maximum amplitude of the lamp wave G1.

The arithmetic circuit 405 subtracts the count value cnH of the high gain reset signal from the count value csH_low of the high gain low illuminance signal and stores it in the arithmetic circuit 405 as the digital signal value DsH_low of the high gain low illuminance signal. Similarly, the arithmetic circuit 405 subtracts the count value cnH of the high gain reset signal from the count value csH_high of the high gain high illuminance signal and stores it in the arithmetic circuit 405 as the digital signal value DsH_high of the high gain high illuminance signal. Here, the saturated digital signal value (AD saturation signal value) DmaxAD in the high gain AD conversion is a value obtained by subtracting the count value cnH of the high gain reset signal from the AD saturation count value cmaxAD.

In the period tt4, the gain of the charge-voltage conversion is changed to a low gain (ie, 1/4 times) for performing the charge-voltage conversion using the FD addition capacitance CFDadd. The control timing of the pixel operation when the gain is changed is as described with reference to FIG. 20 (e), and the potential distributions of the low-light pixel and the high-light pixel changed to the low gain are shown in FIG. 22, respectively. This is as described with reference to (c-2) and FIG. 21 (b-7). The period tt4 corresponds to a period in which the high gain pixel signal VsH transitions to the low gain pixel signal VsL and a signal stabilization period thereafter based on the change in the conversion gain of the FD unit from the high gain to the low gain. Since the FD unit is set to low gain in this period, the low gain low illuminance signal VsL_low or the low gain high illuminance signal VsL_high is input to the comparator 402 as the pixel signal Vsig via the vertical signal line 231.

In the period tr52, the low gain pixel signal VsL is AD-converted. That is, the low gain low illuminance signal VsL_low or the low gain high illuminance signal VsL_high is AD-converted by being compared with the lamp wave G1 generated in the period tr52.

The comparator 402 outputs a comparison signal indicating the result of comparing the pixel signal Vsig and the lamp wave G1 in the period tr52. Regarding the low gain low illuminance signal VsL_low, the count value csL_low at the timing when the comparison signal from the comparator 402 is inverted (the time when the period tsL_low has elapsed) is input to the arithmetic circuit 405. Regarding the low gain high illuminance signal VsL_high, the count value csL_high at the timing when the comparison signal from the comparator 402 is inverted (the time when the period tsL_high has elapsed) is input to the arithmetic circuit 405.

As described above, the gains of the low gain pixel signal VsL and the low gain reset signal VnL at the time of charge-voltage conversion are 1/4 times. Therefore, the arithmetic circuit 405 subtracts the count value cnL of the low gain reset signal VnL from the count value csL_low of the low gain low illuminance signal VsL_low. Then, the value obtained by subtraction is multiplied by 4, and stored as a digital value (low gain low illuminance signal value 4 · DsL_low corresponding to high gain) obtained by converting the low gain low illuminance signal into a high gain equivalent. Similarly, the arithmetic circuit 405 subtracts the count value cnL of the low gain reset signal VnL from the count value csL_high of the low gain high illuminance signal VsL_high. Then, the value obtained by subtraction is multiplied by 4, and stored as a digital value (low gain high illuminance signal value 4 · DsL_high corresponding to high gain) obtained by converting the low gain high illuminance signal into a high gain equivalent.

As described above, the AD conversion of the low gain pixel signal VsL and the high gain pixel signal VsH is executed.

Here, the saturated digital signal value (AD saturation signal value) in the low gain AD conversion is a value obtained by subtracting the count value cnL of the low gain reset signal from the AD saturation count value corresponding to the maximum amplitude of the ramp wave G1. ..

In the present embodiment, the rate of change (slope) and generation period of the lamp wave G1 used for the low gain AD conversion are equal to the rate of change and the generation period of the lamp wave G1 used for the high gain AD conversion. The amplitude of the lamp wave G1 is equal to the determination voltage Vjd. The difference between the count value cnH of the high gain reset signal and the count value cnL of the low gain reset signal is relatively small as compared with the AD saturation count value. Therefore, since the saturated digital signal value in the high gain AD conversion and the saturated digital signal value in the low gain AD conversion are substantially equal to each other, the digital signal value obtained by the AD conversion in the saturated state is set to "AD" regardless of the gain state. It is defined as "saturation signal value DmaxAD". Based on the above definition, the digital signal value in the saturated state in the low gain AD conversion corresponding to the high gain takes a value four times (4. DmaxAD) of the AD saturation signal value DmaxAD.

In the period tt5, the photoelectric conversion element PD and the FD unit are reset, and the signal reading operation of one line of pixels ends. The control timing of the pixel operation at the time of reset is as described with reference to FIG. 20 (f). The period tt5 corresponds to the period of the above reset operation and the subsequent signal stabilization period. In parallel with the operation of reading the pixel signal of the next row, the horizontal scanning unit 207 selects the column signal processing unit 203 for each column via the column selection line 251 to obtain the stored digitized pixel signal. It is controlled so that it is transferred to the output unit 209 via the horizontal output line 261.

Hereinafter, the high dynamic range processing (HDR processing) in the present embodiment will be described.

The signal values for each pixel 200 according to the present embodiment are both the digital signal values DsH_low and DsH_high of the high gain pixel signal VsH and the digital signal values 4 · DsL_low and 4 · DsL_high of the low gain pixel signal VsL corresponding to the high gain. .. The arithmetic circuit 405 of the column signal processing unit 203 stores both of the above two digital signal values for one read pixel 200.

Therefore, it is preferable that the arithmetic circuit 405 of the fourth embodiment executes at least one of the first to fourth HDR processes shown below using the above digital signal values.

The first HDR processing will be described. When the value of the high gain pixel signal VsH is smaller than the AD saturation signal value DmaxAD, the arithmetic circuit 405 stores the high gain low illuminance signal value DsH_low as the signal value of the corresponding pixel 200.

On the other hand, in the arithmetic circuit 405, when the value of the high gain pixel signal VsH is equal to the AD saturation signal value DmaxAD at the time of high gain saturation, the signal value of the pixel 200 corresponding to the low gain high illuminance signal value 4 · DsL_high corresponding to the high gain. Remember as.

According to the above configuration, an input / output characteristic capable of outputting a saturated digital signal value of 4 and DmaxAD in a low gain AD conversion equivalent to a high gain is realized, so that an image subjected to 4 times HDR processing can be obtained. Can be obtained.

The second HDR process will be described. When the value of the high gain pixel signal VsH is equal to the AD saturation signal value DmaxAD at the time of high gain saturation, the arithmetic circuit 405 stores the low gain high illuminance signal value 4 · DsL_high corresponding to the high gain as the signal value of the corresponding pixel 200. To do. The above processing is the same as the first HDR processing.

On the other hand, when the value of the high gain pixel signal VsH is smaller than the AD saturation signal value DmaxAD, the arithmetic circuit 405 weights and adds the high gain low illuminance signal value DsH_low and the low gain low illuminance signal value 4 · DsL_low corresponding to the high gain. To do. By using the signal value Y (HDR) obtained by weighting addition and the weighting coefficient α (0 ≦ α ≦ 1), it can be mathematically expressed as the following equation (1).

Y (HDR) = (1-α) ・ DsH_low + α ・ 4 ・ DsL_low …… Equation (1)
The weighting coefficient α is adjusted to 0 when the input in the HDR processing is 0, and is adjusted to 1 when the input in the HDR processing is the AD saturation signal value DmaxAD at the time of high gain saturation. Further, when the input in the HDR processing is larger than 0 and smaller than the AD saturation signal value DmaxAD, the weighting coefficient α is adjusted according to the high gain low illuminance signal value DsH_low (for example, proportionally).

According to the above configuration, since the weighting addition is executed according to the magnitude of the input in the HDR processing, a gentle transition between the high gain low illuminance signal value DsH_low and the low gain low illuminance signal value 4 · DsL_low corresponding to the high gain It is realized and the discomfort of the image is suppressed. In addition, as with the first HDR processing, input / output characteristics that enable output up to the saturated digital signal value of 4 and DmaxAD in low gain AD conversion equivalent to high gain are realized, so HDR processing four times as much. You can get the image with.

In the second HDR processing described above, the weighting coefficient α may be adjusted to 0 when the input in the HDR processing exceeds 0 and is in the range of less than 1/2 of the AD saturation signal value DmaxAD. When the weighting coefficient α is in the range of more than 1/2 of the AD saturation signal value DmaxAD and less than the AD saturation signal value DmaxAD in the HDR processing, it follows the high gain low illumination signal value DsH_low (for example, to be proportional). It may be adjusted to a value greater than 0 and less than 1. According to the above configuration, since the signal with high resolution accuracy by the high gain AD conversion is maintained on the low illuminance side, it is possible to suppress the deterioration of the image quality on the low illuminance side.

The third HDR process will be described. Each arithmetic circuit 405 adds the value of the high gain pixel signal VsH and the value of the low gain pixel signal VsL corresponding to the high gain. More specifically, it is as follows.

When the input in the HDR processing is less than the AD saturation signal value DmaxAD, the arithmetic circuit 405 adds the high gain low illuminance signal value DsH_low and the low gain low illuminance signal value 4 · DsL_low corresponding to the high gain. At this time, if the slope of the input / output characteristics of the high gain pixel signal is multiplied by 1, the slope of the input / output characteristics of the low gain pixel signal corresponding to the high gain is also multiplied by 1, so that the slope of the input / output characteristics after the above addition is also multiplied by 1. Is double. When the input in the HDR processing is the AD saturation signal value DmaxAD, the value after the HDR processing is twice the AD saturation signal value DmaxAD (2. DmaxAD).

When the input in HDR processing exceeds the AD saturation signal value DmaxAD and is less than the low gain AD saturation signal value 4 · DmaxAD corresponding to the high gain, the high gain high illuminance signal value DsH_high and the low gain high illuminance signal value 4 · corresponding to the high gain DsL_high is added. At this time, while the high gain high illuminance signal value DsH_high is fixed to the AD saturation signal value DmaxAD, the slope of the input / output characteristics of the low gain pixel signal corresponding to the high gain remains 1 times, so that after the above addition. The slope of the input / output characteristics is 1 time. Further, when the input in the HDR processing is a low gain AD saturation signal value 4 · DmaxAD corresponding to a high gain, the value after the HDR processing is 5 times (5 · DmaxAD) of the AD saturation signal value DmaxAD. According to the above configuration, an image subjected to HDR processing having 5 times the AD conversion accuracy is acquired.

The fourth HDR process will be described. Generally, in this process, the value of the low gain pixel signal VsL is used as it is without being quadrupled. Each arithmetic circuit 405 adds the value of the high gain pixel signal VsH and the value of the low gain pixel signal VsL. More specifically, it is as follows.

When the input in the HDR processing is less than the AD saturation signal value DmaxAD, the arithmetic circuit 405 adds the high gain low illuminance signal value DsH_low and the low gain low illuminance signal value DsL_low. At this time, if the slope of the input / output characteristics of the high gain pixel signal is 1 times, the slope of the input / output characteristics of the low gain pixel signal corresponding to the high gain is 1/4 times, so that the input / output characteristics after the above addition The slope of is 5/4 times. When the input in the HDR processing is the AD saturation signal value DmaxAD, the value after the HDR processing is 5/4 times the AD saturation signal value DmaxAD ((5/4) · DmaxAD).

When the input in HDR processing exceeds the AD saturation signal value DmaxAD and is less than 4 times the AD saturation signal value 4 · DmaxAD, the arithmetic circuit 405 adds the high gain high illuminance signal value DsH_high and the low gain high illuminance signal value DsL_high. To do. At this time, while the high gain high illuminance signal value DsH_high is fixed to the AD saturation signal value DmaxAD, the slope of the input / output characteristics of the low gain pixel signal remains 1/4 times, so that the input / output after the above addition is performed. The slope of the characteristic is 1/4 times. Further, when the input in the HDR processing is the AD saturation signal value 4 · DmaxAD which is 4 times, the value after the HDR processing is twice the AD saturation signal value DmaxAD (2 · DmaxAD). According to the above configuration, an image subjected to HDR processing having twice the AD conversion accuracy is acquired.

When the arithmetic circuit 405 executes any of the HDR processing described above, the output from the arithmetic circuit 405 corresponding to the read pixels 200 becomes one. Which HDR process is to be executed may be determined based on a setting by the user, or may be automatically determined based on parameters such as imaging conditions.

Alternatively, the signal processing unit 13 of the image pickup apparatus 1 may execute the HDR processing. In the case of this example, the arithmetic circuit 405 outputs the digital signal value of the high gain pixel signal VsH and the digital signal value of the low gain pixel signal VsL (value not multiplied by 4). The signal processing unit 13 executes the above-mentioned first, second, or third HDR processing after multiplying the digital signal value of the low gain pixel signal VsL by four. Alternatively, the signal processing unit 13 executes the above-mentioned fourth HDR processing by using the digital signal value of the low gain pixel signal VsL as it is without quadrupling it. When the signal processing unit 13 executes the first, second, or third HDR processing, the arithmetic circuit 405 may output the digital signal value of the pixel signal corresponding to the high gain to the signal processing unit 13.

In the first to third HDR processing described above, the value of the low gain pixel signal VsL (DsL_low, DsL_high) is quadrupled to convert it to a value corresponding to high gain. An error diffusion method may be applied in order to reduce the quantization error at the value of the low gain pixel signal VsL corresponding to the high gain. For example, any one of 0, 1, 2, and 3 selected using a random number may be added to the value of the low gain pixel signal VsL corresponding to the high gain after conversion. The error diffusion by the above random number addition may be executed by either the arithmetic circuit 405 or the signal processing unit 13. According to the above configuration, the quantization error of the low gain pixel signal VsL corresponding to the high gain is reduced, and the image quality of the image after the HDR processing can be improved.

In the above HDR processing, the gain ratio of the high gain AD conversion and the low gain AD conversion is four times, but any gain ratio can be adopted. By setting the ratio of the FD capacitance CFD and the FD addition capacitance CFDadd to 1: n, the gain ratio can be set to n times.

According to the configuration of the present embodiment described above, a wide dynamic range (particularly, a wide dynamic range in high-light pixels) and high resolution accuracy (particularly, high resolution accuracy in low-light pixels) in AD conversion can be realized. In addition, since the low-light signal and the high-light signal are AD-converted using a single slope (lamp wave) having the same waveform, a good image signal with reduced signal unevenness can be obtained, and the image quality of the captured image is improved. Can be made to. In addition, since the shooting operation is completed by one exposure process, the effect that the moving body in the image does not blur even if the HDR process is performed is achieved.

Further, according to the configuration of the present embodiment, in the reading of the reset signal of the FD unit prior to the reading of the signal charge of the photoelectric conversion element PD, the low gain reset signal is converted into the high gain reset signal to obtain two types of gain. The corresponding reset signal can be read continuously. Similarly, in reading the signal charge of the photoelectric conversion element PD, the pixel signals corresponding to the two types of gain can be continuously read by converting the high gain pixel signal into the low gain pixel signal. Further, since the reset signal and the pixel signal corresponding to the two types of gain can be read out in a common state, the image quality of the captured image can be further improved.

Further, in the gain control using the FD connection portion TFD and the FD extension portion FDext of the present embodiment described above, the electric charge can be completely transferred, so that the generation of noise is remarkably suppressed. In addition, in the configuration of the present embodiment, since the high gain reset signal and the high gain pixel signal are continuously read out, the gain is not changed. Therefore, it is possible to suppress the generation of slight noise due to the gain change in the low illuminance range (for example, the range of less than 1/4 of the saturation voltage of the pixel), so that the image quality of the captured image can be further improved.

<Fifth Embodiment>
Hereinafter, a fifth embodiment of the present invention will be described with reference to FIGS. 24 to 26. The description of FIGS. 1, 2, and 5 according to the first embodiment and the description of FIGS. 18 and 20 to 22 according to the fourth embodiment are incorporated into the fifth embodiment.

In the fourth embodiment, after the high gain pixel signals VsH_low and VsH_high are AD-converted, the charge-voltage conversion gain is changed to the low gain state, and then the low-gain pixel signals VsL_low and VsL_high are AD-converted.

In contrast, in the fifth embodiment, after the signal charge is read out to the FD unit in the high gain state, it is determined whether the signal is a low illuminance signal or a high illuminance signal based on the determination voltage Vjd, and the signal charge is high. The gain low light signal VsH_low is selected. Next, the charge-voltage conversion gain is changed from the high gain state to the low gain state, and the low gain high illuminance signal VsL_high and the high gain low illuminance signal VsH_low are converted into digital signals by one AD conversion.

FIG. 24 is a circuit diagram showing a circuit configuration of the column signal processing unit 203 of the image pickup device 12 according to the present embodiment. Similar to the first embodiment (FIG. 4), the column signal processing unit 203 includes two switch circuits 400 and 401 in addition to the comparator 402, the counter circuit 403, the latch circuit 404, and the arithmetic circuit 405. .. As described below, the column signal processing unit 203 functions as an AD conversion circuit.

The switch circuit 400 has a sample hold operation of holding the pixel signal Vsig transmitted from the vertical signal line 231 in the sample hold capacitance CSH based on the control from the column signal processing unit 203 via the connected switch control line pSwS. To control. The switch circuit 400 conducts when the control signal supplied from the switch control line pSwS is High (turns on), and shuts off when the control signal is Low (turns off).

The switch circuit 401 controls the sample hold operation of holding the pixel signal Vsig transmitted from the vertical signal line 231 in the sample hold capacitance CSH based on the control from the comparator 402 via the connected switch control line pSwH. To do. The switch circuit 401 conducts when the control signal supplied from the switch control line pSwH is High (turns on), and shuts off when the control signal is Low (turns off).

The comparator 402 is an element that outputs a comparison result of two input signals. For example, when the magnitude relationship between the two input signals is reversed, the output signal is changed from High to Low. A sample hold capacitance CSH and a ramp wave signal line Vrmp are connected to the comparator 402 as two input signal sources.

Further, the comparator 402 can output a switching signal to the switch control line pSwH that controls the sample hold operation for each column based on the comparison result between the determination voltage Vjd and the pixel signal Vsig. In the present embodiment, the comparator 402 sets the switch circuit 401 to the ON state when the voltage (pixel voltage) of the pixel signal Vsig is larger than the determination voltage Vjd. As a result, the pixel signal Vsig is maintained in a state in which it can be input. On the other hand, the comparator 402 sets the switch circuit 401 to the off state if the voltage of the pixel signal Vsig is smaller than the determination voltage Vjd. As a result, the pixel signal Vsig at the time of the comparison operation by the comparator 402 is held in the sample hold capacitance CSH. Details of the output of the switching signal with respect to the switch control line pSwH will be described later.

Since other configurations and operations regarding the comparator 402 are the same as those in the fourth embodiment, detailed description thereof will be omitted. Similarly, since the configuration and operation of the counter circuit 403, the latch circuit 404, and the arithmetic circuit 405 are the same as those in the fourth embodiment, detailed description thereof will be omitted.

The arithmetic circuit 405 stores the comparison result between the determination voltage Vjd and the pixel signal Vsig, and executes the signal processing operation described later.

As described above, the column signal processing unit 203 constitutes an AD conversion circuit using a comparator 402, a counter circuit 403, a latch circuit 404, and a ramp wave signal line Vrmp.

As described above, the control line 281 connected from the timing unit 211 to the column signal processing unit 203 includes a switch control line pSwS, a ramp wave signal line Vrmmp, a counter control line pCNT, a latch control line pLTC, and an arithmetic control line pCAL. Including. The column selection line 251 connected from the horizontal scanning unit 207 to the column signal processing unit 203 corresponds to the selection line pH in FIG. 24. The horizontal output line 261 connected from the column signal processing unit 203 to the output unit 209 corresponds to the digital output line DSig in FIG. 24.

The pixel readout operation and the comparison operation of the image pickup device 12 according to the fifth embodiment of the present invention will be described with reference to FIGS. 25 and 26. FIG. 25 is a timing chart of the column signal processing unit 203 showing the read operation and the comparison operation in the image sensor 12 according to the fifth embodiment of the present invention. FIG. 25 shows the operation of reading the pixel signal of one row in the operation of each row starting from the times s04, s08, and s12 of FIG. 5, and the transition of the pixel signal Vsig and the lamp wave Vrmp input to the comparator 402. Is shown. The horizontal axis (t direction) corresponds to the passage of time, and the vertical axis (V direction) corresponds to the potential based on the initial voltage of the lamp wave Vrmp.

In the period tr1, the operation of initializing the column signal processing unit 203 is executed. As the above initial setting, for example, clamping on the input signal of the comparator 402 is executed. More details are as follows. The output from the comparator 402 to the switch control line pSwH is set to High, and the switch control line pSwS is set to High. As a result, the two switch circuits 400 and 401 are set to the ON state, and the pixel signal Vsig, which is the initial state of the vertical signal line 231 is held in the sample hold capacitance CSH. At this time, in the comparator 402, the pixel signal Vsig and the lamp wave signal Vrmp, which are two input signals, are clamped as reference levels. The switch control line pSwH is maintained high until the determination period described later is reached.

In the period tt1, the FD unit is reset and the gain of the charge-voltage conversion is set to a low gain (that is, 1/4 times) for executing the charge-voltage conversion using the FD addition capacitance CFDadd. A low gain reset signal VnL is input to the sample hold capacitance CSH and the comparator 402 via the vertical signal line 231. The reset signal VnL may be held in the sample hold capacitance CSH by setting the switch control line pSwS to Low and setting the switch circuit 400 to the off state. The switch control line pSwH is maintained high and the switch circuit 401 is maintained in the on state.

The lamp wave G1 is generated in the period tr2. The comparator 402 outputs a comparison signal indicating the result of comparing the low gain reset signal VnL and the lamp wave G1. Then, the count value cnL at the timing when the comparison signal from the comparator 402 is inverted (the time when the period tnL has elapsed) is stored in the arithmetic circuit 405.

In period tt2, the gain of charge-voltage conversion is changed to a high gain (ie, 1x) to perform charge-voltage conversion using only the FD capacitance CFD. When the switch control line pSwS is set to Low in the period tt1, the signal of the vertical signal line 231 is set to the sample hold capacitance CSH by setting the switch control line pSwS to High again and setting the switch circuit 400 to the ON state. Make it inputtable.

A high gain reset signal VnH is input to the sample hold capacitance CSH and the comparator 402 via the vertical signal line 231. The reset signal VnH may be held in the sample hold capacitance CSH by setting the switch control line pSwS to Low and setting the switch circuit 400 to the off state. The switch control line pSwH is maintained high and the switch circuit 401 is maintained in the on state.

The lamp wave G1 is generated in the period tr3. The comparator 402 outputs a comparison signal indicating the result of comparing the reset signal VnH and the lamp wave G1. Then, the count value cnH at the timing when the comparison signal from the comparator 402 is inverted (the time when the period tnH has elapsed) is stored in the arithmetic circuit 405.

In the period tt3, the electric charge accumulated in the photoelectric conversion element PD is transferred to the FD unit. When the switch control line pSwS is set to Low in the period tt2, the signal of the vertical signal line 231 can be input to the sample hold capacitance CSH by setting the switch control line pSwS to High and setting the switch circuit 400 to the ON state. To. Since the FD section is set to high gain in this period, the high gain low illuminance signal VsH_low or the high gain high illuminance signal VsH_high is sent to the sample hold capacitance CSH and the comparator 402 via the vertical signal line 231 as the pixel signal Vsig. Is entered. By setting the switch control line pSwS to Low and setting the switch circuit 400 to the off state, the pixel signal having the above high gain may be held in the sample hold capacitance CSH. The switch control line pSwH is maintained high and the switch circuit 401 is maintained in the on state.

In the period tr4, the comparator 402 compares the determination voltage Vjd output to the ramp wave signal line Vrmp with the voltage of the high gain pixel signal Vsig (high gain low illuminance signal VsH_low or high gain high illuminance signal VsH_high). Judge the magnitude relationship. The period tr4 corresponds to the determination period. Hereinafter, the determination operation by the comparator 402 will be described with reference to FIG. 26.

FIG. 26 is an explanatory diagram of a determination operation executed by the column signal processing unit 203 of the image pickup device 12 according to the fifth embodiment of the present invention. In FIG. 26, for explanation, the column signal processing unit 203 to which the vertical signal line 231 to which the high-intensity signal is output is connected is on the upper side, and the column signal processing unit 203 to which the vertical signal line 231 to which the low-intensity signal is output is connected. Is shown on the bottom. The high illuminance signal is a low gain high illuminance signal VsL_high or a high gain high illuminance signal VsH_high, and the low illuminance signal is a low gain low illuminance signal VsL_low or a high gain low illuminance signal VsH_low. In FIG. 26, elements other than the sample hold circuit S & H for executing the determination operation and the comparator Comp (comparator 402) are shown in a simplified manner.

FIG. 26A shows the state of the sample hold circuit S & H immediately before the period tr4 at which the determination voltage Vjd is output. In both sample hold circuits S & H, the switch control lines pSwS and pSwH are set to High, so that the switch circuits 400 and 401 are set to the ON state. Therefore, as described above for the period tt3, the high gain high illuminance signal VsH_high and the high gain low illuminance signal VsH_low are input to the sample hold capacitance CSH and the comparator 402, respectively.

FIG. 26B shows the state of the sample hold circuit S & H in the period tr4, which is the determination period. In FIG. 26B, the comparator 402 determines the magnitude relationship between the determination voltage Vjd output to the lamp wave signal line Vrmp and the high gain pixel signal Vsig (VsH_high, VsH_low). When the switch control line pSwS is set to Low, the switch circuit 400 is set to the off state, and the high gain pixel signal Vsig (VsH_high, VsH_low) is held in the sample hold capacitance CSH.

In the comparator 402 (upper side) to which the high-gain high-intensity signal VsH_high is input, the voltage of the high-gain high-intensity signal VsH_high is equal to or higher than the determination voltage Vjd, so that the comparison result by the comparator 402 is High. The comparator 402 outputs High indicating the comparison result to the switch control line pSwH, and keeps the switch circuit 401 in the ON state.

On the other hand, in the comparator 402 (lower side) to which the high gain low illuminance signal VsH_low is input, the voltage of the high gain low illuminance signal VsH_low is smaller than the determination voltage Vjd, so the comparison result by the comparator 402 is Low. The comparator 402 outputs Low indicating the comparison result to the switch control line pSwH, and sets the switch circuit 401 to the off state.

As described above, in the period tr4 which is the determination period, the comparator 402 (Comparator Comp) outputs the signal indicating the comparison result by the comparator 402 as it is to the switch control line pSwH as a switching signal. In addition, the switch control line pSwH after the period tr4 is controlled to maintain the signal state (High or Low) until the column signal processing unit 203 is initialized in the period tr1 of the pixel signal reading of the next row. ..

When the period tr4 ends, the output of the determination voltage Vjd is stopped, so that the high gain pixel signal Vsig (VsH_high, VsH_low) exceeds the lamp wave signal Vrmp, so that the comparison result by the comparator 402 returns to High.

In the period tt4, the gain of the charge-voltage conversion is changed to a low gain (ie, 1/4 times) for performing the charge-voltage conversion using the FD addition capacitance CFDadd. When the switch control line pSwS is set to Low first, the pixel signal Vsig of the vertical signal line 231 is set to the sample hold capacity CSH by setting the switch control line pSwS to High and setting the switch circuit 400 to the ON state. Set so that it can be held in.

Here, when the high gain low illuminance signal VsH_low is input to the comparator 402 and the determination operation is executed (lower side) in the period tr4, the switch circuit 401 is set to the off state as described above. Therefore, the low gain low illuminance signal VsL_low, which is the pixel signal Vsig obtained by the low gain charge-voltage conversion, is not input to the sample hold capacitance CSH and the comparator 402. On the other hand, when the high gain high illuminance signal VsH_high is input to the comparator 402 and the determination operation is executed (upper side) in the period tr4, the switch circuit 401 is set to the ON state as described above. Therefore, the low gain high illuminance signal VsL_high, which is the pixel signal Vsig obtained by the low gain charge-voltage conversion, is input to the sample hold capacitance CSH and the comparator 402.

FIG. 26C shows a state in which a low gain pixel signal Vsig (VsL_high, VsL_low) is input to the sample hold circuit S & H via the vertical signal line 231 during the period tt4. As described above, in the period tt4, the switch control line pSwS is set to High and the switch circuit 400 is set to the ON state.

In the sample hold circuit S & H (lower side) to which the low gain low illuminance signal VsL_low is input, the switch circuit 401 is set to the off state. Therefore, the high gain low illuminance signal VsH_low held in the sample hold capacitance CSH is input to the comparator 402. On the other hand, in the sample hold circuit S & H (upper side) to which the low gain high illuminance signal VsL_high is input, the switch circuit 401 is set to the ON state. Therefore, the low-gain high-illumination signal VsL_high input to the sample-hold circuit S & H is held in the sample-hold capacitance CSH and input to the comparator 402.

After the low-gain pixel signal Vsig is input, the low-gain high-intensity signal VsL_high is held in the sample hold capacitance CSH by setting the switch control line pSwS to Low and setting the switch circuit 400 to the off state. You may. When the switch circuit 400 is set to the off state, the low gain high illuminance signal VsL_high held in the sample hold capacitance CSH is electrically disconnected from the vertical signal line 231. As a result, the low gain is similar to the high gain low illuminance signal VsH_low (lower side of FIG. 26B) that is electrically disconnected from the vertical signal line 231 and held in the sample hold capacitance CSH in the previous determination period tr4. The high illuminance signal VsL_high can be held.

The lamp wave G1 is generated in the period tr5. The low gain high illuminance signal VsL_high or the high gain low illuminance signal VsH_low held in the sample hold capacitance CSH is AD-converted by being compared with the generated lamp wave G1. Since the rate of change (slope) of the lamp wave G1 generated in the period tr5 is substantially equal to the rate of change of the lamp wave G1 generated in the period tr2 and tr3, the conditions common to the period tr2 and tr3 and the period tr5 are the same. AD conversion is executed. However, since the period tr5 has a sufficient margin with respect to the amplitude of the pixel signal, the generation period of the lamp wave G1 in the period tr5 is longer than the generation period of the lamp wave G1 in the periods tr2 and tr3. As described above, the determination voltage Vjd is lower than the potential in the off state of the FD connection transistor TFD so that the linearity of the charge voltage conversion can be maintained with respect to the FD capacitance CFD (that is, the amount of charge is small. The voltage is set high). Therefore, in the present embodiment, the high gain pixel signal VsH having a determination voltage Vjd or higher is converted into a low gain pixel signal VsL and then AD converted as a low gain high illuminance signal VsL_high. The amplitude of the lamp wave G1 in the period tr5 is set to match the determination voltage Vjd, which is a range in which the linearity of the charge-voltage conversion of the pixel signal is maintained.

The comparator 402 outputs a comparison signal indicating the result of comparing the pixel signal Vsig and the lamp wave G1 in the period tr5. Regarding the high gain low illuminance signal VsH_low, the count value csH_low at the timing when the comparison signal from the comparator 402 is inverted (the time when the period tsH_low has elapsed) is stored in the arithmetic circuit 405. Regarding the low gain high illuminance signal VsL_high, the count value csL_high at the timing when the comparison signal from the comparator 402 is inverted (the time when the period tsL_high has elapsed) is stored in the arithmetic circuit 405.

Next, the arithmetic circuit 405 acquires and stores the digital signal value of the pixel signal Vsig based on the above-mentioned count value. The arithmetic circuit 405 of the column signal processing unit 203 (lower side) to which the high gain low illuminance signal VsH_low is input subtracts the count value cnH of the high gain reset signal VnH from the count value csH_low of the high gain low illuminance signal VsH_low. The arithmetic circuit 405 stores the value obtained by the above subtraction in the arithmetic circuit 405 itself as a digital value of the high gain low illuminance signal VsH_low.

On the other hand, the arithmetic circuit 405 of the column signal processing unit 203 (upper side) to which the low-gain high-intensity signal VsL_high is input subtracts the low-gain reset signal VnL count value cnL from the low-gain high-intensity signal VsL_high count value csL_high. As described above, the gains of the low-gain high-intensity signal VsL_high and the low-gain high-intensity signal VsL_high at the time of charge-voltage conversion are 1/4 times. Therefore, the arithmetic circuit 405 multiplies the value obtained by the above subtraction by four and stores the low gain high illuminance signal VsL_high as a digital value converted to correspond to the high gain in the arithmetic circuit 405 itself.

Since the magnitude relationship between the determination voltage Vjd and the pixel signal Vsig in the period tr4 is stored in the arithmetic circuit 405 as a comparison result, the arithmetic circuit 405 selects the high gain reset signal VnH and the low gain reset signal VnL. be able to.

In the period tt5, the photoelectric conversion element PD and the FD unit are reset, and the signal reading operation of one line of pixels ends. The details of the period tt5 are the same as those in the fourth embodiment. In parallel with the operation of reading the pixel signal of the next row, the horizontal scanning unit 207 selects the column signal processing unit 203 for each column via the column selection line 251 to obtain the stored digitized pixel signal. It is controlled so that it is transferred to the output unit 209 via the horizontal output line 261.

According to the configuration of the present embodiment described above, a wide dynamic range (particularly, a wide dynamic range in high-light pixels) and high resolution accuracy (particularly, high resolution accuracy in low-light pixels) in AD conversion can be realized. This is because the pixel signal obtained by charge-voltage conversion (dual gain processing) using either of the two types of gain is AD-converted. Further, when the magnification ratio of the two types of gain is n times (for example, 4 times), an input / output characteristic is realized so that the output is n times the AD saturation signal value with respect to the input of the pixel saturation voltage. Therefore, it is possible to acquire an image subjected to n times high dynamic range (HDR) processing.

According to the configuration of the present embodiment described above, the low-light signal and the high-light signal are AD-converted in parallel (preferably at the same time) using the same single slope, so that signal unevenness is reduced. Image signals can be acquired. Therefore, the image quality of the captured image can be improved. Further, since the shooting operation is completed by one exposure process, the effect that the moving body in the image does not blur even if the HDR process is performed is achieved. In addition, since the low-light signal and the high-light signal can be AD-converted in parallel (preferably at the same time) in one process, the frame rate can be improved and timely AD conversion can be realized.

In summary, in the configuration of the present embodiment, HDR processing by one AD conversion can be realized by dual gain processing in which the gain of charge-voltage conversion is selected by the comparator according to the voltage level of the pixel signal, and the frame rate. Can also be improved.

Further, in the configuration of the present embodiment, when reading the reset signal of the FD unit, the low gain reset signal VnL is converted into the high gain reset signal VnH. By performing the above conversion process, the reset signals corresponding to the two types of gain can be continuously read out. In addition, when reading out the pixel signal corresponding to the signal charge of the photoelectric conversion element PD, the high gain pixel signal VsH is converted into the low gain pixel signal VsL. By performing the above conversion processing, pixel signals corresponding to the two types of gain can be continuously read out. As described above, since the reset signal and the pixel signal corresponding to the two types of gain can be read out in a common state, the image quality of the captured image can be further improved.

Further, as in the fourth embodiment, in the gain control using the FD connection portion TFD and the FD extension portion FDext of the present embodiment described above, the electric charge can be completely transferred, so that the generation of noise is remarkably suppressed. In addition, in the configuration of the present embodiment, since the high gain reset signal and the high gain pixel signal are continuously read out, the gain is not changed. Therefore, it is possible to suppress the generation of slight noise due to the gain change in the low illuminance range (for example, the range of less than 1/4 of the saturation voltage of the pixel), so that the image quality of the captured image can be further improved.

<Modified example of the fifth embodiment>
A modified example of the fifth embodiment of the present invention will be described with reference to FIG. 27. FIG. 27 is a circuit diagram showing a circuit configuration of the column signal processing unit 203 of the image pickup device 12 according to the modified example of the fifth embodiment.

The column signal processing unit 203 of the fifth embodiment (FIG. 24) has two switch circuits 400 and 401. The sample hold operation is realized by controlling the switch circuits 400 and 401 by the switch control lines pSwS and pSwH, respectively.

In contrast, the column signal processing unit 203 of this modification has only one switch circuit 401. The sample hold operation of this modification is realized by controlling the switch circuit 401 by the output of the AND circuit to which the switch control lines pSwS and pSwH are connected.

In the fifth embodiment, the sample hold capacitance CSH holding the low gain high illuminance signal VsL_high is electrically separated from the vertical signal line 231 by the switch circuit 400 (FIG. 24) during the AD conversion in the period tr5. .. Similarly, during the AD conversion in the period tr5, the sample hold capacitance CSH holding the high gain low illuminance signal VsH_low is electrically separated from the vertical signal line 231 by the switch circuit 401 (FIG. 24).

In contrast, in this modification, the sample hold capacitance CSH is separated from the vertical signal line 231 by a single switch circuit 401 during the AD conversion in the period tr5.

Therefore, according to the configuration of the present modification, as compared with the configuration of the fifth embodiment of FIG. 24, the state of the low gain high illuminance signal VsL_high and the state of the high gain low illuminance signal VsH_low held in the sample hold capacitance CSH. Can be closer. As a result, adverse effects such as signal unevenness on the image can be further reduced.

<Sixth Embodiment>
Hereinafter, a sixth embodiment of the present invention will be described with reference to FIG. 28. The description of FIGS. 1, 2, and 5 according to the first embodiment and the description of FIGS. 19 to 23 according to the fourth embodiment are incorporated in the sixth embodiment.

In the above-described embodiment, the FD expansion unit of the pixel 200 is configured as a gate-controlled MOS transistor (FD expansion transistor FDext), and when High is input to the gate and is in the ON state, the signal charge is the FD expansion unit. Accumulate in.

In contrast, in the pixel 200 of the sixth embodiment, the FD expansion unit (FD expansion capacitor Cext) constitutes a capacitance grounded with respect to the substrate.

FIG. 28 is a circuit diagram showing a circuit configuration of pixels 200 of the image pickup device 12 according to the sixth embodiment of the present invention. The pixel 200 of the present embodiment has a circuit configuration in which the FD expansion transistor FDext, which is an FD expansion portion in the pixel 200 of the fourth embodiment (FIG. 18), is replaced with an FD expansion capacitor Cext. Other elements are the same as in FIG.

The potential distribution of the pixel 200 of the present embodiment will be described with reference to FIG. 21. In FIGS. 21 (b-1) to 21 (b-7), the configuration in which the FD expansion transistor FDext portion is always set to the ON state corresponds to the configuration in which the FD expansion transistor FDext is replaced with the FD expansion capacitor Cext. To do.

The potential (for example, the depletion potential) in the state where the signal charge is not accumulated in the FD expansion capacitor Cext is set lower than the potential of the power supply voltage Vdd (that is, higher as the actual voltage). When the above potential is set higher than the potential of the power supply voltage Vdd (that is, lower than the actual voltage), even if the FD connection transistor TFD and the reset transistor RS are set to the ON state, the power supply voltage Vdd of the FD unit is set. This is because it cannot be reset to.

In FIG. 21 (b-2), since the potential in the state where the signal charge is not accumulated in the FD expansion capacitor Cext is lower than the potential of the power supply voltage Vdd, the FD section and the FD expansion capacitor Cext are reset to the power supply voltage Vdd. Can be done. Also in FIGS. 21 (b-3) and 21 (b-4), the FD section and the FD expansion capacitor Cext are maintained at the reset power supply voltage Vdd.

Therefore, according to the configuration of the pixel 200 of the present embodiment described above, the same operations, actions, and technical effects as those of the fourth and fifth embodiments can be realized.

Further, the charge storage capacity per unit area of the FD expansion capacitor Cext, which is the capacity grounded on the substrate, can be easily configured to be larger than the charge storage capacity per unit area of the FD expansion transistor FDext, which is becoming lower in voltage. Is possible. Therefore, by reducing the area of the FD expansion capacitor Cext and increasing the area of the photoelectric conversion element PD, it is possible to improve the characteristics such as saturation and sensitivity. On the other hand, by maintaining the area of the FD expansion capacitor Cext, it is possible to increase the magnification of the dynamic range in the HDR processing.

<Other Embodiments>
Although the preferred embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and various modifications and modifications can be made within the scope of the gist thereof.

12 Image sensor 200 pixels 202 Vertical scanning unit 203 Row signal processing unit PD photoelectric conversion element (photoelectric conversion unit)
CFD FD capacity TX transfer transistor (transfer switch)
TFD FD connection transistor (FD connection)
FDext FD expansion transistor (FD expansion part)
RS reset transistor (reset switch)
400 Switch circuit 401 Switch circuit 402 Comparator 405 Comparator circuit VnL reset signal VnH reset signal Vsig pixel signal (VsL_low, VsL_high, VsH_low, VsH_high)
Vjd judgment voltage G1 lamp wave S & H sample hold circuit

Claims (29)

An FD unit that converts the charge of the signal transferred from the photoelectric conversion unit into a voltage, and an FD expansion unit that is connected to the FD unit and functions as an expansion capacity of the FD unit by being set to the ON state, respectively. With multiple pixels arranged in a matrix
An image pickup including a plurality of column signal processing units which are commonly connected to a plurality of pixel rows including each of the plurality of the pixels arranged in the column direction and AD-convert the pixel signals supplied from the pixels. It's an element
Each of the column signal processing units
A comparator for comparing the pixel voltage of the pixel signal with the determination voltage is provided.
When the pixel voltage is smaller than the determination voltage, the first AD conversion is executed on the high gain pixel signal which is the pixel signal when the FD extension unit is in the off state.
When the pixel voltage is larger than the determination voltage, the second AD conversion is executed on the low gain pixel signal which is the pixel signal when the FD extension unit is on.
The plurality of the column signal processing units
An image pickup device characterized in that the first AD conversion and the second AD conversion are started in parallel. The image pickup device according to claim 1, wherein the first AD conversion and the second AD conversion are started at the same time in the plurality of column signal processing units. Each of the column signal processing units
The image pickup device according to claim 1 or 2, further comprising a sample hold circuit that holds the pixel voltage when the pixel voltage input to the comparator is larger than the determination voltage. An FD unit that converts the charge of the signal transferred from the photoelectric conversion unit into a voltage, and an FD expansion unit that is connected to the FD unit and functions as an expansion capacity of the FD unit by being set to the ON state, respectively. With multiple pixels arranged in a matrix
An image sensor including a vertical scanning unit that is commonly connected to a plurality of pixel rows including each of the plurality of pixels arranged in the row direction and controls the operation of the pixels.
The vertical scanning unit is
It is possible to switch between the on state and the off state of the FD expansion unit.
A first read operation for reading a high gain pixel signal from the pixel in which the FD expansion unit is off and a second read operation for reading a low gain pixel signal from the pixel in which the FD expansion unit is on are executed. An image sensor characterized by that. The fourth aspect of claim 4, wherein the vertical scanning unit executes the first read operation after resetting the FD unit, and executes the second read operation after the first read operation. Image sensor. Each of the pixels further comprises a transfer switch that controls the transfer of the signal from the photoelectric conversion unit to the FD unit.
4. The vertical scanning unit is characterized in that the signal is transferred to the FD unit and then the second read operation is executed, and the first read operation is executed after the second read operation. Alternatively, the image pickup device according to claim 5. Further, a plurality of column signal processing units are further provided, which are commonly connected to a plurality of pixel rows including the plurality of the pixels arranged in one row and AD-convert the pixel signals supplied from the pixels.
Each of the column signal processing units includes a comparator that compares the pixel voltage of the pixel signal with the determination voltage.
Based on the comparison result of the comparator with respect to the low gain pixel signal read by the second read operation after the second read operation executed after the signal is transferred to the FD unit by the transfer switch. , The high gain pixel signal read by the first read operation and the low gain pixel signal read by the second read operation are selected. Item 6. The image pickup device according to Item 6. Each of the column signal processing units
When the pixel voltage is smaller than the determination voltage, the first AD conversion is executed for the high gain pixel signal when the FD extension unit is in the off state.
The image pickup device according to claim 7, wherein when the pixel voltage is larger than the determination voltage, the second AD conversion is executed for the low gain pixel signal when the FD extension unit is in the ON state. The image pickup device according to claim 8, wherein the HDR process is executed based on the result of the first AD conversion and the result of the second AD conversion. The image pickup device according to claim 1 or 8, wherein the voltage of the lamp wave having substantially the same rate of change in both the first AD conversion and the second AD conversion is used as the determination voltage. The high gain pixel after the low gain pixel signal when the FD expansion unit is on is supplied from the pixel to the column signal processing unit and then the FD expansion unit is switched from the on state to the off state. The image pickup device according to any one of claims 1 to 3 or 7 to 10, wherein a signal is supplied from the pixel to the column signal processing unit. Claims 1 to 3 or the like, wherein a high gain reset signal when the FD extension unit is in the off state is supplied from the pixel to the column signal processing unit after the FD unit is reset. The image pickup device according to any one of claims 7 to 11. After the high gain reset signal when the FD expansion unit is in the off state is supplied to the column signal processing unit, the low gain reset signal after the FD expansion unit is switched from the off state to the on state is the pixel. The image pickup device according to claim 12, wherein the image pickup device is supplied to the row signal processing unit. The image pickup device according to any one of claims 1 to 13, wherein the FD extension unit is arranged between the FD unit and a reset switch for resetting the FD unit. The image pickup device according to any one of claims 1 to 13, wherein the FD extension unit is arranged between the photoelectric conversion unit and the FD unit. A plurality of pixels arranged in a matrix each including an FD unit that converts the charge of the signal transferred from the photoelectric conversion unit into a voltage, and an FD connection unit and an FD extension unit that are connected to the FD unit as a capacitance. ,
An image sensor including a vertical scanning unit that is commonly connected to a plurality of pixel rows including each of the plurality of pixels arranged in the row direction and controls the operation of the pixels.
The vertical scanning unit is
It is possible to switch between the on state and the off state of the FD connection portion.
A first read operation for reading a high gain pixel signal from the pixel in which the FD connection portion is off and a second read operation for reading a low gain pixel signal from the pixel in which the FD connection portion is on are executed. An image sensor characterized by that. 16. The 16th aspect of the present invention, wherein the vertical scanning unit executes the second read operation after resetting the FD unit, and executes the first read operation after the second read operation. Image sensor. Each of the pixels further comprises a transfer switch that controls the transfer of the signal from the photoelectric conversion unit to the FD unit.
16. The vertical scanning unit is characterized in that the signal is transferred to the FD unit and then the first read operation is executed, and the second read operation is executed after the first read operation. Alternatively, the image pickup device according to claim 17. Further, a plurality of column signal processing units are further provided, which are commonly connected to a plurality of pixel rows including the plurality of the pixels arranged in one row and AD-convert the pixel signals supplied from the pixels.
Each of the column signal processing units includes a comparator that compares the pixel voltage of the pixel signal with the determination voltage.
Based on the comparison result of the comparator with respect to the high gain pixel signal read by the first read operation after the first read operation executed after the signal is transferred to the FD unit by the transfer switch. The claim is characterized in that it is selected whether to hold the low gain pixel signal read by the second read operation or the high gain pixel signal read by the first read operation. Item 18. The image pickup device according to Item 18. A plurality of pixels arranged in a matrix, each of which includes an FD unit that converts the charge of a signal transferred from the photoelectric conversion unit into a voltage, and an FD connection unit and an FD extension unit that are connected to the FD unit as a capacitance. ,
An image pickup including a plurality of column signal processing units which are commonly connected to a plurality of pixel rows including each of the plurality of the pixels arranged in the column direction and AD-convert the pixel signals supplied from the pixels. It's an element
Each of the column signal processing units
A comparator for comparing the pixel voltage of the pixel signal with the determination voltage is provided.
When the pixel voltage is smaller than the determination voltage, the first AD conversion is executed on the high gain pixel signal which is the pixel signal when the FD connection portion is in the off state.
When the pixel voltage is larger than the determination voltage, the second AD conversion is executed on the low gain pixel signal which is the pixel signal when the FD connection portion is in the ON state.
The plurality of the column signal processing units
An image pickup device characterized in that the first AD conversion and the second AD conversion are started in parallel. The image pickup device according to claim 20, wherein the first AD conversion and the second AD conversion are started at the same time in the plurality of column signal processing units. Each of the column signal processing units
The image pickup device according to claim 20 or 21, further comprising a sample hold circuit that holds the pixel voltage when the pixel voltage input to the comparator is smaller than the determination voltage. The invention according to any one of claims 20 to 22, wherein the voltage of the lamp wave having substantially the same rate of change in both the first AD conversion and the second AD conversion is used as the determination voltage. Image sensor. The image pickup device according to any one of claims 16 to 23, wherein the FD connection portion is arranged between the FD portion and the FD extension portion. The image sensor according to any one of claims 1 to 24,
A synchronous control unit that controls the operation of the image sensor,
An image pickup apparatus including a signal processing unit that performs signal processing on a pixel signal supplied from the image pickup device. An FD unit that converts the charge of the signal transferred from the photoelectric conversion unit into a voltage, and an FD expansion unit that is connected to the FD unit and functions as an expansion capacity of the FD unit by being set to the ON state, respectively. With multiple pixels arranged in a matrix
An image pickup including a plurality of column signal processing units which are commonly connected to a plurality of pixel rows including each of the plurality of the pixels arranged in the column direction and AD-convert the pixel signals supplied from the pixels. It is a control method of the element
When the pixel voltage of the pixel signal is smaller than the determination voltage, the first AD conversion is executed for the high gain pixel signal which is the pixel signal when the FD extension unit is in the off state.
When the pixel voltage is larger than the determination voltage, the second AD conversion is executed for the low gain pixel signal which is the pixel signal when the FD extension unit is on.
A control method characterized in that the first AD conversion and the second AD conversion are started in parallel. An FD unit that converts the charge of the signal transferred from the photoelectric conversion unit into a voltage, and an FD expansion unit that is connected to the FD unit and functions as an expansion capacity of the FD unit by being set to the ON state, respectively. With multiple pixels arranged in a matrix
A method for controlling an image sensor, which includes a vertical scanning unit that is commonly connected to a plurality of pixel rows including a plurality of the pixels arranged in the row direction and controls the operation of the pixels.
Switching between the on state and the off state of the FD expansion unit
A first read operation for reading a high gain pixel signal from the pixel in which the FD expansion unit is off and a second read operation for reading a low gain pixel signal from the pixel in which the FD expansion unit is on are executed. A control method characterized by having a thing and. A plurality of pixels arranged in a matrix each including an FD unit that converts the charge of the signal transferred from the photoelectric conversion unit into a voltage, and an FD connection unit and an FD extension unit that are connected to the FD unit as a capacitance. ,
A method for controlling an image sensor, which includes a vertical scanning unit that is commonly connected to a plurality of pixel rows including a plurality of the pixels arranged in the row direction and controls the operation of the pixels.
Switching between the on state and the off state of the FD connection part
A first read operation for reading a high gain pixel signal from the pixel in which the FD connection portion is off and a second read operation for reading a low gain pixel signal from the pixel in which the FD connection portion is on are executed. A control method characterized by having a thing and. A plurality of pixels arranged in a matrix each including an FD unit that converts the charge of the signal transferred from the photoelectric conversion unit into a voltage, and an FD connection unit and an FD extension unit that are connected to the FD unit as a capacitance. ,
An image pickup including a plurality of column signal processing units which are commonly connected to a plurality of pixel rows including each of the plurality of the pixels arranged in the column direction and AD-convert the pixel signals supplied from the pixels. It is a control method of the element
When the pixel voltage of the pixel signal is smaller than the determination voltage, the first AD conversion is executed for the high gain pixel signal which is the pixel signal when the FD connection portion is in the off state.
When the pixel voltage is larger than the determination voltage, the second AD conversion is executed for the low gain pixel signal which is the pixel signal when the FD connection portion is on.
A control method characterized in that the first AD conversion and the second AD conversion are started in parallel.