JPH0936738A - Clock generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To keep high stability by constituting a control oscillation circuit so that it has high stability with respect to a phase comparator output thereby applying a locking over a wide frequency range. SOLUTION: A signal synchronized with a head switching timing is given to a terminal 110 and switches 112, 113 are closed for a prescribed period before and after the switching timing to disconnect a data phase locked loop consisting of a PC 102, a loop filter 103 and a VCO 105 to activate a center frequency lock loop for the VCO 105 consisting of a RefOSC 107, an FPC 108 and a loop filter 109. Thus, an error voltage S13 being an output of the filter 109 is given to the VCO 105 as it is and the center frequency of the VCO 105 is locked to an output frequency of the OSC 107. Thus, even during an operation period of the data phase locked loop, the center frequency of the VCO 105 is kept to be locked around the clock frequency generated by the OSC 107 to keep the stability.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generator, and more particularly to an apparatus for generating a clock phase-synchronized with a reproduced signal.

[0002]

2. Description of the Related Art PLL circuits are used for various purposes. For example, in a device for recording and reproducing a digital signal, for example, a digital video tape recorder (D-VTR), it is indispensable to generate a clock phase-synchronized with the reproduction signal when extracting data from the reproduction signal.

In this specification, a PLL circuit applied to such a D-VTR will be described as an example. FIG. 3 shows DV
FIG. 2 is a diagram illustrating a configuration of a conventional general PLL circuit used for a TR.

In the figure, a clock obtained from a reproduced signal input to an input terminal 301 is compared in phase by a phase comparator (PC) 302 with a clock C1 output from a voltage controlled oscillator (VCO) 304, and a phase comparison voltage is output. S1 is output. The high frequency component of the phase comparison voltage S1 is cut by the loop filter 303, and an error voltage S2 is generated at the output of the loop filter 303. The frequency of the clock C1, which is the output of the voltage controlled oscillator (VCO) 304, is controlled by the error voltage S2.

With the above configuration, the PLL circuit can output to the output terminal 305 a clock C1 synchronized in phase with the clock component of the reproduction signal, and data is extracted from the reproduction signal according to this clock. .

[0006]

When the above-described PLL circuit is used to form a clock for extracting data of a D-VTR, it is necessary to widen a lock range so as to lock over a wide frequency range. This is the case when performing playback while transporting the tape at a speed different from that at the time of standard recording and playback, for example, so-called special playback (cue, review, etc.)
This is because the frequency of the clock component in the reproduced signal changes when performing reproduction in a long time mode or the like.

However, if the lock range is expanded, the PLL
The problem is that the stability of
-It has been difficult to secure a lock range over a wide frequency range while securing stability against jitter required for a VTR or the like.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a device which can be locked over a wide frequency range and can stably generate a clock.

[0009]

SUMMARY OF THE INVENTION In order to solve the conventional problems and to achieve the above object, the present invention comprises a control oscillating means for generating a clock phase-synchronized with a signal reproduced by a rotary head. In the clock generator,
A phase control loop that controls the control oscillating means based on the phase difference between the reproduction signal and the clock from the control oscillating means, and a frequency error detection based on the frequency error between the target frequency and the clock from the control oscillating means. A frequency control loop for generating a signal and controlling the control oscillation means by the frequency error detection signal, wherein the frequency control loop synchronizes with the signal synchronized with the rotation phase of the rotary head. It is configured to update the value.

(Operation) By controlling the output frequency of the reference oscillation circuit even when the frequency of the input clock is changed by the above-described configuration, the output of the phase comparator is controlled to have high stability. An oscillation circuit can be formed. This locks over a wide frequency range,
In addition, a PLL circuit having high stability can be configured.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below.

FIG. 1 shows a PLL according to an embodiment of the present invention.
It is a figure which shows the structure of a circuit, and is for forming the clock for extracting data from the reproduction signal of D-VTR.

In FIG. 1, an input terminal 101, a phase comparator (PC) 102, a loop filter 103, a voltage controlled oscillator (VCO) 105 and an output terminal 106 are a conventional PL.
The configuration is the same as that of the L circuit, and a loop configured from these is hereinafter referred to as a data phase lock loop.

Further, a reference frequency oscillator (Ref. OS
C) 107, a frequency phase comparator (FPC) 108, and a loop filter 109 are circuits for locking the center frequency of the VCO 105, and a loop including these is hereinafter referred to as a center frequency lock loop.

The PLL circuit of FIG. 1 has a data phase locked loop having the same configuration as that of the PLL circuit of FIG.
The configuration is such that a center frequency lock loop is added to control the center frequency of the CO 105 in a wide range.

As described above, a clock signal having a frequency corresponding to each mode in which the frequency of the clock component in the reproduced signal is different is generated by the reference frequency oscillator 107, and a relatively wide range (in this example, the clock component at the time of standard reproduction). Frequency ±
Locking is possible at a few percent or more).

That is, by locking the center frequency of the VCO 105 near the clock frequency corresponding to each mode, the lock range determined by the time constant of the loop filter 103 is narrowed, thereby achieving high stability. The configuration is such that it can cope with a change of about several% of the frequency of the clock component in each mode.

The operation of each unit in FIG. 1 will be described below.

A clock obtained from a reproduction signal from a reproduction head of the D-VTR is input to an input terminal 101. Here, in the case of a D-VTR, the reproduced signal is generally a signal obtained by switching a plurality of heads and reproducing the signal.
Before and after the head switching timing, there is a portion including a signal other than the original data pattern, and the reproduced signal is discontinuous at that portion.

Therefore, a signal synchronized with the head switching timing signal is input to the input terminal 110, and the switches 112 and 113 are closed for a predetermined period (including a signal other than the original pattern) before and after the head switching timing. Thus, during this period, the data phase lock loop is cut, and only the center frequency lock loop is operated effectively.

At this time, the reference frequency oscillation circuit 107 generates a clock signal having a frequency corresponding to the frequency of the clock component in the signal reproduced in each mode. This will be described in detail later. Reference frequency oscillation circuit 107
Is the clock S15 which is the output of the VCO 105.
Is compared with the frequency and phase by a frequency phase comparator (FPC) 108 to generate a comparison voltage S11. This comparison voltage S
Reference numeral 11 denotes a high-frequency component cut by a loop filter 109 composed of a resistor and a capacitor, and an error voltage S13 is generated at the output.

At this time, since the data phase lock loop is cut, the error voltage S1 is supplied to the VCO 105.
3, the center frequency of the VCO 105 is locked to the output frequency of the reference frequency oscillation circuit 107.

The reason why the FPC is used is that locking is performed in all the ranges of the VCO 105. Here, the loop filter 109 has a sample hold function, and the switch 113 is turned off (opened).
During this time, the output voltage is maintained.

As a result, the center frequency of the VCO 105 is kept locked near the clock frequency generated by the comparison frequency oscillation circuit 107 even during the operation of the data phase lock loop. Here, VCO1
05 has a wide range centered on a standard clock frequency (frequency of a clock component in a reproduced signal at the time of standard reproduction).

Now, in the portion including the original data pattern except for the period before and after the head switching in the input reproduction signal, the switches 112 and 113 are opened to turn off the center frequency lock loop, and only the data phase lock loop is turned off. Enable effective operation.

The clock in the reproduced signal input to the input terminal 101 is compared in phase with the clock S 105 output from the phase comparator 102 and the VCO 105, and the phase comparison voltage S
10 is output. The high frequency component of the phase comparison voltage S10 is cut by the loop filter 103, and an error voltage S12 is generated at the output of the loop filter 103. The error voltage S12 is output from the adder circuit 104 to the output error voltage S of the center frequency lock loop held as described above.
13 to control the frequency of the reproduction clock S15 output from the VCO 105.

Here, the time constant in the loop filter 103 is set relatively large so as to narrow the lock range in order to obtain a desired stability. At this time, the amplitude of the output error voltage S12 of the loop filter 103 is small, but as described above, the output error voltage S13 of the center frequency lock loop is added to become the input S14 of the VCO 105. It is possible to sufficiently cope with a change in the clock frequency.

The switch 111 in the loop filter 103 is used to increase the lock range slightly at the time of lock-in so as to quickly lock in, and to narrow the lock range after lock-in to achieve high stability. is there.

Next, the configuration of the comparison frequency oscillation circuit 109 will be described.

FIG. 2 shows the reference frequency oscillating circuit 107 shown in FIG.
It is a figure which shows the example of a specific structure.

The input terminal 201 receives data indicating each mode at the time of reproduction, for example, data indicating modes such as normal reproduction, fast forward reproduction, and reverse reproduction. Data indicating this mode is supplied to the data conversion table 202, and the frequency division ratio of the frequency divider 203 is set according to the data output from the data conversion table 202.

As described above, the output of the VCO 207 is frequency-divided by the frequency divider 203 according to the frequency division ratio N set in accordance with the mode, and the horizontal synchronizing signal f _H in the reproduction signal input to the input terminal 204 as a reference signal is output. , Are compared by the phase comparator 205. Accordingly, the phase comparator 205 outputs the phase comparison voltage S20. The high frequency component of the phase comparison voltage S20 is cut by the loop filter 206, and an error voltage S21 is generated at the output of the loop filter 206.

The frequency of the clock S23, which is the output of the VCO 207, is controlled by this error voltage S21. As a result, a reference clock having a frequency corresponding to each mode is output to the output terminal 208. This reference clock is F
It will be supplied to the PC 108.

According to the PLL circuit having the above configuration,
A stable clock having a frequency corresponding to each mode and a phase synchronized with a clock component in the reproduction signal is output from the output terminal 106 in FIG.

In the above-described embodiment, the control oscillation circuit has a structure in which the loop filter of the data phase lock loop and the loop filter of the center frequency lock loop are separately provided. However, the output of the PC 102 and the output of the FPC 108 are different from each other. May be added and then supplied to the VCO 105 through a loop filter.

It is also possible to increase the center frequency of the VCO 105 and form an output clock to the terminal 106 or an input clock to the FPC 108 and the PC 102 via the frequency divider.

[0037]

As is apparent from the above description, according to the present invention, the frequency range of the lockable reproduction signal can be set wide and the clock can be generated stably.

Further, since the frequency error signal is updated in synchronization with the rotation phase of the head, the frequency of the clock can be adjusted in a cycle related to the rotation cycle of the head.

Further, in the other invention of the present application, since the reference signal is set according to the mode, it becomes possible to generate a clock having an optimum frequency according to the mode.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a PLL circuit as an embodiment of the present invention.

FIG. 2 is a diagram showing a specific configuration example of the reference frequency oscillator of FIG. 1;

FIG. 3 is a diagram showing a configuration example of a conventional PLL circuit.

[Explanation of symbols]

 Reference Signs List 101 clock input terminal 102 phase comparator 103 loop filter 104 addition circuit 105 voltage controlled oscillator 106 output terminal 107 reference frequency oscillator 108 frequency phase comparator 109 loop filter 202 data conversion table 203 frequency divider 204 reference signal input terminal 205 phase comparator 206 Loop filter 207 Voltage controlled oscillator

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuyuki Tanaka 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc.

Claims (8)

[Claims] 1. A clock generator comprising a control oscillating means for generating a clock phase-synchronized with a signal reproduced by a rotary head, wherein the control oscillating means is controlled based on a phase difference between the reproduced signal and the clock. And a frequency control loop that generates a frequency error detection signal based on a frequency error between a target frequency and the clock, and controls the control oscillation means by the frequency error detection signal. The clock generator is characterized in that the value of the frequency error signal is updated in synchronization with a signal synchronized with the rotation phase of the rotary head. 2. The phase control loop according to claim 1, wherein the phase control loop detects a phase difference between the reproduction signal and the clock;
2. The clock generator according to claim 1, further comprising: a loop filter that inputs an output of the phase difference detecting unit, wherein the control oscillating unit is controlled by an output of the loop filter. 3. The frequency control loop includes: a reference signal generating unit configured to generate a reference signal corresponding to the target frequency;
It has a frequency detection means for detecting the frequency error using the reference signal and the clock, and a loop filter for filtering the output of the frequency detection means to generate the frequency error signal. The clock generation device according to Item 1. 4. A switching means for switching the reference signal according to a reproduction mode.
2. The clock generator according to claim 1. 5. The clock generator according to claim 3, further comprising a switching unit that switches the reference signal according to a reproduction speed of the reproduction signal. 6. The reproduction signal is a signal reproduced by tracing a recording medium by switching a plurality of the rotary heads, and the frequency control loop synchronizes with the switching signal of the heads to generate the frequency error signal. The clock generator according to claim 1, wherein the clock generator is updated. 7. The clock is used to extract data from the reproduced signal.
2. The clock generator according to claim 1. 8. A clock generator comprising a control oscillating means for generating a clock phase-synchronized with a reproduced signal, and a phase control loop for controlling the control oscillating means based on a phase difference between the reproduced signal and the clock. A frequency control loop that detects a frequency error between the target frequency and the clock by using a reference signal corresponding to the target frequency and the clock, and controls the control oscillation means based on the frequency error; And a control means for setting a signal to a value according to a reproduction mode.