JPH0936422A - Group iii nitride semiconductor light emitting element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the emission efficiency of a UV emission element using a group III nitride compound semiconductor. SOLUTION: An emission layer 5 is constructed of a multiple quantum well comprising a large number of barrier layers 51 of AlX2 Ga1- X2 N and well layers 52 of AlX1 Ga1- X1 N (X1<X2) laminated alternately wherein silicon and zinc are added simultaneously to all well layers 52. UV emission intensity is enhanced through pair emission at acceptor level and donor level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting device using a group III nitride semiconductor with improved efficiency of ultraviolet light emission.

[0002]

2. Description of the Related Art Conventionally, in an ultraviolet light emitting device using a Group III nitride semiconductor, InGaN or AlGaN has been used for a light emitting layer. When InGaN is used for the light emitting layer, ultraviolet light having a wavelength of 380 nm or less is obtained by band-to-band emission when the In composition ratio is 5.5% or less. When AlGaN is used for the light emitting layer, the composition ratio of Al is about 16%, zinc and silicon are added as emission centers, and ultraviolet rays having a wavelength of 380 nm are obtained by donor-acceptor pair emission. There is.

[0003]

However, the light emitting device having such a structure still has a problem that the light emitting efficiency is low. That is, when InGaN is used for the light emitting layer, the crystallinity of the light emitting layer is poor due to low temperature growth, and the light emitting efficiency is low. or,
When AlGaN is used for the light emitting layer, the light emission efficiency decreases due to dislocation due to misfit of the lattice constant.

The present invention has been made to solve the above problems, and an object thereof is to improve the luminous efficiency of an ultraviolet light emitting device using a Group III nitride compound semiconductor.

[0005]

According to a first aspect of the present invention, in a light emitting device using a group III nitride semiconductor in the light emitting layer, the light emitting layer includes a barrier layer made of Al _X2 Ga _{1 -X2} N and an Al layer. _X1 Ga
_The quantum well is composed of quantum wells in which well layers made of _1-X1 N (X1 <X2) are alternately stacked, and an acceptor impurity and a donor impurity are added to the light emitting layer. The quantum well structure may be repeated once or many times.

Further, the inventions of claims 2, 3, and 4 define how to add the acceptor impurity and the donor impurity in the well layer and the barrier layer. That is, the invention of claim 2 is such that the acceptor impurity and the donor impurity are added only to each well layer. According to the third aspect of the present invention, acceptor impurities and donor impurities are alternately added to the adjacent well layers. According to the invention of claim 4, an acceptor impurity is added to the well layer and a donor impurity is added to the barrier layer, or conversely, a donor impurity is added to the well layer or an acceptor impurity is added to the barrier layer.

According to a fifth aspect of the invention, zinc is used as the acceptor impurity and silicon is used as the donor impurity.
In the invention of claim 6, the light emitting layer is made of p-conductivity-type Al _X3 Ga _{1 -X3} N (X1 ≤ X3) with acceptor impurities added.
Layer and n-conductivity type Al _X4 Ga _1-X4 N doped with donor impurities
The structure is characterized by being sandwiched between n layers of (X1 ≤ X4).
Furthermore, in the invention of claim 7, the acceptor impurity added to the p layer is magnesium, and the donor impurity added to the n layer is silicon.

It is desirable that the molar composition ratio of Al in the light emitting layer is 15% or more and the thickness of the well layer is in the range of 50Å to 200Å. If it is less than 50Å, impurity diffusion will occur, and if it is more than 200Å, the quantum effect will not occur, which is not desirable. or,
The thickness of the barrier layer is preferably in the range of 50Å to 200Å.
If it is 50 Å or less, the efficiency of confining carriers in the well layer decreases, and if it is 200 Å or more, the quantum effect does not occur, which is not preferable. If it is 200 Å or more, the resistance becomes large in the case of non-doping, and cracking due to dislocations occurs in the case of doping, which is not desirable.
The concentration of acceptor impurities and donor impurities added to the light emitting layer is preferably in the range of 1 × 10 ¹⁷ / cm ³ to 1 × 10 ²⁰ / cm ³ . When it is 1 × 10 ¹⁷ / cm ³ or less, the luminous efficiency is lowered due to lack of emission centers, and when it is 1 × 10 ²⁰ / cm ³ or more, the crystallinity deteriorates and the Auger effect occurs, which is not desirable.

[0009]

[Advantageous Effects of the Invention] By using AlGaN, which has better crystallinity than InGaN, for the light emitting layer and using the strained superlattice of the quantum well structure for the light emitting layer, propagation of the lattice constant misfit is prevented and the well layer The crystallinity was improved, and thus the luminous efficiency was improved. In particular, the acceptor impurity and the donor impurity were added together to the well layer having good crystallinity, and the light emission efficiency of ultraviolet rays could be greatly improved by counter-emission by the acceptor level and the donor level.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment In FIG. 1, a light emitting diode 10 has a sapphire substrate 1 on which 500.degree.
An N 2 buffer layer 2 is formed. The buffer layer 2
On the top, in order, a film thickness of about 2.0 μm and an electron concentration of 2 × 10 ¹⁸ / c
High carrier concentration n ⁺ layer 3 made of m ³ silicon-doped GaN, film thickness about 1.0 μm, n layer 4 made of silicon-doped Al _0.3 Ga _0.7 N with electron concentration 2 × 10 ¹⁸ / cm ³ , total film thickness about 0.11μ
m emission layer 5, film thickness about 1.0 μm, hole concentration 5 × 10 ¹⁷ / c
m ³ , Al doped with magnesium at a concentration of 1 × 10 ²⁰ / cm ³
_A p-layer 61 made of _0.3 Ga _0.7 N, a contact layer 62 made of magnesium-doped GaN having a film thickness of about 0.2 μm, a hole concentration of 7 × 10 ¹⁷ / cm ³ and a magnesium concentration of 2 × 10 ²⁰ / cm ³ are formed. . Then, the electrode 7 made of Ni and bonded to the contact layer 62 is formed on the contact layer 62. Further, a part of the surface of the high carrier concentration n ⁺ layer 3 is exposed, and an electrode 8 made of Ni and bonded to the layer 3 is formed on the exposed portion.

As shown in FIG. 2, the detailed structure of the light emitting layer 5 includes six barrier layers 51 made of Al _0.25 Ga _0.75 N having a film thickness of about 100 Å and Al _0.2 Ga _0.8 N having a film thickness of about 100 Å. A multi-quantum well structure in which five well layers 52 composed of
The total film thickness is about 0.11 μm. Further, zinc and silicon are added to the well layer 52 at a concentration of 5 × 10 ¹⁸ / cm ³ , respectively.

Next, a method of manufacturing the light emitting diode 10 having the above structure will be described. The light emitting diode 10 is
It was manufactured by vapor phase growth by an organometallic compound vapor phase growth method (hereinafter referred to as “M0VPE”). The gas used was NH
₃ and carrier gas H ₂ or N ₂ and trimethylgallium (Ga
(CH _{3) 3)} (hereinafter referred to as "TMG") and trimethylaluminum _{(Al (CH 3) 3)} ( hereinafter referred to as "TMA") and silane (SiH ₄₎
And diethyl zinc (hereinafter referred to as "DEZ") and cyclopentadienyl magnesium _{(Mg (C 5 H 5)} 2) ( hereinafter referred to as "CP ₂ Mg").

First, a single crystal sapphire substrate 1 having a thickness of 100 to 400 μm, which is cleaned by organic cleaning and heat treatment and whose main surface is a-plane, is mounted on a susceptor placed in a reaction chamber of a M0VPE apparatus. Next, the sapphire substrate 1 was subjected to gas phase etching at a temperature of 1100 ° C. while flowing H ₂ at a flow rate of 2 liter / min at normal pressure into the reaction chamber.

[0014] Next, by lowering the temperature to 400 ° C., and H ₂
20 liter / min, NH ₃ 10 liter / min, TMA 1.8 × 10 ^-5
The buffer layer 2 of AlN was formed at a thickness of about 500Å by supplying at a mol / min. Next, the temperature of the sapphire substrate 1 is set to 1150.
° C, H ₂ at 20 liter / min, NH ₃ at 10 liter / min,
TMG was supplied at 1.7 × 10 ⁻⁴ l / min, and silane diluted to 0.86 ppm with H ₂ gas was supplied at 200 ml / min for 30 minutes to obtain a film thickness of about 2.2 μm.
[mu] m, thereby forming an electron concentration of 2 × 10 ¹⁸ / cm high carrier concentration n ⁺ layer 3 made of GaN of silicon doped ^3.

Next, the temperature of the sapphire substrate 1 is maintained at 1100 ° C., N ₂ or H ₂ is 10 liter / min, and NH ₃ is 10 liter / min.
Min, TMG 1.12 × 10 ^-4 mol / min, TMA 0.47 × 10 ^-4 mol / min, and silane diluted to 0.86 ppm with H ₂ gas at 10 × 10 ^-9 mol / min for 60 min. Then, the n layer 4 made of silicon-doped Al _0.3 Ga _0.7 N having a film thickness of about 1 μm and a concentration of 1 × 10 ¹⁸ / cm ³ was formed.

After that, the temperature of the sapphire substrate 1 is set to 1100 ° C.
And N ₂ or H ₂ at 20 liter / min, NH ₃ at 10 liter / min.
Min, TMG 1 x 10 ^-5 mol / min, TMA 0.39 x 10 ^-4 mol / min
Introduced for 3 minutes at a thickness of 100 consisting of Al _0.25 Ga _0.75 N
The barrier layer 51 was formed. Next, 20 lit N ₂ or H ₂
er / min, NH ₃ 10 liter / min, TMG 1 × 10 ^-5 mol / min
Min, TMA 0.31 × 10 ^-4 mol / min and by H ₂ gas
Silane diluted to 0.86ppm at 10 × 10 ^-9 mol / min, DEZ
Introduced for 3 minutes at 2 × 10 ^-4 mol / min, silicon and zinc with a thickness of 100 Å consisting of Al _0.2 Ga _0.8 N are 5 ×, respectively.
A well layer 52 having a concentration of 10 ¹⁸ / cm ³ was formed. By repeating such a procedure, as shown in FIG. 6, a light emitting layer 5 having a total thickness of 0.11 μm is formed by alternately stacking five layers of barrier layers 51 and well layers 52 and having a multiple quantum well structure. did.

Subsequently, the temperature is maintained at 1100 ° C. and N ₂ or H ₂
20 liter / min, NH ₃ 10 liter / min, TMG 1.12 × 10
^-4 mol / min, 0.47 × 10 ^-4 mol / min of TMA and CP ₂ Mg
Was introduced at a rate of 2 × 10 ⁻⁴ mol / min for 60 minutes, and a p-layer 6 made of magnesium (Mg) -doped Al _0.3 Ga _0.7 N with a thickness of about 1.0 μm was formed.
1 was formed. The concentration of magnesium in the p-layer 61 is 1 × 10
^{It is 20} / cm ³ . In this state, the p layer 61 is still an insulator having a resistivity of 10 ⁸ Ωcm or more.

Subsequently, the temperature was maintained at 1100 ° C. and N ₂ or H _{2 was} added.
20 liter / min, NH ₃ 10 liter / min, TMG 1.12 × 10
^-4 mol / min and CP ₂ Mg at a rate of 4 × 10 ^-4 mol / min
This was introduced for 4 minutes to form a contact layer 62 made of GaN doped with magnesium (Mg) and having a thickness of about 0.2 μm. The magnesium concentration of the contact layer 62 is 2 × 10 ²⁰ / cm ³ . In this state, the contact layer 62 still has a resistivity
It is an insulator of 10 ⁸ Ωcm or more.

In this way, a wafer having a sectional structure shown in FIG. 2 was obtained. Next, this wafer is subjected to 45 ° C. at 45 ° C.
Heat treated for minutes. By this heat treatment, the contact layer 6
2, the p-layer 61 has a hole concentration of 7 × 10 ¹⁷ / cm ³ ,
It became a p-conductivity type semiconductor with 5 × 10 ¹⁷ / cm ³ and a resistivity of 2 Ωcm and 0.8 Ωcm. Thus, a wafer having a multilayer structure was obtained.

Next, as shown in FIG. 3, the contact layer 6
A SiO ₂ layer 9 having a thickness of 2000 Å was formed on the No. ₂ layer by sputtering, and a photoresist 10 was applied on the SiO ₂ layer 9. Then, by photolithography, as shown in FIG. 3, on the contact layer 62, the photoresist 1 of the electrode formation site A ^′ for the high carrier concentration n ⁺ layer 3 is formed.
0 was removed. Next, as shown in FIG. 4, the SiO ₂ layer 9 not covered with the photoresist 10 was removed with a hydrofluoric acid-based etching solution.

Next, the contact layer 62 and the p layer 6 which are not covered with the photoresist 10 and the SiO ₂ layer 9 are formed.
1, light emitting layer 5, n layer 4, vacuum degree 0.04 Torr, high frequency power
0.44 W / cm ² and BCl ₃ gas were supplied at a rate of 10 ml / min for dry etching, and then Ar was used for dry etching. In this step, as shown in FIG. 5, a hole A for taking out the electrode for the high carrier concentration n ⁺ layer 3 was formed.

Next, Ni is vapor-deposited uniformly on the entire surface of the sample, and a photoresist is applied, a photolithography process,
Through the etching process, as shown in FIG. 1, the electrodes 8 and 7 for the high carrier concentration n ⁺ layer 3 and the contact layer 62 are formed.
Was formed. Then, the wafer treated as described above was cut into each chip to obtain a light emitting diode chip.

The light emitting device thus obtained had a driving current of 20 mA, an emission peak wavelength of 380 nm and an emission intensity of 2 mW. The luminous efficiency was 3%, which was 10 times higher than that of the conventional structure.

In the above embodiment, the barrier layer 5 of the light emitting layer 5 is used.
P layer 61 and n layer 4 having a band gap of 1 on both sides
Is formed in a double heterojunction that is smaller than the band gap. Although the double heterojunction structure is used in the above embodiment, a single heterojunction structure may be used. Further, heat treatment was used to form the p-layer,
You may make it p-type by electron beam irradiation.

Second Embodiment In the first embodiment, zinc and silicon are simultaneously added to each well layer 52. Light emitting diode 1 of second embodiment
As shown in FIG. 6, a plurality of well layers 5
20 is obtained by adding silicon and zinc alternately in order. In this structure, paired light emission by the acceptor level and the donor level becomes possible, and the luminous efficiency of ultraviolet rays is improved. The light emitting device thus obtained has a driving current of 20
With mA, the emission peak wavelength was 380 nm and the emission intensity was 5 mW.
The luminous efficiency was 7%, which was 25 times higher than that of the conventional structure.

Third Embodiment As shown in FIG. 7, the light emitting diode 200 according to the third embodiment has zinc added to all the well layers 521 and silicon added to all the barrier layers 511. In this structure, paired light emission by the acceptor level and the donor level becomes possible, and the luminous efficiency of ultraviolet rays is improved. Conversely, silicon may be added to all the well layers 521, and zinc may be added to all the barrier layers 511. The light emitting device thus obtained had a driving current of 20 mA, an emission peak wavelength of 370 nm and an emission intensity of 5 mW. This luminous efficiency is 7
%, Which is 25 times higher than that of the conventional configuration.

Fourth Embodiment In all the above embodiments, the barrier layers 51, 510,
Although magnesium is not added to 511, the p-type may be formed by heat treatment or electron beam irradiation treatment after adding magnesium. The light emitting device thus obtained had a driving current of 20 mA, an emission peak wavelength of 380 nm and an emission intensity of 10 mW. The luminous efficiency was 15%, which was 50 times higher than that of the conventional structure.

In the above embodiments, all light emitting diodes are shown as light emitting elements, but laser diodes may be used.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a configuration of a light emitting diode according to a first specific example of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of the light emitting diode of the same embodiment.

FIG. 3 is a cross-sectional view showing a manufacturing process of the light emitting diode of the embodiment.

FIG. 4 is a cross-sectional view showing a manufacturing process of the light emitting diode of the same embodiment.

FIG. 5 is a cross-sectional view showing the manufacturing process of the light emitting diode of the same embodiment.

FIG. 6 is a configuration diagram showing a configuration of a light emitting diode according to a second embodiment.

FIG. 7 is a configuration diagram showing a configuration of a light emitting diode according to a third embodiment.

[Explanation of symbols]

10, 100, 200 ... Light emitting diode 1 ... Sapphire substrate 2 ... Buffer layer 3 ... High carrier concentration n ⁺ layer 4 ... N layer 5 ... Light emitting layer 51, 510, 511 ... Barrier layer 52, 520, 521 ... Well layer 61 ... p layer 62 ... contact layer 7, 8 ... electrode

Claims (7)

[Claims] 1. A light emitting device using a Group III nitride semiconductor as a light emitting layer, wherein the light emitting layer comprises a barrier layer made of Al _X2 Ga _{1 -X2} N and an Al _X1 Ga layer.
_A group III nitride semiconductor light-emitting device comprising a quantum well in which well layers made of _1-X1 N (X1 <X2) are alternately stacked, and an acceptor impurity and a donor impurity are added to the light emitting layer. element. 2. The Group III nitride semiconductor light emitting device according to claim 1, wherein the acceptor impurity and the donor impurity are added only to each well layer of the light emitting layer. 3. The group III nitride semiconductor light emitting device according to claim 1, wherein the acceptor impurity and the donor impurity are alternately added to a well layer adjacent to the light emitting layer. 4. The well layer of the light emitting layer contains the acceptor impurity, the barrier layer of the light emitting layer contains the donor impurity, and conversely, the well layer contains the donor impurity.
The barrier layer contains the acceptor impurities,
The group III nitride semiconductor light emitting device according to claim 1, wherein the group III nitride semiconductor light emitting device is added. 5. The Group III nitride semiconductor light emitting device according to claim 1, wherein the acceptor impurity is zinc and the donor impurity is silicon. 6. The light emitting layer comprises ap layer made of p _- conductivity type Al _X3 Ga _{1 -X3} N (X1 ≤X3) doped with an acceptor impurity and an n-conductivity type Al _X4 doped with a donor impurity. Ga _1-X4 N
The group III nitride semiconductor light emitting device according to claim 1, wherein the group III nitride semiconductor light emitting device is sandwiched by an n layer composed of (X1 ≤ X4). 7. The Group III nitride according to claim 6, wherein the acceptor impurity added to the p layer is magnesium, and the donor impurity added to the n layer is silicon. Semiconductor light emitting device.