JP3727091B2 - Group 3 nitride semiconductor device - Google Patents

Group 3 nitride semiconductor device Download PDF

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Publication number
JP3727091B2
JP3727091B2 JP30825195A JP30825195A JP3727091B2 JP 3727091 B2 JP3727091 B2 JP 3727091B2 JP 30825195 A JP30825195 A JP 30825195A JP 30825195 A JP30825195 A JP 30825195A JP 3727091 B2 JP3727091 B2 JP 3727091B2
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Japan
Prior art keywords
layer
nitride semiconductor
group iii
light emitting
iii nitride
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JP30825195A
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JPH09129925A (en
Inventor
史郎 山崎
誠二 永井
正好 小池
勇 赤崎
浩 天野
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Japan Science and Technology Agency
Toyoda Gosei Co Ltd
National Institute of Japan Science and Technology Agency
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Japan Science and Technology Agency
Toyoda Gosei Co Ltd
National Institute of Japan Science and Technology Agency
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  • Recrystallisation Techniques (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Semiconductor Lasers (AREA)
  • Led Devices (AREA)

Description

【0001】
【発明の属する技術分野】
本発明は、結晶性の良い素子層を高い成長速度で得るようにした半導体素子に関する。
【0002】
【従来技術】
従来、サファイア基板上にバッファ層を形成して、そのバッファ層上にGaN から成る基底層を厚さ2〜3μmに形成し、その基底層上にAlGaInN から成るヘテロ接合の発光層を形成した発光素子が知られている。この発光素子の各層の形成は有機金属化合物気相成長法(MOVPE) により形成されている。
【0003】
【発明が解決しようとする課題】
一方、薄膜の成長方法に膜厚の制御性の良い分子線エピタキー法(MBE) が知られている。
本発明者らは、上記構造の発光素子を分子線エピタキー法(MBE) で形成した。しかし、基底層の厚さは2〜3μm必要であり、この厚さの基底層をMBE で成長させるには長時間要した。又、素子の製造速度を向上させるためには、この厚さの基底層の成長速度を速くする必要があるが、その成長速度を速くすると、基底層の結晶性が低下し、従って、基底層の上に形成される発光層の結晶性も低下した。その結果、発光輝度の高い素子は得られなかった。
【0004】
本発明は上記課題を解決するために成されたものであり、その目的は、性能の高い素子を高速で得られるようにすることである。
【0005】
【課題を解決するための手段】
本発明は、基底層を有機金属化合物気相成長法(MOVPE)により形成し、素子層を分子線エピタキー法(MBE)により形成した。このことにより、基底層を結晶性良く高速度で形成することができる。その結果、結晶性の高い基底層の上に形成される素子層の結晶性も高くなり、その成膜がMBEで行われるために膜厚の制御性も高くなり、高性能の素子を高速度で得ることができる。
【0006】
更に、基底層を厚さ2μm以上に形成したものであるので、基底層及びその上に形成される素子層の結晶性を良くすることができる。
さらに、請求項2、3、4、5の発明により、発光出力の高い発光ダイオード、レーザを得ることができる。
【0007】
【発明の実施の形態】
第1実施例
図1において、発光ダイオード10は、サファイア基板1を有しており、そのサファイア基板1上に500 ÅのAlN のバッファ層2が形成されている。そのバッファ層2の上には、順に、膜厚約2.0 μm、電子濃度2 ×1018/cm3のシリコンドープGaN から成る高キャリア濃度n+ 層3、膜厚0.10μm、電子濃度 2×1018/cm3のシリコンドープのGaN から成るn層4、全膜厚約0.07μmのInGaN の多重量子井戸から成る発光層5、膜厚約0.2 μm、ホール濃度5 ×1017/cm3、濃度1 ×1020/cm3にマグネシウムがドープされたAl0.08Ga0.92N から成るp層61、膜厚約0.2 μm、ホール濃度 7×1017/cm3、マグネシウム濃度 2×1020/cm3のマグネシウムドープのGaN から成るコンタクト層62が形成されている。そして、コンタクト層62上にはその層62に接合するNiから成る電極7が形成されている。さらに、高キャリア濃度n+ 層3の表面の一部は露出しており、その露出部上にその層3に接合するNiから成る電極8が形成されている。尚、n+ 層3は基底層であり、n層4、発光層5、p層61、コンタクト層62が素子として機能する素子層である。
【0008】
次に、この構造の発光ダイオード10の製造方法について説明する。
上記発光ダイオード10のバッファ層2と高キャリア濃度n+ 層3とは、有機金属化合物気相成長法( 以下「M0VPE 」と記す) による気相成長により製造された。MOVPE で用いられたガスは、NH3 とキャリアガスH2又はN2 とトリメチルガリウム(Ga(CH3)3)(以下「TMG 」と記す) とトリメチルアルミニウム(Al(CH3)3)(以下「TMA 」と記す) とシラン(SiH4)である。
【0009】
まず、有機洗浄及び熱処理により洗浄したa面を主面とする厚さ100 〜400 μmの単結晶のサファイア基板1をM0VPE 装置の反応室に載置されたサセプタに装着する。次に、常圧でH2を流速2 liter/分で反応室に流しながら温度1100℃でサファイア基板1を気相エッチングした。
【0010】
次に、温度を 400℃まで低下させて、H2を20 liter/分、NH3 を10 liter/分、TMA を 1.8×10-5モル/分で供給してAlN のバッファ層2が約 500Åの厚さに形成された。次に、サファイア基板1の温度を1000℃に保持し、H2を20 liter/分、NH3 を10 liter/分、TMG を 1.7×10-4ル/分、H2ガスにより0.86ppm に希釈されたシランを20×10-8mol/分で30分供給して、膜厚約2 μm、電子濃度 2×1018/cm3のシリコンドープのGaN から成る高キャリア濃度n+ 層3を形成した。
【0011】
次に、上記の層の積層の完了した基板をMBE 装置内に取り付けた。サファイア基板1の温度を660 ℃に保持し、成長速度0.2 μm/h で、膜厚約0.1 μm、濃度 2×1018/cm3にシリコンが添加されたGaN から成るn層4を形成した。
【0012】
その後、サファイア基板1の温度を660 ℃に保持し、成長速度0.1 μm/h で、膜厚約10nmのIn0.08Ga0.92N から成るバリア層51を形成した。次に、サファイア基板1の温度を同一に保持して、成長速度0.1 μm/h で、膜厚約10nmのIn0.16Ga0.84N から成るシリコンが 5×1018/cm3の濃度に添加された井戸層52を形成した。このような手順の繰り返しにより、図2に示すように、バリア層51と井戸層52とを交互に、4層と3層だけ積層した多重量子井戸構造で、全体の厚さ70nmの発光層5を形成した。
【0013】
続いて、温度を660 ℃に保持し、成長速度0.2 μm/h で膜厚約0.2 μmのマグネシウム(Mg)ドープのAl0.08Ga0.92N から成るp層61を形成した。p層61のマグネシウムの濃度は 5×1020/cm3であり、ホール濃度は 2×1018/cm3である。
【0014】
続いて、温度を660 ℃に保持し、成長速度0.2 μm/h 膜厚約0.2 μmのマグネシウム(Mg)ドープのGaN から成るコンタクト層62を形成した。コンタクト層62のマグネシウムの濃度は 5×1021/cm3であり、ホール濃度は 3×1018/cm3である。
【0015】
このようにして、図2に示す断面構造のウエハが得られた。
次に、図3に示すように、コンタクト層62の上に、スパッタリングによりSiO2層9を2000Åの厚さに形成し、そのSiO2層9上にフォトレジスト10を塗布した。そして、フォトリソグラフにより、図3に示すように、コンタクト層62上において、高キャリア濃度n+ 層3に対する電極形成部位A' のフォトレジスト10を除去した。次に、図4に示すように、フォトレジスト10によって覆われていないSiO2層9をフッ化水素酸系エッチング液で除去した。
【0016】
次に、フォトレジスト10及びSiO2層9によって覆われていない部位のコンタクト層62、p層61、発光層5、n層4を、真空度0.04Torr、高周波電力0.44W/cm2 、BCl3ガスを10 ml/分の割合で供給しドライエッチングした後、Arでドライエッチングした。この工程で、図5に示すように、高キャリア濃度n+ 層3に対する電極取出しのための孔Aが形成された。
【0017】
次に、試料の上全面に、一様にNiを蒸着し、フォトレジストの塗布、フォトリソグラフィ工程、エッチング工程を経て、図1に示すように、高キャリア濃度n+ 層3及びコンタクト層62に対する電極8,7を形成した。その後、上記の如く処理されたウエハを各チップに切断して、発光ダイオードチップを得た。
【0018】
このようにして得られた発光素子は、駆動電流20mAで、発光ピーク波長 405nm、発光強度2mWであった。この発光効率は3%であった。上記の構成と同一構成の発光ダイオードの全ての層をMBE で形成した場合に比べて発光出力は105 倍に大きくなった。
【0019】
このように本願発明では、結晶性が高く厚く形成する必要のある基底層をMOVPE 法で高速に形成し、膜厚の制御が要求される素子層はMBE 法で形成したことを特徴とする。よって、結晶性の高い基底層が高速で得られることから、その上の素子層の結晶性を低下させることなく素子の製造速度を向上させることができる。
【0020】
尚、上記実施例では、n層4にGaN を用いているが、n伝導型のAlGaN を用いても良い。さらに、p層61はなくても良い。又、発光層5の多重量子井戸構造の周期は任意であり、又、単量子井戸構造でも良い。井戸層、バリア層にはInGaN を用いたがInxGayAl1-x-yN (0≦x≦1, 0≦y≦1, 0≦x+y≦1)等の3族窒化物半導体を用いても良い。さらに、井戸層にシリコンを添加したが、他のドナー不純物でも良く、無添加でも良い。
【0021】
又、図6に示すように、バリア層513は無添加で、井戸層523にのみドナー不純物(例えば、シリコン)とアクセプタ不純物(例えば、亜鉛)を添加しても良い。又、図7に示すように、バリア層510は無添加で、井戸層520について、ドナー不純物(例えば、シリコン)とアクセプタ不純物(例えば、亜鉛)を交互に添加しても良い。さらに、図8に示すように、井戸層521にドナー不純物(例えば、シリコン)を添加し、バリア層511にアクセプタ不純物(例えば、亜鉛)を添加しても良いし、逆に、井戸層521にアクセプタ不純物を添加し、バリア層511にドナー不純物を添加しても良い。これらの不純物分布に関する特徴は、発光波長を変化させることができる。井戸層、バリア層は、n型でもp型でも半絶縁性でも良い。
【0022】
又、発光層5は、各層を厚くして量子井戸構造にはならない多重層としても良い。この場合も同様に、図6〜図7の構造が考えられる。この場合、不純物の分布のみに注目しているので、層513と層523、層510と層520、層511と層521を同一組成比としても良い。上記の不純物分布は、発光波長を変化させることができる。この場合も発光層5の各層は、n型、p型、半絶縁性であっても良い。
【0023】
さらに、発光層5は図9に示すように単層にしても良い。上記実施例では、サファイア基板を用いたがSiC 、MgAl2O4 等を用いることができる。又、バッファ層にはAlN を用いたがAlGaN 、GaN 、InAlGaN 等を用いることができる。さらに、基底層にはGaN を用いているが、InxGayAl1-x-yN等の3族窒化物半導体を用いることができる。同様に、素子層にも任意組成比のInxGayAl1-x-yN 等の3族窒化物半導体を用いることができる。MBEで成長させるとき熱処理なしにp型化できるが、成長後に熱処理を加えても良い。
【0024】
又、本発明は発光ダイオードの他、青色や紫外領域のレーザダイオード、光検出素子、その他の機能素子に応用することができる。
【図面の簡単な説明】
【図1】本発明の具体的な第1実施例に係る発光ダイオードの構成を示した構成図。
【図2】同実施例の発光ダイオードの製造工程を示した断面図。
【図3】同実施例の発光ダイオードの製造工程を示した断面図。
【図4】同実施例の発光ダイオードの製造工程を示した断面図。
【図5】同実施例の発光ダイオードの製造工程を示した断面図。
【図6】発光層の他の構造を示した断面図。
【図7】発光層の他の構造を示した断面図。
【図8】発光層の他の構造を示した断面図。
【図9】他の実施例の発光ダイオードの構成を示した構成図。
【符号の説明】
10…発光ダイオード
1…サファイア基板
2…バッファ層
3…高キャリア濃度n+
4…n層
5…発光層
61…p層
62…コンタトク層
7,8…電極
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor element in which an element layer having good crystallinity is obtained at a high growth rate.
[0002]
[Prior art]
Conventionally, a buffer layer is formed on a sapphire substrate, a base layer made of GaN is formed on the buffer layer to a thickness of 2 to 3 μm, and a heterojunction light-emitting layer made of AlGaInN is formed on the base layer. Devices are known. Each layer of the light emitting element is formed by metal organic compound vapor phase epitaxy (MOVPE).
[0003]
[Problems to be solved by the invention]
On the other hand, a molecular beam epitaxy method (MBE) having a good film thickness controllability is known as a thin film growth method.
The inventors of the present invention formed a light emitting element having the above structure by a molecular beam epitaxy method (MBE). However, the thickness of the base layer is required to be 2 to 3 μm, and it took a long time to grow the base layer having this thickness by MBE. Further, in order to improve the manufacturing speed of the device, it is necessary to increase the growth rate of the base layer of this thickness. However, if the growth rate is increased, the crystallinity of the base layer is lowered, and therefore the base layer is reduced. The crystallinity of the light emitting layer formed thereon was also lowered. As a result, an element with high emission luminance could not be obtained.
[0004]
The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a high-performance element at high speed.
[0005]
[Means for Solving the Problems]
In the present invention, the base layer is formed by metal organic compound vapor phase epitaxy (MOVPE), and the element layer is formed by molecular beam epitaxy (MBE) . As a result, the base layer can be formed at high speed with good crystallinity. As a result, the crystallinity of the element layer formed on the highly crystalline base layer is also high, and the film formation is performed by MBE, so the controllability of the film thickness is also high, and the high-performance element is high speed. Can be obtained at
[0006]
Furthermore, since it is made by forming the above thickness 2μm a group bottom layer, it is possible to improve the crystallinity of the element layer formed on the base layer and thereon.
Further, according to the second, third , fourth , and fifth inventions, a light emitting diode and a laser having a high light emission output can be obtained.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
First embodiment In Fig. 1, a light emitting diode 10 has a sapphire substrate 1, and a 500 サ フ ァ イ ア AlN buffer layer 2 is formed on the sapphire substrate 1. Of On the buffer layer 2, in turn, a film thickness of about 2.0 [mu] m, the electron concentration of 2 × 10 18 / cm high carrier concentration comprising a silicon-doped GaN of 3 n + layer 3, the thickness 0.10 .mu.m, electron concentration 2 × 10 N layer 4 made of silicon-doped GaN of 18 / cm 3 , light-emitting layer 5 made of InGaN multiple quantum well with a total film thickness of about 0.07 μm, film thickness of about 0.2 μm, hole concentration 5 × 10 17 / cm 3 , concentration P layer 61 made of Al 0.08 Ga 0.92 N doped with magnesium at 1 × 10 20 / cm 3 , with a film thickness of about 0.2 μm, hole concentration of 7 × 10 17 / cm 3 , magnesium concentration of 2 × 10 20 / cm 3 A contact layer 62 made of magnesium-doped GaN is formed. On the contact layer 62, an electrode 7 made of Ni bonded to the layer 62 is formed. Further, a part of the surface of the high carrier concentration n + layer 3 is exposed, and an electrode 8 made of Ni bonded to the layer 3 is formed on the exposed portion. The n + layer 3 is a base layer, and the n layer 4, the light emitting layer 5, the p layer 61, and the contact layer 62 are element layers that function as elements.
[0008]
Next, a method for manufacturing the light emitting diode 10 having this structure will be described.
The buffer layer 2 and the high carrier concentration n + layer 3 of the light emitting diode 10 were manufactured by vapor phase growth using a metal organic compound vapor phase growth method (hereinafter referred to as “M0VPE”). The gases used in MOVPE are NH 3 and carrier gas H 2 or N 2 , trimethylgallium (Ga (CH 3 ) 3 ) (hereinafter referred to as “TMG”) and trimethylaluminum (Al (CH 3 ) 3 ) (hereinafter referred to as “TMG”). "TMA") and silane (SiH 4 ).
[0009]
First, a single-crystal sapphire substrate 1 having a thickness of 100 to 400 μm whose main surface is a surface cleaned by organic cleaning and heat treatment is mounted on a susceptor mounted in a reaction chamber of an M0VPE apparatus. Next, the sapphire substrate 1 was vapor-phase etched at a temperature of 1100 ° C. while flowing H 2 at normal pressure and a flow rate of 2 liter / min into the reaction chamber.
[0010]
Next, the temperature is lowered to 400 ° C., H 2 is supplied at 20 liter / min, NH 3 is supplied at 10 liter / min, and TMA is supplied at 1.8 × 10 −5 mol / min. The thickness was formed. Next, the temperature of the sapphire substrate 1 is maintained at 1000 ° C., H 2 is 20 liter / min, NH 3 is 10 liter / min, TMG is 1.7 × 10 −4 liter / min, diluted to 0.86 ppm with H 2 gas. silane was supplied for 30 minutes at 20 × 10 -8 mol / min, forming a thickness of about 2 [mu] m, the electron concentration of 2 × 10 18 / cm high carrier concentration n + layer 3 made of GaN doped with silicon of 3 did.
[0011]
Next, the substrate on which the above layers were laminated was mounted in the MBE apparatus. The temperature of the sapphire substrate 1 was maintained at 660 ° C., an n layer 4 made of GaN doped with silicon at a growth rate of 0.2 μm / h, a film thickness of about 0.1 μm, and a concentration of 2 × 10 18 / cm 3 was formed.
[0012]
Thereafter, the temperature of the sapphire substrate 1 was maintained at 660 ° C., and a barrier layer 51 made of In 0.08 Ga 0.92 N having a thickness of about 10 nm was formed at a growth rate of 0.1 μm / h. Next, the temperature of the sapphire substrate 1 was kept the same, and a silicon film made of In 0.16 Ga 0.84 N with a film thickness of about 10 nm was added to a concentration of 5 × 10 18 / cm 3 at a growth rate of 0.1 μm / h. A well layer 52 was formed. By repeating such a procedure, as shown in FIG. 2, a light emitting layer 5 having a multi-quantum well structure in which barrier layers 51 and well layers 52 are alternately stacked in four layers and three layers, and has a total thickness of 70 nm. Formed.
[0013]
Subsequently, the p layer 61 made of magnesium (Mg) -doped Al 0.08 Ga 0.92 N having a growth rate of 0.2 μm / h and a film thickness of about 0.2 μm was formed while maintaining the temperature at 660 ° C. The p-layer 61 has a magnesium concentration of 5 × 10 20 / cm 3 and a hole concentration of 2 × 10 18 / cm 3 .
[0014]
Subsequently, the temperature was maintained at 660 ° C., and a contact layer 62 made of magnesium (Mg) -doped GaN having a growth rate of 0.2 μm / h and a film thickness of about 0.2 μm was formed. The contact layer 62 has a magnesium concentration of 5 × 10 21 / cm 3 and a hole concentration of 3 × 10 18 / cm 3 .
[0015]
In this way, a wafer having a cross-sectional structure shown in FIG. 2 was obtained.
Next, as shown in FIG. 3, a SiO 2 layer 9 having a thickness of 2000 mm was formed on the contact layer 62 by sputtering, and a photoresist 10 was applied on the SiO 2 layer 9. Then, by photolithography, as shown in FIG. 3, on the contact layer 62, the photoresist 10 at the electrode formation site A ′ with respect to the high carrier concentration n + layer 3 was removed. Next, as shown in FIG. 4, the SiO 2 layer 9 not covered with the photoresist 10 was removed with a hydrofluoric acid etching solution.
[0016]
Next, the contact layer 62, the p layer 61, the light emitting layer 5, and the n layer 4 at portions not covered with the photoresist 10 and the SiO 2 layer 9 are subjected to a degree of vacuum of 0.04 Torr, a high frequency power of 0.44 W / cm 2 , and BCl 3. Gas was supplied at a rate of 10 ml / min for dry etching, followed by dry etching with Ar. In this step, as shown in FIG. 5, a hole A for extracting an electrode from the high carrier concentration n + layer 3 was formed.
[0017]
Next, Ni is uniformly vapor-deposited on the entire upper surface of the sample, and after applying a photoresist, a photolithography process, and an etching process, as shown in FIG. 1, the high carrier concentration n + layer 3 and the contact layer 62 are applied. Electrodes 8 and 7 were formed. Thereafter, the wafer processed as described above was cut into each chip to obtain a light emitting diode chip.
[0018]
The light-emitting element thus obtained had a drive current of 20 mA, an emission peak wavelength of 405 nm, and an emission intensity of 2 mW. This luminous efficiency was 3%. Compared with the case where all layers of the light emitting diode having the same structure as described above are formed by MBE, the light emission output is increased 10 5 times.
[0019]
As described above, the present invention is characterized in that the base layer, which has a high crystallinity and needs to be formed thick, is formed at a high speed by the MOVPE method, and the element layer requiring control of the film thickness is formed by the MBE method. Therefore, since the base layer having high crystallinity can be obtained at high speed, the device manufacturing speed can be improved without lowering the crystallinity of the element layer thereon.
[0020]
In the above embodiment, GaN is used for the n layer 4, but n-conducting AlGaN may be used. Further, the p layer 61 may not be provided. Moreover, the period of the multiple quantum well structure of the light emitting layer 5 is arbitrary, and a single quantum well structure may be sufficient. InGaN is used for the well layer and the barrier layer, but a group III nitride semiconductor such as In x Ga y Al 1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1) is used. It may be used. Further, although silicon is added to the well layer, other donor impurities may be added or may not be added.
[0021]
Further, as shown in FIG. 6, the barrier layer 513 may be added without adding a donor impurity (for example, silicon) and an acceptor impurity (for example, zinc) only to the well layer 523. Further, as shown in FIG. 7, the barrier layer 510 may be added without adding a donor impurity (for example, silicon) and an acceptor impurity (for example, zinc) to the well layer 520 alternately. Further, as shown in FIG. 8, a donor impurity (eg, silicon) may be added to the well layer 521, and an acceptor impurity (eg, zinc) may be added to the barrier layer 511. An acceptor impurity may be added and a donor impurity may be added to the barrier layer 511. These features relating to the impurity distribution can change the emission wavelength. The well layer and the barrier layer may be n-type, p-type, or semi-insulating.
[0022]
Further, the light emitting layer 5 may be a multi-layer that does not have a quantum well structure by thickening each layer. In this case as well, the structures of FIGS. 6 to 7 can be considered. In this case, since attention is paid only to the distribution of impurities, the layers 513 and 523, the layers 510 and 520, and the layers 511 and 521 may have the same composition ratio. The above impurity distribution can change the emission wavelength. Also in this case, each layer of the light emitting layer 5 may be n-type, p-type, and semi-insulating.
[0023]
Furthermore, the light emitting layer 5 may be a single layer as shown in FIG. In the above embodiment, a sapphire substrate is used, but SiC, MgAl 2 O 4 or the like can be used. Further, although AlN is used for the buffer layer, AlGaN, GaN, InAlGaN, or the like can be used. Further, although GaN is used for the base layer, a group III nitride semiconductor such as In x Ga y Al 1-xy N can be used. Similarly, a group III nitride semiconductor such as In x Ga y Al 1-xy N having an arbitrary composition ratio can be used for the element layer. When grown by MBE, it can be made p-type without heat treatment, but heat treatment may be added after growth.
[0024]
In addition to the light emitting diode, the present invention can be applied to laser diodes in the blue and ultraviolet regions, light detection elements, and other functional elements.
[Brief description of the drawings]
FIG. 1 is a configuration diagram illustrating a configuration of a light emitting diode according to a first specific example of the present invention.
FIG. 2 is a cross-sectional view showing a manufacturing process of the light-emitting diode of the same example.
FIG. 3 is a cross-sectional view showing a manufacturing process of the light-emitting diode of the example.
FIG. 4 is a cross-sectional view showing a manufacturing process of the light-emitting diode of the same example.
FIG. 5 is a cross-sectional view showing a manufacturing process of the light-emitting diode of the example.
FIG. 6 is a cross-sectional view showing another structure of the light emitting layer.
FIG. 7 is a cross-sectional view showing another structure of the light emitting layer.
FIG. 8 is a cross-sectional view showing another structure of the light emitting layer.
FIG. 9 is a configuration diagram illustrating a configuration of a light emitting diode according to another embodiment.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Light emitting diode 1 ... Sapphire substrate 2 ... Buffer layer 3 ... High carrier concentration n <+> layer 4 ... n layer 5 ... Light emitting layer 61 ... p layer 62 ... Contact layer 7, 8 ... Electrode

Claims (5)

基板と基板上に形成されたバッファ層とそのバッファ層上に形成された3族窒化物半導体から成る基底層とその基底層上に形成された3族窒化物半導体から成る素子層とを有する半導体素子において、
前記基底層は有機金属化合物気相成長法(MOVPE)により形成された層であり、
前記基底層は2μm以上の厚さに形成されており、
前記素子層は分子線エピタキー法(MBE)により形成された層である
ことを特徴とする3族窒化物半導体素子。
A semiconductor having a substrate, a buffer layer formed on the substrate, a base layer made of a group III nitride semiconductor formed on the buffer layer, and an element layer made of a group III nitride semiconductor formed on the base layer In the element
The base layer is a layer formed by metal organic compound vapor deposition (MOVPE),
The base layer is formed to a thickness of 2 μm or more,
The group III nitride semiconductor device, wherein the device layer is a layer formed by molecular beam epitaxy (MBE).
前記基底層はGaNから成り前記素子層は3族窒化物半導体から成る少なくともp層とn層とを有した発光素子を形成していることを特徴とする請求項1に記載の3族窒化物半導体素子。2. The group III nitride according to claim 1 , wherein the base layer is made of GaN and the element layer is a light emitting element having at least a p layer and an n layer made of a group 3 nitride semiconductor. Semiconductor element. 前記素子層はp層とn層とその間に介在する量子井戸構造の発光層とから成ることを特徴とする請求項1に記載の3族窒化物半導体素子。2. The group III nitride semiconductor device according to claim 1 , wherein the device layer includes a p-layer, an n-layer, and a light-emitting layer having a quantum well structure interposed therebetween. 前記基板はサファイア基板であることを特徴とする請求項2に記載の3族窒化物半導体素子。The group III nitride semiconductor device according to claim 2 , wherein the substrate is a sapphire substrate. 前記バッファ層はAlNであることを特徴とする請求項2に記載の3族窒化物半導体素子。3 nitride semiconductor device according to claim 2 wherein the buffer layer is characterized by the AlN der Turkey.
JP30825195A 1995-10-31 1995-10-31 Group 3 nitride semiconductor device Expired - Fee Related JP3727091B2 (en)

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