JP2626431B2 - Nitrogen-3 group element compound semiconductor light emitting device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a blue-emitting nitrogen-3 group element semiconductor light emitting device.

[0002]

2. Description of the Related Art Conventionally, a blue light emitting diode using a GaN-based compound semiconductor has been known. The GaN
Attention has been paid to the fact that system compound semiconductors are of direct transition type and thus have high luminous efficiency, and that blue, one of the three primary colors of light, is used as the luminescent color.

Recently, it has been revealed that p-type GaN can be obtained by doping Mg and irradiating an electron beam. As a result, the conventional n-layer and semi-insulating layer (i
A GaN light emitting diode having a pn junction instead of a junction with a layer is proposed.

[0004]

However, even with the above-mentioned light emitting diode having a pn junction, the light emission luminance is not yet sufficient, and a sufficient light emitting life has not been obtained. Therefore, an object of the present invention is to provide a nitrogen- group III element compound semiconductor (Al _x Ga _Y In _1-XY N; including X = 0, Y = 0, X = Y = 0).
It is to improve the light emission luminance of the light emitting diode and to prolong the element life.

[0005]

A first feature of the present invention is as follows.
n-type nitrogen-group III element compound semiconductor (Al _x Ga _Y In _1-XY N; X =
0, Y = 0, X = Y = 0) and p-type nitrogen-3
A nitrogen-group III element compound semiconductor light emitting device having a p-layer made of a group III element compound semiconductor (Al _x Ga _Y In _1-XY N; including X = 0, Y = 0, X = Y = 0); The layer has a double structure of a low carrier concentration n layer and a high carrier concentration n ⁺ layer in order from the side joined to the p layer, and the p layer has a low carrier concentration p layer in order from the side joined to the n layer. This is a double structure with a high carrier concentration p ⁺ layer. The second feature of the present invention is that the low carrier concentration p layer has a hole concentration of 1 × 10 ¹⁴ to 1 × 10 ¹⁶ / cm ³ , and the third feature of the present invention is that the high carrier concentration p layer ^{The +} layer has a hole concentration of 1 × 10 ¹⁶ to 2 × 10 ¹⁷ / cm ³ . A fourth feature of the present invention is that the low carrier concentration n layer has an electron concentration of 1 × 10 ¹⁴ to 1 × 10 ¹⁶ / cm ³ , and a fifth feature of the present invention is that the low carrier concentration n layer
The layer has a thickness of 0.5 to 2.0 μm. A sixth feature of the present invention is that the high carrier concentration n ⁺ layer has an electron concentration of 1 × 10 ¹⁶ to 1 × 10 ¹⁹ / cm ³ , and a seventh feature of the present invention is that the high carrier concentration n ⁺ layer is 2.0 to 10 μm
m. An eighth feature of the present invention is that
Low carrier concentration p layer and high carrier concentration p ⁺ layer are insulators
Is that a portion of the nitrogen -3 group element compound semiconductor layer formed by p-type, the ninth aspect of the present invention, the low carrier
Concentration p layer and high carrier concentration p ⁺ layer is magnesium (Mg)
Is a layer that has been converted to a p-type conductor after the addition of
That is. Further, the tenth aspect of the present invention, high calibration
That silicon is added to the rear concentration n ⁺ layer.
You.

The n-type layer and the p-type layer directly involved in the pn junction have a carrier concentration of 1 × 10 ¹⁴ to 1 × 10 ¹⁶ / cm ^3.
Are desirably substantially equal in the range of

[0007]

According to the present invention, the carrier concentration of the layer closer to the pn junction is reduced, and the carrier concentration of the layer farther from the pn junction is increased, so that both the n-layer and the p-layer are double layers. Since it was formed, the light emission luminance was improved. Emission brightness is 10
mcd, which is twice as high as that of a conventional pn junction GaN light emitting diode. Further, the emission lifetime is 10 ⁴ hours, 1.5 times the emission lifetime of the conventional pn junction GaN light emitting diodes.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment In FIG. 1, a light emitting diode 10 has a sapphire substrate 1 on which 500 .ANG.
Buffer layer 2 is formed. On the buffer layer 2, a film thickness of about 2.2 μm and an electron concentration of 2 × 10 ¹⁸ / cm ³
A high carrier concentration n ⁺ layer 3 made of silicon-doped GaN and a low carrier concentration n layer 4 made of non-doped GaN having a film thickness of about 1.5 μm and an electron concentration of 1 × 10 ¹⁶ / cm ³ are formed. Further, on the low carrier concentration n layer 4, a low carrier concentration p layer 51 made of Mg-doped GaN having a film thickness of about 0.5 μm and a hole concentration of 1 × 10 ¹⁶ / cm ³ , a film thickness of about 0.2 μm, A high carrier concentration p ⁺ layer 52 having a concentration of 2 × 10 ¹⁷ / cm ³ is formed. The electrode 7 made of nickel connected to the high carrier concentration p ⁺ layer 52 and the high carrier concentration n ⁺
An electrode 8 made of nickel and connected to the layer 3 is formed. The electrode 8 and the electrode 7 are electrically insulated and separated by the groove 9.

Next, a method of manufacturing the light emitting diode 10 having this structure will be described. The light emitting diode 10 includes:
It was manufactured by vapor phase growth by an organometallic compound vapor phase growth method (hereinafter referred to as “M0VPE”). The gas used was NH
₃ and the carrier gas H ₂ and trimethylgallium (Ga (CH _{3) 3)}
(Hereinafter referred to as "TMG") and trimethylaluminum (Al
(CH ₃ ) ₃ ) (hereinafter referred to as “TMA”), silane (SiH ₄ ), and biscyclopentadienyl magnesium (Mg (C ₅ H ₅ ) ₂ ) (hereinafter referred to as “CP ₂ Mg”).

First, a single-crystal sapphire substrate 1 whose main surface is the surface A cleaned by organic cleaning and heat treatment is mounted on a susceptor placed in a reaction chamber of an MOVPE apparatus. Next, while flowing H ₂ at normal pressure into the reaction chamber at a flow rate of 2 liter / min, the temperature was 1100
The sapphire substrate 1 was subjected to gas-phase etching at a temperature of ℃.

[0011] Next, by lowering the temperature to 400 ° C., and H ₂
20 liter / min, NH ₃ 10 liter / min, TMA 1.8 × 10 ^-5
Supplying at mol / min, an AlN buffer layer 2 was formed to a thickness of about 500 °. Next, the temperature of the sapphire substrate 1 was set to 1150
° C, H ₂ at 20 liter / min, NH ₃ at 10 liter / min,
TMG 1.7 × 10 ^-4 mol / min, supplying 30 minutes silane diluted with H ₂ to 0.86ppm a (SiH ₄₎ at a rate of 200 ml / min, a film thickness of about 2.2 .mu.m, electron concentration 2 × 10 ¹⁸ / A high carrier concentration n ⁺ layer 3 made of GaN of cm ³ was formed.

Subsequently, the temperature of the sapphire substrate 1 is set to 1150 ° C.
, H ₂ at 20 liter / min, NH ₃ at 10 liter / min, TMG
At a rate of 1.7 × 10 ^-4 mol / min for 20 minutes,
A low carrier concentration n-layer 4 made of GaN having a thickness of 1.5 μm and an electron concentration of 1 × 10 ¹⁶ / cm ³ was formed.

Next, the sapphire substrate 1 is heated to 1150 ° C.
H ₂ 20 liter / min, NH ₃ 10 liter / min, TMG 1.7
× 10 ^-4 mol / min, CP ₂ Mg at 8 × 10 ^-8 mol / min 7
The low carrier concentration p-layer 51 made of GaN having a thickness of 0.5 μm was formed by supplying for 5 minutes. In this state, the low carrier concentration p layer 51 is still an insulator having a resistivity of 10 ⁸ Ωcm or more.

Next, the sapphire substrate 1 is heated to 1150 ° C.
H ₂ 20 liter / min, NH ₃ 10 liter / min, TMG 1.7
× 10 ^-4 mol / min, CP ₂ Mg at 3 × 10 ^-7 mol / min
The high carrier concentration ^p.sup . ⁺ Layer 52 made of GaN having a thickness of 0.2 .mu.m was formed. In this state, the high carrier concentration p ⁺ layer 52 is still an insulator having a resistivity of 10 ⁸ Ωcm or more.

Next, the above-described high carrier concentration p ⁺ layer 52 and low carrier concentration p layer 5
1 was uniformly irradiated with an electron beam. The electron beam irradiation conditions were: acceleration voltage 10 KV, sample current 1 μA, beam moving speed 0.2 mm /
sec, the beam diameter is 60 μmφ, and the degree of vacuum is 2.1 × 10 ⁻⁵ Torr. By the irradiation of the electron beam, the low carrier concentration p layer 51 is formed.
Is a p-conductivity semiconductor having a hole concentration of 1 × 10 ¹⁶ / cm ³ and a resistivity of 40 Ωcm, and the high carrier concentration p ⁺ layer 52 is composed of a p-conductivity semiconductor having a hole concentration of 2 × 10 ¹⁷ / cm ³ and a resistivity of 2 Ωcm. became. Thus, a wafer having a multilayer structure as shown in FIG. 2 was obtained.

FIGS. 3 to 7 described below are cross-sectional views showing only one device on the wafer. In actuality, processing is performed on a wafer in which this device is continuously repeated. It is cut for each element.

As shown in FIG. 3, an SiO ₂ layer 11 is formed on the high carrier concentration p ⁺
It was formed in thickness. Next, a photoresist 12 was applied on the SiO ₂ layer 11. Then, by photolithography, on the high carrier concentration p ⁺ layer 52, the electrode formation site A corresponding to the hole 15 formed so as to reach the high carrier concentration n ⁺ layer 3 and the electrode formation portion are formed with the high carrier concentration p ⁺
The photoresist in the portion B where the groove 9 for insulating and separating from the electrode of the layer 52 was formed was removed.

Next, as shown in FIG. 4, the SiO ₂ layer 11 not covered with the photoresist 12 was removed with a hydrofluoric acid-based etchant. Next, as shown in FIG.
The upper surface of the high carrier concentration p ⁺ layer 52 at a portion not covered by the photoresist 12 and the SiO ₂ layer 11 and the lower carrier concentration p layer 51, the low carrier concentration n layer 4, and the high carrier concentration n ⁺ layer 3 The part was dry-etched by supplying a degree of vacuum of 0.04 Torr, high-frequency power of 0.44 W / cm ² , and BCl ₃ gas at a rate of 10 ml / min, followed by dry etching with Ar. In this step, a hole 15 for extracting an electrode from the high carrier concentration n ⁺ layer 3 and a groove 9 for insulating and separating were formed.

Next, as shown in FIG. 6, the SiO ₂ layer 11 remaining on the high carrier concentration p ⁺ layer 52 was removed with hydrofluoric acid. Next, as shown in FIG.
The Ni layer 13 was formed by vapor deposition. As a result, the Ni layer 13 electrically connected to the high carrier concentration n ⁺ layer 3 is formed in the hole 15. Then, a photoresist 14 is applied on the Ni layer 13, and photolithography is performed so that the photoresist 14 has an electrode portion for the high carrier concentration n ⁺ layer 3 and the high carrier concentration p ⁺ layer 52.
A pattern was formed in a predetermined shape.

Next, as shown in FIG. 7, the exposed portion of the lower Ni layer 13 was etched with a nitric acid-based etchant using the photoresist 14 as a mask. At this time, the Ni layer 13 deposited on the groove 9 for insulation separation is completely removed.
Next, the photoresist 14 is removed with acetone, and the electrode 8 of the high carrier concentration n ⁺ layer 3 and the high carrier concentration p ⁺ layer 52 are removed.
Electrode 7 was left. Thereafter, the wafer processed as described above was cut into individual devices to obtain a gallium nitride-based light emitting device having a pn structure shown in FIG.

The light emission intensity of the light emitting diode 10 manufactured as described above was measured to be 10 mcd, and the light emission luminance was twice as high as that of the conventional pn junction GaN light emitting diode. Further, the emission lifetime is 10 ⁴ hours was 1.5 times that of the emission lifetime of the GaN light emitting diodes of a conventional pn junction.

The doping gas of magnesium Mg used in the above embodiment may be methyl biscyclopentadienyl magnesium Mg (C ₆ H ₇ ) ₂ in addition to the above gases.

The electron concentration of the low carrier concentration n layer 4 is 1
× 10 ¹⁴ to 1 × 10 ¹⁶ / cm ³ and a film thickness of 0.5 to 2 μm are desirable. When the electron concentration is 1 × 10 ¹⁶ / cm ³ or more, the emission intensity is decreased, and thus it is not desirable. When the electron concentration is 1 × 10 ¹⁴ / cm ³ or less, the series resistance of the light emitting element becomes too high and heat is generated when a current is applied. . On the other hand, if the film thickness is 2 μm or more, the series resistance of the light-emitting element becomes excessively high, and heat is generated when a current is applied. Undesirably, if the film thickness is 0.5 μm or less, the light emission intensity decreases.

Further, it is desirable that the high carrier concentration n ⁺ layer 3 has an electron concentration of 1 × 10 ¹⁶ to 1 × 10 ¹⁹ / cm ³ and a film thickness of 2 to 10 μm. Undesirable because the electron concentration crystallinity becomes 1 × 10 ¹⁹ / cm ³ or more is deteriorated, undesirably series resistance of the light emitting element becomes 1 × 10 ¹⁶ / cm ³ or less generates heat and electric current becomes too high . On the other hand, when the film thickness is 10 μm or more, the substrate is undesirably curved, and when the film thickness is 2 μm or less, the series resistance of the light emitting element becomes excessively high and heat is generated when a current is applied.

The low carrier concentration p layer 51 has a hole concentration of 1 × 10 ¹⁴ to 1 × 10 ¹⁶ / cm ³ and a thickness of 0.2 to 1 μm.
Is desirable. When the hole concentration is 1 × 10 ¹⁶ / cm ³ or more, the matching with the low carrier concentration n-layer 4 is deteriorated, and the luminous efficiency is lowered. Undesirably, when the hole concentration is 1 × 10 ¹⁴ / cm ³ or less, the series resistance becomes high. It is not desirable because it becomes too much. On the other hand, if the film thickness is 1 μm or more, the series resistance is increased, which is not desirable.

The hole concentration of the high carrier concentration p ⁺ layer 52 is preferably 1 × 10 ¹⁶ to 2 × 10 ¹⁷ / cm ³ , and the film thickness is preferably 0.2 μm. A p ⁺ layer having a hole concentration of 2 × 10 ¹⁷ / cm ³ or more cannot be formed. When the density is 1 × 10 ¹⁶ / cm ³ or less, the series resistance increases, which is not desirable. Further, when the film thickness is 0.5 μm or more, the series resistance increases, which is not desirable.
When the thickness is 1 μm or less, the hole injection efficiency decreases, which is not desirable.

Second Embodiment Referring to FIG. 8, the light emitting diode 10 has a sapphire substrate 1, and the sapphire substrate 1
Buffer layer 2 is formed. On the buffer layer 2, in order, a film thickness of about 2.2 μm and an electron concentration of 2 × 10 ¹⁸ / cm ³
A high carrier concentration n ⁺ layer 3 made of silicon-doped GaN and a low carrier concentration n layer 4 made of non-doped GaN having a film thickness of about 1.5 μm and an electron concentration of 1 × 10 ¹⁶ / cm ³ are formed. Further, on the low carrier concentration n layer 4, a low impurity concentration i-layer 61 made of Mg-doped GaN having a thickness of about 0.5 μm and a Mg concentration of 5 × 10 ¹⁹ / cm ³ , a thickness of about 0.2 μm, Concentration 2 ×
A high impurity concentration i ⁺ layer 62 of 10 ²⁰ / cm ³ is formed.

The predetermined regions of the low impurity concentration i-layer 61 and the high impurity concentration i ⁺ layer 62 have a low carrier concentration of 1 × 10 ¹⁶ / cm ³ , which is a p-conduction type by electron beam irradiation. A p layer 501 and a high carrier concentration p ⁺ layer 502 having a hole concentration of 2 × 10 ¹⁷ / cm ³ are formed.

[0029] Further, from the upper surface of the high impurity concentration i ⁺ layer 62, the high impurity concentration i ⁺ layer 62, low impurity concentration i layer 61,
A hole 15 penetrating through the low carrier concentration n layer 4 and reaching the high carrier concentration n ⁺ layer 3 is formed. An electrode 81 made of nickel joined to the high carrier concentration n ⁺ layer 3 through the hole 15 is formed on the high impurity concentration i ⁺ layer 62. Further, on the upper surface of the high carrier concentration p ⁺ layer 502, the electrode 71 formed of nickel for high carrier concentration p ⁺ layer 502 is formed. High carrier concentration n ⁺ layer 3
Is separated from the high carrier concentration p ⁺ layer 502 and the low carrier concentration p layer 501 by the high impurity concentration i ⁺ layer 62 and the low impurity concentration i layer 61.

Next, a method of manufacturing the light emitting diode 10 having this structure will be described. 9 to 1 showing the manufacturing process
Reference numeral 5 is a cross-sectional view of only one element in the wafer, and the following manufacturing process is actually performed on a wafer on which the elements shown in the figure are repeatedly formed. Then, finally, the wafer is cut to form each light emitting element.

The wafer shown in FIG. 9 is manufactured in the same manner as in the first embodiment. Next, as shown in FIG. 10, the SiO ₂ layer 11 is formed on the high impurity concentration i ⁺ layer 62 by sputtering.
Was formed to a thickness of 2000 mm. Next, a photoresist 12 was applied on the SiO ₂ layer 11. Then, the photoresist at the electrode formation site A corresponding to the hole 15 formed to reach the high carrier concentration n ⁺ layer 3 in the high impurity concentration i ⁺ layer 62 was removed by photolithography.

Next, as shown in FIG. 11, the SiO ₂ layer 11 not covered with the photoresist 12 was removed with a hydrofluoric acid-based etchant. Next, as shown in FIG. 12, the photoresist 12 and the SiO ₂ layer 11 a high impurity concentration of a portion not covered by the i ⁺ layer 62 and the low carrier concentration n layer 4 and the low impurity concentration i layer 61 thereunder A part of the upper surface of the high carrier concentration n ⁺ layer 3 was dry-etched by supplying a vacuum degree of 0.04 Torr, high-frequency power of 0.44 W / cm ² , and BCl ₃ gas at a rate of 10 ml / min, and then dry-etching with Ar. In this step, a hole 15 for extracting an electrode from the high carrier concentration n ⁺ layer 3 was formed. Next, as shown in FIG. 13, the SiO ₂ layer 11 remaining on the high impurity concentration i ⁺ layer 62
Was removed with hydrofluoric acid.

Next, as shown in FIG. 14, only predetermined regions of the high impurity concentration i.sup. ⁺ Layer 62 and the low impurity concentration i layer 61 are irradiated with an electron beam using a reflection electron beam diffraction device. A high carrier concentration p ⁺ layer 502 having a hole concentration of 2 × 10 ¹⁷ / cm ³ and a low carrier concentration p layer 501 having a hole concentration of 1 × 10 ¹⁶ / cm ³ were formed.

The irradiation conditions of the electron beam were as follows: acceleration voltage 10 KV, sample current 1 μA, beam moving speed 0.2 mm / sec, beam diameter 60
μmφ, vacuum degree 2.1 × 10 ⁻⁵ Torr. At this time, portions other than the high carrier concentration p ⁺ layer 502 and the low carrier concentration p layer 501, that is, the portions not irradiated with the electron beam, are the high impurity concentration i ⁺ layer 62 and the low impurity concentration i layer 6 of the insulator.
It remains at 1. Therefore, the high carrier concentration p ⁺ layer 502
And the low carrier concentration p-layer 501 is:
Conduction is made to the low carrier concentration n layer 4, but in the lateral direction, the high impurity concentration i ⁺ layer 62 and the low impurity concentration i
It is electrically insulated and separated by the layer 61.

Next, as shown in FIG. 15, a high carrier concentration p ⁺ layer 502, a high impurity concentration i ⁺ layer 62, and a high carrier concentration n ^{+ The} Ni layer 20 was formed on the ⁺ layer 3 by vapor deposition. Then, a photoresist 21 is applied on the Ni layer 20, and the photoresist 21 is applied by photolithography.
Are the high carrier concentration n ⁺ layer 3 and the high carrier concentration p ⁺ layer 5
A pattern was formed in a predetermined shape so that the electrode portion for 02 remained. Next, using the photoresist 21 as a mask, the exposed portion of the lower Ni layer 20 was etched with a nitric acid-based etchant, and the photoresist 21 was removed with acetone.
In this way, as shown in FIG.
The electrode 81 of the ⁺ layer 3 and the electrode 71 of the high carrier concentration p ⁺ layer 502 were formed. Thereafter, the wafer formed as described above was cut for each element.

[0036] Measurement of the emission intensity of the light emitting diode 10, which is manufactured in this way, as in the first embodiment, a 10Mcd, emission lifetime was 10 ⁴ hours.

Third Embodiment A light emitting diode 10 may be constructed as shown in FIG. That is, on the buffer layer 2, in order, a film thickness of about 0.
High carrier concentration p ^{+ of} 2 μm, hole concentration 2 × 10 ¹⁷ / cm ³
Layer 52, thickness about 0.5 μm, hole concentration of 1 × 10 ¹⁵ / cm ³ Mg
A low carrier concentration p layer 51 made of doped GaN is formed. Then, on the low carrier concentration p layer 51,
Non-doped Ga with a film thickness of about 1.5 μm and an electron concentration of 1 × 10 ¹⁵ / cm ³
Low carrier concentration n layer 4 consisting of N, a thickness of about 2.2 [mu] m, the electron concentration 2 × 10 ¹⁸ / cm ³ of silicon-doped high carrier concentration n ⁺ layer 3 made of GaN is formed.

An electrode 72 made of nickel and connected to the high carrier concentration p ⁺ layer 52 and the high carrier concentration n
An electrode 82 made of nickel and connected to the ⁺ layer 3 is formed. The electrode 82 and the electrode 72 are electrically insulated from each other by grooves 91 formed in the high carrier concentration n ⁺ layer 3, the low carrier concentration n layer 4, and the low carrier concentration p layer 51.

As described above, the present embodiment differs from the first embodiment in that the order of depositing the p layer and the n layer on the substrate 1 is reversed. Manufacturing can be performed in the same manner as in the first embodiment.

Fourth Embodiment In the light emitting diode of the first embodiment having the structure shown in FIG. 1, a high carrier concentration n ⁺ layer 3, a low carrier concentration n layer 4,
Low carrier concentration p layer 51, high carrier concentration p ⁺ layer 52
Was set to Al _0.2 Ga _0.5 In _0.3 N, respectively. The high carrier concentration n ⁺ layer 3 has an electron concentration of 2 × 10 ¹⁸ / c
m ³ , and the low carrier concentration n-layer 4 was formed at an electron concentration of 1 × 10 ¹⁶ / cm ³ without adding impurities. Low carrier concentration p layer 5
No. 1 is formed by adding magnesium (Mg) and irradiating an electron beam to form a hole concentration of 1 × 10 ¹⁶ / cm ³ , and a high carrier concentration p ⁺ layer 52.
Was added to magnesium (Mg) and irradiated with an electron beam to form a hole concentration of 2 × 10 ¹⁷ / cm ³ . The electrode 7 made of nickel connected to the high carrier concentration p ⁺ layer 52
And an electrode 8 made of nickel and connected to the high carrier concentration n ⁺ layer 3.

Next, the light emitting diode 10 having this structure can be manufactured similarly to the light emitting diode of the first embodiment. Trimethylindium (In (CH ₃ ) ₃ ) was used in addition to TMG, TMA, silane, and CP ₂ Mg gas. The generation temperature and gas flow rate are the same as in the first embodiment. The flow rates of the other gases are the same as in the first embodiment, except that trimethylindium is supplied at 1.7 × 10 ⁻⁴ mol / min.

Next, similarly to the first embodiment, the high carrier concentration p ⁺ layer 52 and the low carrier concentration p layer 51 are uniformly irradiated with an electron beam using a reflection electron beam diffraction apparatus. A p-type semiconductor was obtained.

The light emission intensity of the light emitting diode 10 thus manufactured was measured to be 10 mcd, and the light emission luminance was twice as high as that of the conventional pn junction GaN light emitting diode. Further, the emission lifetime is 10 ⁴ hours was 1.5 times that of the emission lifetime of the GaN light emitting diodes of a conventional pn junction.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a configuration of a light emitting diode according to a first specific example of the present invention.

FIG. 2 is a sectional view showing a manufacturing process of the light-emitting diode of the embodiment.

FIG. 3 is a sectional view showing a manufacturing step of the light-emitting diode of the embodiment.

FIG. 4 is a sectional view showing a manufacturing step of the light-emitting diode of the same embodiment.

FIG. 5 is a sectional view showing the manufacturing process of the light emitting diode of the same embodiment.

FIG. 6 is a sectional view showing the manufacturing process of the light-emitting diode of the example.

FIG. 7 is a sectional view showing the manufacturing process of the light emitting diode of the same embodiment.

FIG. 8 is a configuration diagram showing a configuration of a light emitting diode according to a second specific example of the present invention.

FIG. 9 is a sectional view showing the manufacturing process of the light-emitting diode of the example.

FIG. 10 is a sectional view showing the manufacturing process of the light-emitting diode of the example.

FIG. 11 is a sectional view showing the manufacturing process of the light-emitting diode of the example.

FIG. 12 is a sectional view showing the manufacturing process of the light-emitting diode of the example.

FIG. 13 is a sectional view showing the manufacturing process of the light-emitting diode of the example.

FIG. 14 is a sectional view showing a manufacturing step of the light-emitting diode of the example.

FIG. 15 is a sectional view showing the manufacturing process of the light-emitting diode of the example.

FIG. 16 is a configuration diagram showing a configuration of a light emitting diode according to a third specific example of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Light-emitting diode 1 ... Sapphire substrate 2 ... Buffer layer 3 ... High carrier concentration n ⁺ layer 4 ... Low carrier concentration n layer 51,501 ... Low carrier concentration p layer 52,502 ... High carrier concentration p ⁺ layer 61 ... Low impurity Concentration i layer 62 High impurity concentration i ⁺ layer 7, 8, 71, 72, 81, 82 Electrode 9, 91 Groove

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Junichi Umezaki 1 Ochiai Ochiai, Kasuga-cho, Nishikasugai-gun, Aichi Prefecture Inside Toyota Gosei Co., Ltd.

Claims (10)

(57) [Claims] 1. An n-type nitrogen-group III element compound semiconductor (Al _x
Ga _Y In _1-XY N; X = 0, Y = 0, and X = Y = 0).
p-type nitrogen-group III element compound semiconductor (Al _x Ga _Y In _1-XY N; X =
0, Y = 0, X = Y = 0)
In the group-element compound semiconductor light emitting device, the n layer has a double structure of a low carrier concentration n layer and a high carrier concentration n ⁺ layer in order from the side joined to the p layer, and the p layer has the n layer A light-emitting element having a double structure of a low carrier concentration p layer and a high carrier concentration p ⁺ layer in order from the side joined to the light emitting element. 2. The light emitting device according to claim 1, wherein the low carrier concentration p layer has a hole concentration of 1 × 10 ¹⁴ to 1 × 10 ¹⁶ / cm ³ . 3. The light emitting device according to claim 1, wherein the high carrier concentration p ⁺ layer has a hole concentration of 1 × 10 ¹⁶ to 2 × 10 ¹⁷ / cm ³ . Wherein said low carrier concentration n layer, the electron concentration
Claims, characterized in that a ^{1 × 10 14 ~ 1 × 10} 16 / cm 3
Item 2. A light emitting device according to item 1 . 5. The method according to claim 1, wherein said low carrier concentration n layer is 0.5 to 2.0.
The light emitting device according to claim 1 , wherein the light emitting device has a thickness of μm. Wherein said high carrier concentration n ⁺ layer, 請 characterized in that the electron density is ^{1 × 10 16 ~ 1 × 10} 19 / cm 3
The light emitting device according to claim 1 . 7. The high carrier concentration n ⁺ layer has a thickness of 2.0 to 10
The light emitting device according to claim 1 , wherein the light emitting device has a thickness of μm. Wherein said low carrier concentration p layer and the high calibration
2. The light emitting device according to claim 1, wherein the rear concentration p ⁺ layer is formed by forming a part of the insulator nitrogen-group III element compound semiconductor layer into a p-type. 9. The low carrier concentration p layer and the high carrier concentration
Rear concentration p ⁺ Layer is p-type after adding magnesium (Mg)
A layer characterized by being converted into a conductor.
The light emitting device according to claim 1. 10. The high carrier concentration n ⁺ Layer is silicon
2. The method according to claim 1, wherein
Optical element.