JPH0936224A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device provided with a high-performance high-density wiring layer and a manufacturing method by which the semiconductor integrated circuit device can be manufacture easily. SOLUTION: After an upper wiring layer 15 is formed on a substrate 9 containing an interlayer insulating film 11 having a through hole 14, the pattern of the upper wiring layer 15 is formed by removing unnecessary parts from the wiring layer 15 and a lower wiring layer 12 formed below the wiring layer 15 by etching the wiring layers 15 and 12 from the surface of the wiring layer 15 and, at the same time, the pattern is planarized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly to a technique effectively applied to a semiconductor integrated circuit device having a high performance wiring layer.

[0002]

2. Description of the Related Art In semiconductor integrated circuit devices, high integration and fine processing have been promoted, and accordingly, the wiring structure has become fine, and a high density wiring structure has been required.

In recent years, a multilayer wiring structure has been adopted as a wiring layer of a semiconductor integrated circuit device, and a lower wiring layer and an upper wiring layer are electrically connected to each other through through holes in selective regions of an interlayer insulating film. There is something.

The wiring layers in the semiconductor integrated circuit device examined by the present inventor are as follows.

That is, the lower wiring layer is arranged at a constant interval on the insulating film on the semiconductor substrate on which the semiconductor element is formed, and the upper wiring layer is formed through the through hole in the interlayer insulating film. The upper wiring layers are electrically connected and are arranged at a constant interval.

[0006] As a document describing a technique for forming a wiring layer in a semiconductor integrated circuit device, for example, November 2, 1989, Press Journal Co., Ltd., “'90 latest semiconductor process technology” p267- p273
Are listed in.

[0007]

However, the present inventor has found that the semiconductor integrated circuit device having the above-mentioned multilayer wiring layer has various problems as described below.

That is, in a manufacturing process in which an upper wiring layer is formed on an interlayer insulating film in which a through hole is formed and the upper wiring layer is patterned using a photolithography technique and a selective etching technique, selective etching is performed. Due to the etching solution used in the technology, a dent may be formed in the upper wiring layer above the through hole, that is, a recess may be formed in which a part of the wiring layer above the through hole is depressed from the surroundings. There is a problem that you cannot do it.

When the upper wiring layer is dented and cannot be flattened, the characteristics of the upper wiring layer are deteriorated and the wiring layer of the multi-layer wiring structure cannot be formed with high density.

In order to prevent the occurrence of the above-mentioned dent in the upper wiring layer, a manufacturing method is conceivable in which the upper wiring layer is formed after the through hole wiring layer is selectively embedded in the through hole in the interlayer insulating film. This manufacturing process is adopted because the selectivity and selection conditions in the manufacturing process for selectively forming the through-hole wiring layer in the region of the through-hole become complicated and various problems occur with respect to mass productivity. It is difficult to do so.

This kind of problem also occurs in a manufacturing process for forming a pattern of an upper wiring layer on an interlayer insulating film having a through hole, and the semiconductor integrated circuit device having a multilayer wiring layer has high performance and high performance. There is a problem that a wiring layer having a high density cannot be formed.

It is an object of the present invention to provide a semiconductor integrated circuit device having a high performance and a high density wiring layer.

Another object of the present invention is to provide a manufacturing technique capable of easily manufacturing a semiconductor integrated circuit device having a high performance and a high density wiring layer.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0015]

The typical ones of the inventions disclosed in the present invention will be outlined below.

In the semiconductor integrated circuit device of the present invention, after the lower wiring layer is formed on the surface of the substrate on which a plurality of semiconductor elements are formed, the interlayer insulating film is formed on the substrate including the lower wiring layer, A step of forming a lower wiring layer made of a material having an etching rate higher than that of the upper wiring layer on the interlayer insulating film, and a photoresist film serving as an etching mask on a part of the surface of the lower wiring layer, and then a photo A step of forming a through hole by etching the lower wiring layer and the interlayer insulating film whose surface is exposed using the resist film as an etching mask, and a step of forming a through hole on the base body including the interlayer insulating film. After forming the upper wiring layer, etching is performed from the surface of the upper wiring layer to remove unnecessary regions of the upper wiring layer and the lower wiring layer below the upper wiring layer. And a step of forming a pattern of lines layer.

[0017]

According to the method for manufacturing a semiconductor integrated circuit device of the present invention described above, a step of forming a lower wiring layer made of a material having an etching rate higher than that of the upper wiring layer on the interlayer insulating film, and a step of forming the lower wiring layer After forming a photoresist film serving as an etching mask on a part of the surface, by etching the lower wiring layer and the interlayer insulating film whose surface is exposed using the photoresist film as an etching mask,
After forming the upper wiring layer on the substrate including the step of forming the through hole and the interlayer insulating film in which the through hole is formed, by etching from the surface of the upper wiring layer, the upper wiring layer and its lower portion are formed. By removing the unnecessary region of the lower wiring layer and forming the pattern of the upper wiring layer, a dent is generated on the surface of the upper wiring layer formed on the through hole in the interlayer insulating film. Even if the surface of the upper wiring layer is not flattened due to unevenness in the process of forming the pattern of the upper wiring layer by etching from the surface of the upper wiring layer, the etching rate is lower than that in the lower wiring layer. Since the lower wiring layer made of a large material is provided, the upper wiring layer can be flattened by a simple manufacturing process.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and a duplicate description will be omitted.

(Embodiment 1) FIGS. 1 to 8 are sectional views showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention. The semiconductor integrated circuit device and the manufacturing method thereof according to the present invention will be specifically described with reference to FIG.

First, as shown in FIG. 1, an element isolation region, which is a selective region on the surface of a semiconductor substrate 1 made of, for example, p-type silicon single crystal, is subjected to a thermal oxidation process to form a field made of a silicon oxide film. The insulating film 2 is formed. Although not shown, a channel stopper layer for preventing inversion is formed under the field insulating film 2.

Next, as shown in FIG. 2, a gate insulating film 3 made of silicon oxide is formed in the active region surrounded by the field insulating film 2, and a gate electrode made of polycrystalline silicon is formed on the gate insulating film 3. 4 is formed. The gate electrode 4 is formed by sequentially depositing an insulating film 5 made of a polycrystalline silicon film and a silicon oxide film on the semiconductor substrate 1 and etching these sequentially. Thereafter, a sidewall insulating film 6 made of silicon oxide is formed on the side wall of the gate electrode 4.

Next, an n-type impurity such as phosphorus (P) is ion-implanted into the semiconductor substrate 1 to form an n-type semiconductor region 7 serving as a source and a drain.

Next, as shown in FIG. 3, an insulating film 8 is formed on the semiconductor substrate 1. As the insulating film 8, a silicon oxide film or the like formed by the CVD method can be used.

In the manufacturing process of the semiconductor integrated circuit device described above, the p-channel MOSFET is formed on the semiconductor substrate 1, but the p-channel MOSFET is formed on the semiconductor substrate 1.
It is possible to adopt a mode in which various semiconductor elements such as n-channel MOSFETs, bipolar transistors, and capacitive elements other than the above are formed.

The manufacturing process of the semiconductor integrated circuit device described above can be performed by combining various prior arts. The main part of the semiconductor integrated circuit device and the manufacturing method thereof according to the present invention is the wiring layer of the semiconductor integrated circuit device and the manufacturing method thereof. Based on this, in order to simplify the description hereafter, the semiconductor substrate 1 formed by the above-described manufacturing process is used as the starting material for the p-channel M.
A substrate 9 on which an OSFET is formed is comprehensively illustrated, the internal structure of the substrate 9 having an internal structure is omitted, and the dimensions shown in the drawing are reduced.

Next, as shown in FIG. 4, the lower wiring layer 10 is formed on the surface of the substrate 9. The lower wiring layer 10 is formed by sputtering a tungsten layer, for example. As a material for the lower wiring layer 10, a single wiring layer such as an aluminum layer or a lower layer or an upper layer thereof is provided for the tungsten layer as the lower wiring layer 10 in order to secure the characteristics of stress migration resistance and electromigration resistance. As the wiring layer, a wiring layer obtained by stacking a wiring structure using a refractory metal layer such as a tungsten layer or a titanium nitride (TiN) layer can be used. As the lower wiring layer 10, a combination of electrically conductive materials such as a polycrystalline silicon layer or a laminated layer of a polycrystalline silicon layer and a high melting point silicide layer can be used.

The lower wiring layer 10 includes a wiring layer electrically connected to the n-type semiconductor region 7 through a through hole provided in the insulating film 8 in a region (not shown). It also includes the wiring layers to be connected.

On the lower wiring layer 10, a pattern for the lower wiring layer is formed by using the photolithography technique and the selective etching technique.

Next, an interlayer insulating film 11 is formed on the entire surface so as to cover the lower wiring layer 10. The interlayer insulating film 11 forms an insulating film having excellent step coverage by a CVD method that employs a reaction of TEOS (tetraethoxysilane) and oxygen (TEOS-based reaction), for example.

As another aspect of the interlayer insulating film 11, for example, a silicon oxide film is formed by a CVD method, and then an SOG (Spin On Glass) film is used by a spin coating device (spinner) for flattening the surface. It is possible to adopt a mode in which it is formed as follows. The interlayer insulating film 11 is formed of, for example, a silicon oxide film by a CVD method, and then PSG (Phospho Silicon
cate glass) film or BPSG (Boro Phospho Silicat)
Various embodiments such as an interlayer insulating film having a laminated structure in which an e-Glass film or the like is formed by a CVD method can be adopted.

Next, a lower wiring layer 12 is formed on the surface of the interlayer insulating film 11 for the purpose of flattening the upper wiring layer.

The lower wiring layer is a wiring layer made of a material having an etching rate higher than that of an upper wiring layer described later.

Specifically, if the upper wiring layer is, for example, a wiring layer containing tungsten, the lower wiring layer is a polycrystalline silicon layer which is a wiring layer made of a material having a higher etching rate than the wiring layer containing tungsten. To do.

Next, a photoresist film 13 is formed on the surface of the lower wiring layer 12, and then the photoresist film 13 is patterned by using a photolithography technique for etching to form a through hole in the interlayer insulating film 11. A photoresist film 13 serving as a mask is formed.

Next, as shown in FIG. 5, by using the photoresist film 13 as an etching mask, the interlayer insulating film 12 is selectively etched by a dry etching method or a wet etching method. Is used as an etching mask, the lower wiring layer 12 is selectively removed, and then the interlayer insulating film under the lower wiring layer 12 is removed to form a through hole 14.

Next, as shown in FIG. 6, after removing the unnecessary photoresist film 13, the through hole 14 is removed.
And the upper wiring layer 15 is formed on the lower wiring layer 12.

In this case, a state occurs in which a part of the upper wiring layer 15 above the through hole 14 is depressed from the surroundings, and a recess is formed in the region of the upper wiring layer 15 above the through hole 14. 15a is formed.

The upper wiring layer 15 is formed by sputtering a tungsten layer, for example. Upper wiring layer 15
Can have various modes such as a wiring layer having a laminated structure made of the same material as the lower wiring layer 10 described above.

Next, as shown in FIG. 7, the upper wiring layer 15
A photoresist film 16 is formed on the surface of the.

Next, a pattern for the upper wiring layer is formed on the photoresist film 16 by using the photolithography technique.

Next, using the photoresist film 16 as an etching mask, the upper wiring layer 15 is selectively etched using a selective etching technique to pattern the upper wiring layer 15.

Next, as shown in FIG. 8, after the photoresist film 16 is removed, the upper wiring layer 15 is flattened and the dent 15a is removed. The flattening process is performed by chemical mechanical polishing (CMP).
The upper wiring layer 15 and the lower wiring layer 12 are removed from the surface thereof by a polishing process and an etching solution by using the lishing) method, whereby the surface of the upper wiring layer 15 can be flattened and the lower surface exposed. The wiring layer 12 can be removed.

In this case, the lower wiring layer 12 is the upper wiring layer 1
Since the etching rate is higher than 5, the lower wiring layer 12 functions as a sacrificial layer for etching, and the thickness of the upper wiring layer 15 can be smaller than the thickness of the lower wiring layer 12 that is etched in a certain time.

The upper wiring layer 15 and the lower wiring layer 12 are etched from the surface thereof by the CMP method to remove the dents 15a in the upper wiring layer 15, and the upper wiring layer 15 is flattened. In addition to the aspect in which the unnecessary upper wiring layer 15 is completely removed when the wiring pattern of the upper wiring layer 15 is formed, the upper wiring layer 15 in a region other than the wiring pattern of the upper wiring layer 15 is left to some extent. In this state, the upper wiring layer 15 may be planarized by the CMP method.

In the manufacturing process in which the upper wiring layer 15 is planarized by the CMP method, the photoresist film 1 is used.
6 can be removed by etching.

Further, the operation of sequentially removing the lower wiring layer 12 and the upper wiring layer 15 as the sacrificial film for etching from the surface thereof may be carried out by various etch back methods using wet etching or dry etching. it can.

In this case, the lower wiring layer 12 is the upper wiring layer 1
By using a material different from 5, it can be used as a wiring layer for detecting the etching end point in the etch back method.

Next, after repeating the manufacturing steps of the interlayer insulating film 11 and the upper wiring layer 15 to form a wiring layer having a multilayer wiring structure, a surface protection film such as a nitric oxide film is formed (not shown). By this, the manufacturing process of the semiconductor integrated circuit device is completed.

According to the method of manufacturing the semiconductor integrated circuit device of the present embodiment, the lower wiring layer 12 made of a material having a higher etching rate than the upper wiring layer 15 is formed on the interlayer insulating film 11.
And forming a photoresist film 13 serving as an etching mask on a part of the surface of the lower wiring layer 12, and then exposing the lower wiring layer 12 whose surface is exposed by using the photoresist film 13 as an etching mask. Interlayer insulation film 1
1 is etched to form the through hole 14, and after the upper wiring layer 15 is formed on the substrate 9 including the interlayer insulating film 11 in which the through hole 14 is formed, the surface of the upper wiring layer 15 is formed. The upper wiring layer 15 and the lower wiring layer 12 below the upper wiring layer 15 by etching from
Of the upper wiring layer 15 formed on the through hole 14 in the interlayer insulating film 11 by removing the unnecessary area of the upper wiring layer 15 and forming the pattern of the upper wiring layer 15. Even if the surface is not flattened due to unevenness generated on the surface of the upper wiring layer 15, the upper wiring layer 15 is etched from the surface of the upper wiring layer 15.
In the step of forming the pattern, since the lower wiring layer 12 made of a material having a higher etching rate than the upper wiring layer 15 is provided below the upper wiring layer 15, the upper wiring layer 1
5 can be flattened by a simple manufacturing process.

According to the method of manufacturing the semiconductor integrated circuit device of this embodiment, the upper wiring layer 15 is flattened,
A manufacturing process for removing the dent 15a is adopted. In the flattening process, the upper wiring layer 15 and the lower wiring layer 12 are removed from the surface by etching by using an etch back method or a CMP method, so that the upper wiring layer 1
The surface of No. 5 can be flattened, and the lower wiring layer 12 whose surface is exposed can be removed.

In this case, the lower wiring layer 12 is the upper wiring layer 1
Since the etching rate is higher than 5, the lower wiring layer 12 functions as a sacrifice layer for etching, and the thickness of the upper wiring layer 15 can be smaller than the thickness of the lower wiring layer 12 that is etched in a certain time.

As a result, the dent 15a is formed in the upper wiring layer 15.
Even if the above occurs, the upper wiring layer 15 can be flattened by the flattening process in the simple manufacturing process, so that the wiring layer of the multi-layer wiring structure can be formed at high density without deteriorating the characteristics of the upper wiring layer. it can.

Further, according to the method of manufacturing the semiconductor integrated circuit device of this embodiment, in order to prevent the occurrence of the depression 15a of the upper wiring layer 15, the through hole wiring layer is formed in the through hole 14 in the interlayer insulating film 11. Since it is not necessary to adopt a manufacturing method in which the upper wiring layer 15 is formed after being selectively embedded, the through-hole wiring layer and the upper wiring layer 1
Therefore, it is possible to avoid the problem that the characteristics of the upper wiring layer 15 are deteriorated due to the change of the film quality of the upper wiring layer 15 due to the difference of the film quality of No. 5 and the like.

Therefore, according to the method of manufacturing the semiconductor integrated circuit device of the present embodiment, the upper wiring layer 15 is dented in the manufacturing process of forming the upper wiring layer 15 on the interlayer insulating film 11 having the through holes 14. Since it can be flattened by a simple manufacturing process even if it occurs, a semiconductor integrated circuit device having a high-performance and high-density wiring layer can be easily manufactured.

(Embodiment 2) FIGS. 9 to 11 are sectional views showing a manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention. The semiconductor integrated circuit device and the manufacturing method thereof according to the present invention will be specifically described with reference to FIG.

The feature of the manufacturing process of the semiconductor integrated circuit device of this embodiment is that the upper wiring layer 1 is different from the manufacturing process of the flattened upper wiring layer 15 in the first embodiment described above.
5, an upper wiring layer 17 made of a material having an etching rate smaller than that of the upper wiring layer 15 is formed.
After the dent 15a of 5 is filled with the upper wiring layer 17, a flattening process is performed to flatten the upper wiring layer 15
Is to form

Therefore, the manufacturing process of the semiconductor integrated circuit device of the present embodiment will be described by omitting the manufacturing process similar to the manufacturing process of the semiconductor integrated circuit device of the first embodiment.

As shown in FIG. 9, upper wiring layer 15 is formed on through hole 14 and interlayer insulating film 11. The upper wiring layer 15 is formed by sputtering a tungsten layer, for example.

In this case, there occurs a state in which a part of the upper wiring layer 15 above the through hole 14 is depressed from the surroundings, and a recess is formed in the region of the upper wiring layer 15 above the through hole 14. 15a is formed.

Next, the upper wiring layer 17 for the purpose of flattening the upper wiring layer 15 is formed on the surface of the upper wiring layer 15.
The upper wiring layer 17 is a wiring layer made of a material having a smaller etching rate than the upper wiring layer 15.

Next, as shown in FIG. 10, etching is sequentially performed from the surface of the upper wiring layer 17 by an etch back method or a CMP method to remove unnecessary skin portions of the upper wiring layer 17 and the upper wiring layer 15 and flatten them. Process.

In this case, since the upper wiring layer 17 made of a material having an etching rate smaller than that of the upper wiring layer 15 is formed on the upper wiring layer 15, the upper wiring layer 17 is sequentially etched and removed. Since the upper wiring layer 17 can be left in the recess 15a of the upper wiring layer 15 in a buried state, the flattening process can be performed to form the flattened upper wiring layer 15.

Next, as shown in FIG. 11, a patterning upper wiring layer 15 is formed by removing unnecessary regions of the upper wiring layer 15 by using a photolithography technique and a selective etching technique.

As another aspect of the flattening treatment of the upper wiring layer 15, the upper wiring layer 15 and the upper wiring layer 15 and the upper wiring layer 17 which are patterned by using the photolithography technique and the selective etching technique are used. Layer 1
After forming 7, the flattening process may be performed by an etch back method or a CMP method.

According to the method of manufacturing the semiconductor integrated circuit device of this embodiment, a manufacturing process is employed in which the recess 15a of the upper wiring layer 15 is filled with the upper wiring layer 17 and then the upper wiring layer 15 is flattened. There is. In the flattening process, the surface of the upper wiring layer 15 can be flattened by removing the upper wiring layer 15 and the upper wiring layer 17 from the surface by etching using an etch back method or a CMP method.

In this case, the upper wiring layer 17 is the upper wiring layer 1
Since the etching rate is smaller than 5, the upper wiring layer 17 functions as a sacrificial layer for etching, and the thickness of the upper wiring layer 15 can be made larger than the thickness of the upper wiring layer 17 that is etched in a fixed time.

As a result, the dent 15a is formed in the upper wiring layer 15.
Even if a dent occurs, the upper wiring layer 15 can be flattened by a flattening process in a simple manufacturing process. Therefore, even if a dent occurs in the upper wiring layer 15, the upper wiring layer 15 can be flattened by a simple manufacturing process. Moreover, a semiconductor integrated circuit device having a high-density wiring layer can be easily manufactured.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the above-described embodiment, the MOSF
The semiconductor integrated circuit device having the ET provided on the semiconductor substrate and the method for manufacturing the same have been described as a bipolar transistor, an MO
B combining SFET and bipolar transistor
The present invention can be applied to a semiconductor integrated circuit device having various semiconductor elements such as an iMOS or BiCMOS structure and its manufacturing technology.

[0070]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

(1) According to the method for manufacturing a semiconductor integrated circuit device of the present invention, the step of forming a lower wiring layer made of a material having a higher etching rate than the upper wiring layer on the interlayer insulating film, and the lower wiring layer. After forming a photoresist film that will serve as an etching mask on part of the surface of the, the through holes are formed by etching the lower wiring layer and the interlayer insulating film whose surface is exposed using the photoresist film as an etching mask. And the step of forming an upper wiring layer on the base body including the interlayer insulating film in which the through holes are formed, and then etching from the surface of the upper wiring layer to form the upper wiring layer and the lower wiring layer thereunder. By removing unnecessary areas and forming a pattern of the upper wiring layer, The step of forming a pattern of the upper wiring layer by etching from the surface of the upper wiring layer even if the surface of the formed upper wiring layer has a dent and the surface is uneven and is not flattened. In the above, since the lower wiring layer made of a material having a higher etching rate is provided below the upper wiring layer, the upper wiring layer can be flattened by a simple manufacturing process.

(2) According to the method for manufacturing a semiconductor integrated circuit device of the present invention, a manufacturing process is performed in which the upper wiring layer is flattened and dents are removed. In the flattening process, the upper wiring layer and the lower wiring layer are removed from the surface by etching using an etch back method or a CMP method, whereby the surface of the upper wiring layer can be flattened and the surface is exposed. The lower wiring layer can be removed.

In this case, since the lower wiring layer has a higher etching rate than the upper wiring layer, the lower wiring layer functions as a sacrifice layer for etching, and the upper wiring layer is thicker than the thickness of the lower wiring layer etched in a certain time. Thickness can be reduced.

As a result, even if the upper wiring layer is dented, the upper wiring layer can be flattened by the flattening process by a simple manufacturing process, so that the characteristics of the upper wiring layer are not deteriorated and the multilayer wiring structure can be formed. The wiring layer can be formed with high density.

Further, according to the method of manufacturing the semiconductor integrated circuit device of the present embodiment, the through hole wiring layer is selectively embedded in the through hole in the interlayer insulating film in order to prevent the occurrence of the dent in the upper wiring layer. Since it is not necessary to adopt the manufacturing method of forming the upper wiring layer afterwards, the deterioration of the characteristics due to the change in the film quality of the upper wiring layer due to the difference in the film quality between the through-hole wiring layer and the upper wiring layer, etc. The problem of occurrence can be avoided.

Therefore, according to the method of manufacturing the semiconductor integrated circuit device of the present embodiment, even if the upper wiring layer is dented in the manufacturing process of forming the upper wiring layer on the interlayer insulating film having the through holes. Since it can be flattened by a simple manufacturing process, a semiconductor integrated circuit device having a high-performance and high-density wiring layer can be easily manufactured.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 11 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention.

[Explanation of symbols]

 1 semiconductor substrate 2 field insulating film 3 gate insulating film 4 gate electrode 5 insulating film 6 sidewall insulating film 7 n-type semiconductor region 8 insulating film 9 base 10 lower wiring layer 11 interlayer insulating film 12 lower wiring layer 13 photoresist film 14 through Hole 15 Upper wiring layer 15a Dimple 16 Photoresist film 17 Upper wiring layer

Claims (7)

[Claims] 1. A lower wiring layer on a substrate on which a plurality of semiconductor elements are provided, and an upper wiring layer electrically connected to the lower wiring layer through a through hole formed in an interlayer insulating film. A lower wiring layer made of a material having an etching rate higher than that of the upper wiring layer is provided below the upper wiring layer provided on the surface of the interlayer insulating film. A semiconductor integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein the upper wiring layer provided on the through hole formed in the interlayer insulating film is flat without dents. A characteristic semiconductor integrated circuit device. 3. The semiconductor integrated circuit device according to claim 1, wherein the upper wiring layer is a metal wiring layer containing tungsten, and the lower wiring layer provided under the upper wiring layer is multi-layered. A semiconductor integrated circuit device, which is a wiring layer made of crystalline silicon. 4. A step of forming a lower wiring layer on the surface of a substrate on which a plurality of semiconductor elements are formed, and a step of forming an interlayer insulating film on the substrate including the lower wiring layer, Forming a lower wiring layer made of a material having an etching rate higher than that of the upper wiring layer, and forming a photoresist film as an etching mask on a part of the surface of the lower wiring layer; A step of forming a through hole by etching the lower wiring layer and the interlayer insulating film whose surface is exposed by using as a mask for etching, and A step of forming an upper wiring layer on, by etching from the surface of the upper wiring layer,
And a step of removing an unnecessary region of the upper wiring layer and a lower wiring layer below the upper wiring layer to form a pattern of the upper wiring layer. 5. A step of forming a lower wiring layer on a surface of a substrate on which a plurality of semiconductor elements are formed, and a step of forming an interlayer insulating film on the substrate including the lower wiring layer, A step of forming a through hole by forming a photoresist film as an etching mask on a part of the surface and then etching the interlayer insulating film whose surface is exposed using the photoresist film as an etching mask; After forming an upper wiring layer on a substrate including an interlayer insulating film in which the through hole is formed, an upper wiring layer made of a material having a smaller etching rate than the upper wiring layer is formed on the upper wiring layer. By the step of forming and etching from the surface of the upper wiring layer,
And a step of removing an unnecessary region of the upper wiring layer and the lower wiring layer below the upper wiring layer to form a pattern of the upper wiring layer. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein an etching back method is used for the etching process for forming the pattern of the upper wiring layer. Device manufacturing method. 7. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein a CMP method is used for the etching process for forming the pattern of the upper wiring layer. Manufacturing method.