JPH0936067A - Semiconductor wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to prevent chipping and embody a low cost semiconductor. SOLUTION: In a semiconductor to be diced, a semiconductor wafer is provided with a chipping preventive epitaxial growth layer 11 provided in the form of a bank, which increases its thickness gradually and then reduces its thickness in the direction intersection a scribing line A, along both sides of the scribing line A of the semiconductor wafer so as to prevent the chipping 2 by the dicing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inexpensive semiconductor wafer which can prevent chipping.

[0002]

2. Description of the Related Art Generally, a semiconductor wafer is diced by a semiconductor process, for example, after a large number of identical ICs have been formed, and then separated into individual ICs.

[0003]

However, in such a process, when the semiconductor wafer is diced into chips, large and small chips (chipping) occur on the end faces of the chips. A large chip affects the characteristics of the chip and is treated as a defective chip by visual inspection.

Such chipping causes a decrease in yield. Also, an inspection process is required, which increases the manufacturing cost. The cause of this chipping is due to the diamond blade used in dicing. The larger the particle size of diamond and the coarser the particle size, the more likely chipping occurs.

Basically, it is impossible to cut a semiconductor wafer without chipping. FIG. 6 is an explanatory diagram of an example of dicing a conventional semiconductor wafer. In the figure, 1 indicates a semiconductor wafer and 2 indicates chipping by dicing.

The present invention solves this problem. An object of the present invention relates to a semiconductor wafer which can prevent chipping and is inexpensive.

[0007]

To achieve this object, the present invention provides a semiconductor wafer to be diced on both sides along the scribe line of the semiconductor wafer so as to prevent chipping due to dicing. A semiconductor wafer comprising a chipping-preventing epitaxial growth layer provided in the shape of a bank, the thickness of which gradually increases and then decreases in the orthogonal direction.

[0008]

In the above structure, the surface of the wafer is patterned in order to form the anti-chipping epitaxial growth layer. Apply resist. A chipping-preventing epitaxial growth layer is selectively epitaxially grown at a portion where the resist is not applied. The resist is removed. Dicing along the scribe line. Hereinafter, detailed description will be given based on examples.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an explanatory view of the essential parts of an embodiment of the present invention, showing a state after dicing. In the figure, the configuration of the same symbol as FIG. 6 represents the same function. Hereinafter, only differences from FIG. 6 will be described.

Numeral 11 is on both sides along the scribe line A of the semiconductor wafer 1 in a direction orthogonal to the scribe line A so as to prevent chipping due to dicing.
It is an anti-chipping epitaxial growth layer provided in the shape of a dike that gradually increases in thickness and then decreases.

In the above structure, the device of the present invention is shown in FIG.
~ Produced as shown in FIG. (1) As shown in FIG. 2, predetermined patterning is performed on the surface of the semiconductor wafer 101. The resist 102 is applied. In this case, the semiconductor wafer 101 is made of silicon,
Silicon oxide is used for the resist 102.

(2) As shown in FIG. 3, a chipping prevention epitaxial growth layer 103 is selectively epitaxially grown at a portion where the resist 102 is not applied.

(3) As shown in FIG. 4, the resist 102 is removed. (4) As shown in FIG. 5, along the scribe line A,
Perform dicing. The cut width by dicing and the interval between the chipping prevention epitaxial growth layers 103 do not have to be completely the same.

As a result, (1) the semiconductor wafer 1 in which chipping due to dicing is unlikely to occur is obtained.

(2) Even if chipping occurs, since the chipping prevention epitaxial growth layer 11 exists, the chipping prevention epitaxial growth layer 11 can provide the semiconductor wafer 1 in which chipping is less likely to occur and large chipping is less likely to occur.

By (3), (1) and (2), the semiconductor wafer 1 in which defects due to chipping are reduced and the yield is improved can be obtained. Further, the appearance inspection of chipping becomes unnecessary, and the semiconductor wafer 1 which can reduce the manufacturing cost can be obtained.

[0017]

As described above, according to the present invention, in a semiconductor wafer to be diced, the thickness of the semiconductor wafer along the scribe line is perpendicular to the scribe line so as to prevent chipping due to dicing. A semiconductor wafer was constructed which was provided with a chipping-preventing epitaxial growth layer provided in the shape of a bank that gradually increases and then decreases.

As a result, (1) a semiconductor wafer in which chipping due to dicing is unlikely to occur is obtained. (2) Even if chipping occurs, the chipping prevention epitaxial growth layer exists, so that the chipping prevention epitaxial growth layer can provide a semiconductor wafer in which chipping is less likely to occur and large chipping is less likely to occur.

By (3), (1) and (2), defects due to chipping are reduced and a semiconductor wafer with improved yield can be obtained. Further, a visual inspection for chipping is not required, and a semiconductor wafer that can reduce manufacturing cost can be obtained.

Therefore, according to the present invention, chipping can be prevented and an inexpensive semiconductor wafer can be realized.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a main part configuration of an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a manufacturing process of FIG. 1, and is an explanatory diagram of a resist coating process.

FIG. 3 is an explanatory diagram of a manufacturing process of FIG. 1, and is an explanatory diagram of an epitaxial growth layer forming process.

FIG. 4 is an explanatory diagram of the manufacturing process of FIG. 1 and an explanatory diagram of the resist removing process.

FIG. 5 is an explanatory view of the manufacturing process of FIG. 1 and an explanatory view of the dicing process.

FIG. 6 is an explanatory diagram of a configuration of a conventional example generally used in the related art.

[Explanation of symbols]

 1 Semiconductor Wafer 2 Chipping 11 Chipping Prevention Epitaxial Growth Layer 12 Chipping 101 Semiconductor Wafer 102 Resist 103 Chipping Prevention Epitaxial Growth Layer

Claims (1)

[Claims] 1. In a semiconductor wafer to be diced, along a scribe line of the semiconductor wafer on both sides along a scribe line of the semiconductor wafer so as to prevent chipping due to dicing, the thickness gradually increases in a direction orthogonal to the scribe line, and then decreases. A semiconductor wafer comprising an anti-chipping epitaxial growth layer provided.