JPH0934864A - Single chip microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the single chip microcomputer in which an application program is corrected while being mounted on a device without increasing the number of terminals of the single chip microcomputer. SOLUTION: An ACL terminal 23 and a TEST terminal 24 in the single chip microcomputer 11 are part of external connection terminals prepared in advance for program operation. When a debug program stored in a monitor ROM 16 is started, a connection state in a terminal input signal selector 20 is switched to send/receive data required for debugging the user program to/ from a terminal equipment 31 via the ACL terminal 23 and the TEST terminal 24.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ROM (Read Onl
y Memory) is a device-incorporated single-chip microcomputer that executes a program written in the memory.

[0002]

2. Description of the Related Art Conventionally, a generally used single-chip microcomputer (hereinafter simply referred to as "microcomputer") is used by being incorporated in a device and used by a user program stored in an internal ROM. We are in control. In a general mask ROM version microcomputer, there is no dedicated function for outputting the information inside the microcomputer or modifying the user program, so that it is installed in the equipment, that is, in the state where it actually operates. It is difficult to debug the user program. Further, even if the user program can be debugged, the user program is stored in the ROM of the microcomputer. Therefore, when the ROM is a mask ROM, it is difficult to rewrite the user program.

Development of the microcomputer as described above is performed by using ICE (In Circuit Emulator). When developing a microcomputer by ICE, an evaluation chip (hereinafter referred to as "ever chip") is used instead of a ROM or the like in which a user program is stored. The ever-chip has a structure that can take out not only the output from the terminal in the microcomputer but also the signal level in the signal lines connecting the internal components, and the number of terminals provided is large. Therefore, it cannot be incorporated in the same device as the ROM. Therefore, the ever chip and ICE such as the socket into which the ROM is inserted must be connected by a cable. Since they are connected by a cable, it is necessary to consider the effect of noise input through the cable.

Further, since the EverChip has a different manufacturing process from that of the mask ROM version microcomputer, it may have different electrical characteristics and the like, and there is a problem in using it for the final evaluation of the microcomputer.

An OTP as a single-chip microcomputer capable of directly evaluating the operation of a program by directly mounting the microcomputer in a device to be incorporated.
(One Time Programmable ROM) version is available. Since the OTP version is similar to the mask ROM version in appearance, it can be incorporated into a device to evaluate the operation of the program, but it does not have the function of outputting information inside the microcomputer to the outside. , It takes a lot of time to debug a program.

A first technique for solving the above-mentioned problems in the conventional technique is disclosed in Japanese Patent Laid-Open No. 4-332051.
No. 6,086,045. In the first prior art,
A ROM provided in the microcomputer stores a program for debugging together with a user program. Internal information is output to the terminal device via a communication interface provided in the microcomputer, and a debug command or the like is input from the terminal device. At the start of debugging, the entire contents of the ROM are read into the RAM in the microcomputer, and the program for debugging accesses the RAM.

The second technique is disclosed in Japanese Patent Laid-Open No. 3-2029.
No. 24 discloses this. In the second prior art, an interface with a device that stores a debugging program is provided in the microcomputer. Whether the user program is executed or the user program is debugged is selected depending on the switching state of terminals inside the microcomputer. In this prior art, the debugging program is stored in the debugging device outside the microcomputer, and the user program is read by loading it into the emulation memory of the debugging device. A command is input from a debug device via a microcomputer incorporated in the device to confirm the operation.

The third technique is disclosed in Japanese Patent Laid-Open No. 61-5805.
No. 2 discloses this. In the debug device according to the third prior art, a probe is inserted into the socket in which the ROM storing the application program is replaced with the ROM storing the application program, and signals are exchanged with the microcomputer. A user program to be debugged is stored in the RAM of the debugging device, and this program is debugged. The debug program is stored in the ROM in the debug device.

[0009]

SUMMARY OF THE INVENTION In the first prior art,
The terminal used for communication is a terminal exclusively for communication, which causes an increase in the number of terminals in the microcomputer.

Further, in the second prior art, in order to debug the user program, a device equipped with a program for debugging is separately required, and the debugging cannot be performed easily. Since there are a plurality of terminals for data transfer, the area required by the switching device for switching the terminals becomes large.

In the third prior art, a ROM probe is inserted in place of a ROM storing a user program and the like, and a signal is exchanged between the debug device and the microcomputer by inserting a ROM probe. It is becoming more difficult to emulate at the speed at which the user program actually operates while transmitting and receiving signals via the probe, due to the limit of timing specifications. Further, the connection by the probe may break a device such as a ROM socket to which the microcomputer is attached, which is problematic in terms of safety.

It is an object of the present invention to provide a single-chip microcomputer capable of modifying an application program in a state of being incorporated in a device without increasing the number of terminals in the single-chip microcomputer.

[0013]

SUMMARY OF THE INVENTION The present invention provides a microprocessor, an application program executed by the microprocessor, a ROM for storing a debug program for debugging the application program, an application program and a debug program. In a single-chip microcomputer that includes a RAM that temporarily stores information related to the above and a plurality of external connection terminals, it is possible to exchange information with an external device through some external connection terminals. A communication interface and control means for controlling to switch the functions of the part of the external connection terminals are provided, and the control means connects the part of the external connection terminals when a debugging program is started. To the interface for communication, When the Activation program is started is a single-chip microcomputer, wherein a switch for the program operation functions as a microcomputer. According to the present invention, in the single-chip microcomputer, the application program executed by the microprocessor and the debugging program are stored in the ROM. When debugging an application program, a debugging program is started. When the debugging program is activated, the control means switches the functions of some external connection terminals. The communication interface exchanges information with an external device via the external connection terminal whose function is switched. The debug program debugs the application program based on information supplied from an external device. When the application program is activated, the control means switches the external connection terminal for the program operation function to exchange information. Therefore, since the exchange of information with an external device necessary for debugging the application program is performed using a part of the external connection terminals whose functions are switched by the control means, the information for the debug is not provided. It is not necessary to provide terminals for exclusive use of transfer, and application programs can be debugged without increasing the area of the chip on which the single-chip microcomputer is formed.

The ROM of the present invention is characterized in that it is an electrically rewritable ROM. According to the invention, the ROM comprises an electrically rewritable ROM, for example a flash memory. Therefore,
The application program modified by the debugging program can be stored in the ROM with the single-chip microcomputer incorporated in the device.

Further, the above-mentioned some external connection terminals of the present invention are:
It is characterized in that it functions as an ACL terminal or a TEST terminal. According to the present invention, some external connection terminals for exchanging information with an external device during operation of the debug program are ACL or TEST terminals. Therefore, when performing the function as a single-chip microcomputer, the function of the external connection terminal, which is rarely used, is switched to exchange information with an external device. Therefore, when the application program is debugged, the function of the external connection terminal is changed. The control means can be realized by a simple circuit without the need to switch frequently.

[0016]

1 is a block diagram showing the structure of a single-chip microcomputer 11. As shown in FIG. A single-chip microcomputer (hereinafter simply referred to as a microcomputer) 11 is a CPU (central processing unit).
12, ROM (Read Only Memory) 13, and RAM
(Ramdom Access Memory) 14, comparator 19, terminal input signal selector 20, vector address generation circuit 21
And UART (Universal Asynchronous Receiver and T
ransmitter) 22 and includes a plurality of external connection terminals (not shown). In the microcomputer 11 of FIG. 1, AC is used as a part of external connection terminals.
The L (All CLear) terminal 23 and the TEST terminal 24 are shown.

The ROM 13 is composed of a user ROM 15 and a monitor ROM 16, and is an electrically rewritable ROM such as a flash memory. RA
M14 is a user RAM 17 and an emulated RAM 18
Composed of and. An address bus 25 and a data bus 26 are connected to the CPU 12. ROM13
And the RAM 14 are connected by the CPU 12, the address bus 25, and the data bus 26. Address bus 25
The address of the ROM 13 or the like is designated by, and data is exchanged via the data bus 26.

The user ROM 15 stores a user program which is an application program developed by the user, and the monitor ROM 16 stores a program for debugging the user program. The program for debugging controls communication with the external terminal device 31 and the start and stop of the user program stored in the user ROM 15.

In the user RAM 17, data is temporarily written when the user program stored in the user ROM 15 operates. The emulated RAM 18 is
It stores data and the like input from the terminal device 31 when the debugging program stored in the monitor ROM 16 is activated.

The UART 22 transmits and receives data in a serial manner by using two signal lines based on information such as a data transfer rate stored in advance in the monitor ROM 16 and the number of bits of data transferred at one time. To do. UA
Data is input to the RT 22 from the terminal device 31 via the terminal input signal selector 20. The data input to the UART 22 is input to the emulation RAM 18 and the vector address generation circuit 21.

The microcomputer 11 performs the same operation as when the power is turned on by inputting a predetermined high level signal or low level signal to the ACL terminal 23,
The value of the register or the like in the microcomputer 11 is cleared. When the level of the signal input to the TEST terminal 24 when the power is turned on is a predetermined level, the microcomputer 11 performs a process called a test mode so that the circuit in the microcomputer II operates normally. It is checked by inputting a signal according to a predetermined program.

FIG. 2 is a diagram showing a data format in the UART 22. FIG. 2A shows an example of a format in which the data portion is composed of 7 or 8 bits. In the 7 / 8-bit mode, bits 0 to n are successively added after a predetermined start bit.
A data portion composed of data up to (n is 7 or 8) is provided. When n is 7, a parity bit, which is 1-bit data, is provided following the data portion, but when n is 8, no parity bit is provided. A stop bit consisting of 1 or 2 bits is provided following the data part or the parity bit.

FIG. 2 (2) shows an example of a format in which the data portion is composed of 9 bits. In the 9-bit mode, a predetermined start bit is followed by a data portion composed of data from bit 0 to bit n and a parity bit. A stop bit consisting of 1 or 2 bits is provided following the data portion.

The comparator 19 compares the data on the address bus 25 and the data bus 26 with the data stored in the emulation RAM 18. The vector address generation circuit 21 receives the ACL signal and generates various interrupts, for example, based on the result of the comparison performed in the comparator 19, the user ROM 15 and the monitor ROM 1
The predetermined address in 6 is output. The vector address generation circuit 21 stores, for example, the start address of the debug program in the monitor ROM 16, and the program is executed based on the address output from the vector address generation circuit 21.

FIG. 3 is a block diagram showing the configuration of the terminal input signal selector 20. Terminal input signal selector 20
Includes a register 41, an auto reset circuit 42, a signal switching circuit 43, a signal input permission circuit 44, an input / output switching circuit 45, and a transistor 46.

The input / output switching circuit 45 includes a buffer 51.
A transistor 52 which is an n-type FET (Field Effect Transistor), a NAND gate 53, and a p-type FE
And a transistor 54 which is T. The signal switching circuit 43 is configured to include AND gates 55 and 56 and an OR gate 57, and the output of the AND gate 55 is input to one input terminal of the OR gate 57, and A
The output of the ND gate 56 is input to the other input terminal of the OR gate 57. The signal input permission circuit 44 includes an AND gate 58.

Although shown as one D flip-flop in FIG. 3, the register 41 is a terminal input signal selector 2
A plurality of 0s are provided, and an address for identifying each register 41 is assigned to each.
The data on the data bus 26 is written in the register 41 designated by the address value given via the address bus 25 based on the internal clock signal. When the internal clock signal is input to the input terminal CK of the register 41, the level of the signal input to the input terminal D is output from the output terminal Q, and the inverted output terminal QB outputs an inverted signal of the output terminal Q. Is output. The signal SEL1 output from the output terminal Q is input to one input terminal of the AND gate 58. Signal SEB output from output terminal QB
Is input to one of the input terminals of the AND gates 55 and 56, and is also input to the control terminal of the buffer 51.

The output of the auto reset circuit 42 is input to the reset terminal R of the register 41 and the other input terminal of the AND gate 55. The signal line 60 connected to the ACL terminal 23 is connected to the other input terminal of the AND gate 56 and AN.
It is connected to the other input terminal of D gate 58.

Buffer 5 in input / output switching circuit 45
1, a signal is input from the TEST terminal 24 through the signal line 59. The drain D of the transistor 46, which is a p-type FET, is connected to the signal line 59. In the transistor 46, the gate G is grounded and the source S is given a predetermined potential. Therefore, TEST
When there is no external input to the terminal 24, the level of the signal input to the input / output switching circuit 45 becomes high level.

The signal SEB is inputted to the buffer 51 as a control signal, and when the signal SEB becomes low level, the signal output of the buffer 51 becomes high impedance state. The output of the buffer 51 is the internal TEST signal NTE
Is supplied to other components in the microcomputer 11. The output of the buffer 51 is connected to the drain D of the transistor 54. In the transistor 54, the gate G is grounded and the source S is given a predetermined potential. Therefore, when the signal output of the buffer 51 is in the high impedance state, the internal TES
The T signal NTE becomes high level.

The drain D of the transistor 54 is further connected to the first input terminal of the NAND gate 53. N
The signal SEL1 is input to the second input terminal of the AND gate 53, and the output signal OUA from the UART 22 is input to the third input terminal. The output of the NAND gate 53 is given to the gate G of the transistor 52. In the transistor 52, the drain D is grounded and the source S is connected to the signal line 59.

The operation after the microcomputer 11 is powered on will be described. When the power is turned on, the auto reset circuit 42 outputs a positive pulse signal and the register 41 is reset. Therefore, the signal SEL1 goes low and the signal SEB goes high. Since the signal SEB is input to the control terminal of the buffer 51, the level of the signal input to the TEST terminal 24 is output as it is as the level of the internal TEST signal NTE. The internal TEST signal NTE becomes low level only when the microcomputer 11 is operated in the TEST mode.

The register 41 indicated by the address bus 25 latches the signal value of the data bus 26 input to the input terminal D in synchronization with the internal clock signal CK. When the signal input to the input terminal D is at high level, the signal SEL1 goes to high level. When the signal SEL1 goes high, the signal input to the ACL terminal 23 is input to the UART 22 as the UART input signal UA via the AND gate 58 of the signal input permission circuit 44. By supplying the output of the signal input permission circuit 44 to the UART 22, the debug program of the monitor ROM 16 is activated. The debug program emulates the value of the start address of the application program stored in the user ROM 15 in the emulation RAM 18
To memorize. The debug program also supplies predetermined data to the UART 22.

The UART 22 uses the predetermined data as the UART output signal OUA to output the terminal input signal selector 2.
0 is input to the input / output switching circuit 45. The output of the NAND gate 53 is determined by the signal level of the input data. Since the output of the NAND gate 53 is input to the gate G of the transistor 52, when the signal level of the data is high level, the transistor 52 becomes conductive and the output of the TEST terminal 24 becomes low level. When the signal level of the data is low level, the transistor 52 is cut off and the output signal from the TEST terminal 24 becomes high level.

The terminal device 31 has the ACL terminal 23 and the TE.
When connected to the ST terminal 24, the TEST terminal 2
The terminal device 31 supplies to the ACL terminal 23 data that is a response signal indicating that the terminal device 31 is connected to the ACL terminal 23 and the TEST terminal 24, based on the data input via 4.

In the microcomputer 11, T
If a response signal is not input from the terminal device 31 to the ACL terminal 23 within a predetermined time after the data is output from the EST terminal 24, it is determined that the terminal device 31 is not connected. That is, when the response signal is not input from the terminal device 31, the microcomputer 11 determines that it is not in the program debug mode.

If the response signal is not input from the terminal device 31, the debug program inputs a signal to the register 41 via the data bus 26, thereby registering the register 41.
Is cleared to set the input to the ACL terminal 23 as the internal ACL signal NAC, and the input to the TEST terminal 24 is set to the internal TEST.
It becomes the signal NTE. ACL terminal 23, TES
After the function of the T terminal 24 is switched, the start address of the user program stored in the emulation RAM 18 is returned to the address bus 25 to operate the user program.

When a response signal is input from the terminal device 31, the response signal is input to the UART 22 via the ACL terminal 23 and the signal input permission circuit 44. UART22
The ACL terminal 23 and the TEST terminal 24 are used as communication-dedicated terminals based on the response signal input to. Since it has been confirmed that the debug program is in the program debug mode, the debug program waits for a debug command that is subsequently input via the ACL terminal 23.

The processing in the program debug mode will be described. The debug command input in the terminal device 31 is input to the terminal input signal selector 20 via the ACL terminal 23. Further, it is input to the UART 22, stored in the emulation RAM 18 from the UART 22, and analyzed by the debug program.

When the analyzed command is a command for referring to internal data such as a register, the debug program fetches necessary information from the address bus 25 and the data bus 26 and outputs it to the UART 22. UAR
T22 transmits the given information to the terminal device 31 via the TEST terminal 24.

When the analyzed command is the setting of breakpoint data, the operating debug program stores the data sent from the terminal device 31 in the emulation RAM 18. When the analyzed command is a command for instructing execution of the user program, the start address of the user program stored in the emulation RAM 18 is set on the address bus 25, and the user program is executed from the indicated address. When the breakpoint data is set in advance when the user program is executed in the program debug mode, the breakpoint data and the data on the buses 25 and 26 are compared by the comparator 19.

If the breakpoint data stored in the emulation RAM 18 is an address value,
When this address value matches the address value transferred via the address bus 25, the user program is stopped. When the breakpoint data stored in the emulation RAM 18 is predetermined data other than the address value, the user program is stopped when this data matches the data transferred via the data bus 26. When the user program stops, the address of the stopped user program is stored in the emulation RAM 18 and the debug program in the monitor ROM 16 is started again.

FIG. 4 is a timing chart of each signal in the microcomputer 11. When the power supply shown in FIG. 4 (1) is turned on at time t0, the output of the auto reset circuit 42 shown in FIG. 4 (2) rises from the low "L" level to the high "H" level at time t1. . Since the output of the auto reset circuit 42 becomes high level, the internal ACL signal NA shown in FIG.
C rises. In addition, the TEST terminal 2 shown in FIG.
4 starts to rise, and the internal T shown in FIG.
The EST signal NTE begins to rise.

The output of the auto reset circuit 42 is output at time t.
When it falls to the low level at 2, the internal ACL signal NAC falls to the low level. Auto reset circuit 4
As the output of 2 goes low,
The signal SEL1 shown in (6) begins to rise and becomes high level at time t3. Since the signal SEL1 becomes high level, U shown in FIG.
The predetermined data described above as the ART output signal OUA is output to the terminal device 31 via the TEST terminal 24.
The data output from the TEST terminal 24 is shown in FIG.
As shown in (9), the signal OUA switches between high level and low level. The transmission of the data is performed in the period T1 from time t3 to time t4. Terminal device 3
When the data is input, the microcomputer 1 sends a response signal indicating that the terminal device 31 is connected.
Send to 1.

When the response signal sent from the terminal device 31 shown in FIG. 4 (4) is input to the ACL terminal 23 at time t5, it is input to the UART 22 as the UART input signal UA shown in FIG. 4 (5). It The reception of the response signal is performed in the period T2 from time t5 to time t6. In the period T2, the signal input to the ACL terminal 23 and the UART input signal UA have the same level. During the period T3 from the time t2 when the output of the auto reset circuit 42 falls to the time t6 when the reception of the response signal is completed, the start of the debugging program and the input of the response signal to the UART 22 are awaited. When the response signal is input in the period T2, the program debug mode is set after the time t6.

FIG. 5 is a flow chart showing the processing in the microcomputer 11. In step s1, it waits until the power is turned on. When the power is turned on, the process proceeds to step s2. In step s2, a signal is generated in the auto reset circuit 42 and the register 41
Is reset.

In the following step s3, it is determined whether or not the signal level of the internal TEST signal NTE is high level. When the signal level of the internal TEST signal NTE is the high level, the process proceeds to step s4. Step s4
Then, the signal output from the auto reset circuit 42 is stopped, and the reset state of the register 41 is released. Since the reset state has been released, the register 41 is set to the data bus 2
Take the value of 6 based on the internal clock signal. Therefore, the signal SE output from the output terminal Q of the register 41 is
L1 becomes high level.

When the signal SEL1 goes high, the signal level of the internal ACL signal NAC output from the signal switching circuit 43 goes low. In addition, the UART input signal UA output from the signal input permission circuit 44
The signal level of is determined based on the level of the signal input from the ACL terminal 23. That is, the ACL terminal 2
3 is an input terminal for a data signal sent from the terminal device 31.

At step s5, the monitor R is read based on the address designated by the vector address generation circuit 21.
The debugging program stored in the OM 16 is started. In addition, the start address of the user program stored in the user ROM 15 is the emulated RAM.
18 is stored.

In the following step s6, UART2
A predetermined signal is output from 2 and given to the terminal device 31 via the TEST terminal 24. The TEST terminal 24 serves as an output terminal for outputting a data signal to the terminal device 31. In step s7, the terminal device 31 for the predetermined signal
It is determined whether or not the response signal from is input through the ACL terminal 23. When the response signal is received, the program debug process described above is performed.

When the response signal is not received, it is determined that the terminal device 31 is not connected, and the signal S
Set EL1 to low level. When the signal SEL1 goes low, the signal input to the ACL terminal 23 is used as the internal ACL signal NAC in the microcomputer 11, and the signal input to the TEST terminal 24 is used as the internal TEST signal NTE. Further, the start address of the user program stored in the emulation RAM 18 is read and the user program is activated.

At step s3, the TEST terminal 23
When it is determined that the signal input to the microcomputer is low level, the microcomputer 11 enters the test mode described above.

As described above, according to this embodiment of the present invention, when the microcomputer 11 is activated, the AC
It is confirmed whether the terminal device 31 is connected to the L terminal 23 and the TEST terminal 24. When the terminal device 31 is connected, the terminal input signal selector 20 switches the function of the terminal to make the ACL terminal 23 and the TEST terminal 24 dedicated terminals for communication. Since the program for debugging the user program is stored in the monitor ROM 16, the terminal device 31 may have a configuration capable of displaying the transmitted data and inputting a debug command. The program can be easily debugged without the need to use a dedicated device for.

Further, since the functions of the ACL terminal 23 and the TEST terminal 24 are terminals which are not often used during the normal program operation function, the terminal input signal selector 2
The structure of 0 can be a simple structure.

In this embodiment of the present invention, RO
M13 is a rewritable ROM, but mask R
Even when a non-rewritable ROM such as an OM is used, the debug information can be read out through the terminal input signal selector 20, so that the debugging can be performed with the microcomputer 11 actually attached to the device. It can be performed.

[0056]

As described above, according to the present invention, a part of the connection terminals whose functions are switched by the control means is used for exchanging information with an external device necessary for debugging an application program. Since it is performed, it is not necessary to provide a terminal for exclusive use of communication in the single-chip microcomputer, and the application program stored in the ROM in the state of being attached to the device without increasing the area of the chip on which the single-chip microcomputer is formed. Can be debugged.

Further, according to the present invention, since the ROM is composed of an electrically rewritable ROM, the application program can be modified by the debug program while the single-chip microcomputer is still incorporated in the equipment. Therefore, the application program can be easily debugged, and the time required for developing the application program can be shortened. Further, since the debugging program can be rewritten, the user's own control can be performed.

Further, according to the present invention, when the function of the microcomputer is performed, the function of the external connection terminal which is less frequently used is switched to exchange information with an external device, so that the application program can be debugged. The control means can be realized by a simple circuit without the need to frequently switch the function of the external connection terminal.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a single-chip microcomputer 11 which is an embodiment of the present invention.

FIG. 2 is a diagram showing a data format in a UART 22.

3 is a block diagram showing a configuration of a terminal input signal selector 20. FIG.

4 is a timing chart of each signal in the microcomputer 11. FIG.

FIG. 5 is a flowchart showing processing in the microcomputer 11.

[Explanation of symbols]

 11 Single Chip Microcomputer 12 CPU 13 ROM 14 RAM 15 User ROM 16 Monitor ROM 17 User RAM 18 Emulated RAM 19 Comparator 20 Terminal Input Signal Selector 21 Vector Address Generation Circuit 22 UART 23 ACL Terminal 24 TEST Terminal 25 Address Bus 26 Data Bus 31 Terminal

Claims (3)

[Claims] 1. A ROM for storing a microprocessor, an application program executed by the microprocessor, and a debugging program for debugging the application program.
In a single-chip microcomputer including a RAM for temporarily storing information related to an application program and a debugging program, and a plurality of external connection terminals, an external device and information are provided through some external connection terminals. A communication interface capable of exchanging data, and control means for controlling so as to switch the functions of the part of the external connection terminals, and the control means is configured to operate when the debugging program is activated. A single-chip microcomputer characterized by switching the connection of some external connection terminals to a communication interface and switching to a program operation function as a microcomputer when an application program is started. 2. The ROM is an electrically rewritable R
The single-chip microcomputer according to claim 1, which is an OM. 3. The single-chip microcomputer according to claim 1, wherein the part of the external connection terminals functions as an ACL terminal or a TEST terminal.