JP2003122594A - Semiconductor device and evaluation tool - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately emulate a microprocessor when a power supply is re-turned on. SOLUTION: An emulation circuit 1a emulates a micro processor function. An interface circuit 1b has a function as an interface when data is exchanged between the emulation circuit 1a and an evaluation tool 3, and holds specified data on the micro processor. A first power supply circuit 1c supplies a power from a target board 2 to the emulation circuit 1a. A second power supply circuit 1d supplies a power from the evaluation tool 3 to the interface circuit 1b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and an evaluation device, and more particularly to a semiconductor device and an evaluation device which emulate a function of a microprocessor mounted on a target board to be evaluated and supply an emulation result to an evaluation tool. The present invention relates to an evaluation device having a semiconductor device that emulates a function of a microprocessor mounted on a target board that is a target and an evaluation tool that evaluates an emulation result by the semiconductor device.

[0002]

2. Description of the Related Art When developing a system having a microprocessor, the consistency between the microprocessor and peripheral devices is inspected and, for example, a ROM (Read O
It is necessary to check whether the firmware stored in nly memory) operates normally.

When performing such inspection, it is necessary to monitor the internal state of the microprocessor and stop the execution at an arbitrary position of the firmware. Therefore,
This evaluation device is manufactured by manufacturing an evaluation device having a function of emulating the function of a microprocessor and a function of monitoring the internal state of the microprocessor, and connecting the evaluation device to a board (hereinafter referred to as a target board) of a system to be developed. Conventionally, the above inspection has been performed by sending a command from a personal computer or the like.

FIG. 8 shows a configuration example of a conventional evaluation system for inspecting a microprocessor. As shown in this figure, the conventional system includes a target board 10, an evaluation microcomputer 12, an evaluation tool 14, and a personal computer 16.

Here, the target board 10 is a printed wiring board of a system to be developed, in which a plurality of semiconductor devices, electronic parts and the like are arranged and a socket 10a into which a microprocessor is inserted is arranged. There is.

The evaluation microcomputer 12 has a function of a microprocessor to be inserted into the socket 10a and a function of monitoring the microprocessor. The evaluation microcomputer 12 is connected to the socket 10a by the cable 11 and exchanges data with the target board 10. Further, the evaluation microcomputer 12 is connected to the evaluation tool 14 by the cable 13, receives the ROM data and the control signal, executes the corresponding processing, and transmits the obtained data to the evaluation tool 14.

The evaluation tool 14 generates ROM data (firmware data stored in the ROM) based on the data supplied from the personal computer 16, supplies the ROM data to the evaluation microcomputer 12, and controls the evaluation microcomputer 12. A control signal for generating is generated and supplied to the evaluation microcomputer 12. Further, the data acquired from the evaluation microcomputer 12 is supplied to the personal computer 16.

The personal computer 16 supplies ROM data to the evaluation tool 14 via the cable 15 and also supplies a control signal for controlling the evaluation microcomputer 12. In addition, the personal computer 16
Acquires and analyzes the data collected by the evaluation microcomputer 12.

Next, the operation of the above conventional example will be described. The user operates the personal computer 16,
The control signal is supplied to the evaluation microcomputer 12, the microprocessor is changed from the emulation mode (described later) to the debug mode (described later), and the setting according to the environment of the target board 10 is performed. As specific setting items, a ROM area in the address space, a ROM mask area (use prohibited area), and the like are set.

Here, the emulation mode is a normal operation mode in which the evaluation microcomputer 12 operates by supplying ROM data to the microprocessor, and the debug mode is for setting the internal state of the evaluation microcomputer 12. This is the operation mode of.

Next, the user selects the R to be debugged.
The OM data is sent from the personal computer 16 to the evaluation tool 14 and supplied to the evaluation microcomputer 12. In the evaluation microcomputer 12, the microprocessor is the evaluation tool 14
Based on the ROM data supplied from the above, various arithmetic processes are executed and each part of the target board 10 is controlled. At this time, the evaluation tool 14 uses the evaluation microcomputer 1
The internal state of the second microprocessor is monitored and notified to the personal computer 16.

The personal computer 16 acquires the information about the internal state supplied from the evaluation tool 14 at a predetermined timing (for example, when a predetermined command is executed) and displays it in association with the ROM data. It is possible to know whether or not the ROM data is operating normally. In addition, when it is not executed normally, it is possible to debug by changing the ROM data.

[0013]

In recent years, microprocessors have been installed in mobile phones and home electric appliances, and it is necessary to confirm the operation of the microprocessors installed in these products as well. .

By the way, these products, unlike, for example, a personal computer, are often turned off and restarted without a predetermined procedure.
Therefore, it is necessary to verify that the system does not malfunction even in such a case.

By the way, in the conventional evaluation system, since the power supply of the evaluation microcomputer 12 is supplied from the target board 10, when the power supply is cut off and then turned on again,
The above-mentioned data set in the evaluation microcomputer 12 may be erased.

Therefore, when the power is turned on again, it is necessary to shift to the debug mode, reset these data, and restore the emulation mode. Therefore, extra time is required accordingly. However, there is a problem in that it is impossible to monitor the accurate operating status when the power is turned on.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device and an evaluation device capable of accurately monitoring the operation when the power is turned on again.

[0018]

In order to solve the above problems, the present invention emulates the function of a microprocessor mounted on a target board 2 to be evaluated, as shown in FIG. In the semiconductor device 1 to be supplied to the semiconductor device 3, the emulation circuit 1a for emulating the function of the microprocessor.
And the emulation circuit 1a and the evaluation tool 3
Power is supplied from the target board 2 to the interface circuit 1b that holds a predetermined data related to the microprocessor and the emulation circuit 1a while having a function as an interface for transmitting data between the target board 2 and the interface circuit 1b. A first power supply circuit 1c,
The evaluation tool 3 for the interface circuit 1b
And a second power supply circuit 1d for supplying power from the semiconductor device.

Here, the emulation circuit 1a emulates the function of the microprocessor. The interface circuit 1b has a function as an interface when transmitting data between the emulation circuit 1a and the evaluation tool 3, and holds predetermined data related to the microprocessor. First power supply circuit 1c
Supplies power from the target board 2 to the emulation circuit 1a. The second power supply circuit 1d is
Power is supplied from the evaluation tool 3 to the interface circuit 1b.

In a semiconductor device that emulates the function of a microprocessor mounted on a target board to be evaluated and supplies an emulation result to an evaluation tool, an emulation circuit that emulates the function of the microprocessor, With respect to the emulation circuit and the interface circuit, an interface circuit having a function as an interface when transmitting data between the emulation circuit and the evaluation tool, a holding circuit that holds predetermined data relating to the microprocessor, And a second power supply circuit for supplying power from the evaluation tool to the holding circuit, and a second power supply circuit for supplying power from the target board. To be done.

Here, the emulation circuit emulates the function of the microprocessor. The interface circuit has a function as an interface when transmitting data between the emulation circuit and the evaluation tool. The holding circuit holds predetermined data related to the microprocessor. The first power supply circuit supplies power to the emulation circuit and the interface circuit from the target board. The second power supply circuit supplies power to the holding circuit from the evaluation tool.

Further, in the evaluation device having a semiconductor device that emulates a function of a microprocessor mounted on a target board to be evaluated and an evaluation tool that evaluates a result emulated by the semiconductor device, The device has an emulation circuit that emulates the function of the microprocessor, and a function as an interface when transmitting data between the emulation circuit and the evaluation tool, and also stores predetermined data related to the microprocessor. An interface circuit for holding, a first power supply circuit for supplying power from the target board to the emulation circuit, and a second power supply circuit for supplying power from the evaluation tool to the interface circuit, Having Evaluation device is provided, wherein.

Here, the emulation circuit of the semiconductor device emulates the function of the microprocessor.
The interface circuit has a function as an interface when transmitting data between the emulation circuit and the evaluation tool, and holds predetermined data related to the microprocessor. The first power supply circuit supplies power to the emulation circuit from the target board. The second power supply circuit supplies power to the interface circuit from the evaluation tool.

The semiconductor device emulating the function of a microprocessor mounted on a target board to be evaluated, and an evaluation tool for evaluating a result emulated by the semiconductor device, The apparatus includes an emulation circuit that emulates the function of the microprocessor, an interface circuit that functions as an interface when transmitting data between the emulation circuit and the evaluation tool, and a predetermined microprocessor related to the microprocessor. A holding circuit that holds data, a first power supply circuit that supplies power to the emulation circuit and the interface circuit from the target board, and a second power supply circuit that supplies power to the holding circuit from the evaluation tool. Power supply Evaluation device is provided, characterized in that it comprises a circuit.

Here, the emulation circuit of the semiconductor device emulates the function of the microprocessor.
The interface circuit has a function as an interface when transmitting data between the emulation circuit and the evaluation tool. The holding circuit holds predetermined data related to the microprocessor. The first power supply circuit is
Power is supplied from the target board to the emulation circuit and interface circuit. The second power supply circuit supplies power to the holding circuit from the evaluation tool.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a principle diagram for explaining the operation principle of the present invention. As shown in this figure, a semiconductor device 1 of the present invention is configured by an emulation circuit 1a, an interface circuit 1b, a first power supply circuit 1c, and a second power supply circuit 1d, and is mounted on a target board 2. It emulates the function of the microprocessor, and supplies the result of the emulation to the evaluation tool 3.

The target board 2 is a board to be evaluated, and a cable is connected to the socket in which the microprocessor is to be mounted, and is connected to the semiconductor device 1 via this cable.

The evaluation tool 3 supplies a control signal for controlling the semiconductor device 1 and ROM data to be debugged, acquires an emulation result,
For example, it is supplied to a personal computer (not shown) or the like for display.

Here, the emulation circuit 1a of the semiconductor device 1 emulates the function of the microprocessor to be mounted on the target board 2. The interface circuit 1b has a function as an interface when transmitting data between the emulation circuit 1a and the evaluation tool 3, and holds predetermined data related to the microprocessor.

The first power supply circuit 1c supplies power from the target board 2 to the emulation circuit 1a. The second power supply circuit 1d supplies power from the evaluation tool 3 to the interface circuit 1b.

Next, the operation of the above principle diagram will be described. (1) Operation when Environment Setting of Semiconductor Device 1 When the power of the target board 2 and the evaluation tool 3 is turned on, the first power supply circuit 1c supplies the power supplied from the target board 2 to the emulation circuit 1a. Supply to. The second power supply circuit 1d also supplies the power supplied from the evaluation tool 3 to the interface circuit 1b. As a result, the emulation circuit 1a and the interface circuit 1b become operable.

Then, the reset sequence is executed,
The target board 2 indicates the address (start address) at which the ROM data to be first executed by the emulation circuit 1a is stored.

When the reset sequence is completed, the emulation circuit 1a makes a read request of ROM data from the start address to the evaluation tool 3. As a result, the evaluation tool 3 reads out a tool program (a program for setting the environment) and supplies it to the semiconductor device 1. As a result, the emulation circuit 1a follows the interface circuit 1 according to the supplied tool program.
By setting the registers and the like included in b, the environment is set according to the target board 2.

(2) When the operating environment setting for executing the user program is completed, the evaluation tool 3 sets the semiconductor device 1
A control signal is sent to and the reset sequence is executed again. As a result, the address at which the ROM data to be first executed by the emulation circuit 1a is stored,
That is, the start address is indicated from the target board 2.

When the reset sequence is completed, the emulation circuit 1a makes a read request of ROM data from the start address to the evaluation tool 3. As a result, the evaluation tool 3 reads the user program (program to be debugged) and supplies it to the semiconductor device 1. As a result, the emulation circuit 1a executes various arithmetic processes according to the supplied user program and controls each unit of the target board 2.

At this time, by setting an appropriate breakpoint by the evaluation tool 3, the program execution is stopped at an arbitrary position of the user program, and the state of the internal register of the emulation circuit 1a at that time is monitored. By doing so, it becomes possible to debug the user program.

(3) Operation when the power is cut off When the power of the target board 2 is cut while the user program is being executed, the power supply from the first power supply circuit 1c is cut off. The emulation circuit 1a stops its operation. On the other hand, since the interface circuit 1b is supplied with power from the second power supply circuit 1d and the evaluation tool 3 is still supplied with power, the interface circuit 1b maintains the operating state.

(4) Operation when power is turned off and then on again When the target board 2 is turned on again, power is supplied from the first power supply circuit 1c to the emulation circuit 1a. Is resumed. As a result, the emulation circuit 1a becomes operable. At this time, since the interface circuit 1b is still being supplied with power from the second power supply circuit 1d, the set data is retained, so that it is not necessary to newly set.

Therefore, the operation (2) can be performed by omitting the operation (1) described above. Here, since the normal microprocessor performs the operation of (2) immediately after the power is turned on (however, the execution of the reset sequence is started by a request from the target board side is different), the power is turned on again. In this case, an operation equivalent to that of a normal microprocessor can be realized.

As described above, according to the present invention, the emulation circuit 1a is supplied with power from the target board 2 and the interface circuit 1b is supplied with power from the evaluation tool 3. Even when the power supply of the board 2 is cut off, power is supplied to the interface circuit 1b from the evaluation tool 3, so that the data contained in the interface circuit 1b can be prevented from being erased. As a result, when the power supply of the target board 2 is turned on again, the user program can be executed immediately without resetting the interface circuit 1b, so that an emulation result equivalent to that of a normal microprocessor can be obtained. it can.

Next, an embodiment of the present invention will be described. FIG. 2 is a diagram showing a configuration example of the embodiment of the present invention. As shown in this figure, the system according to the embodiment of the present invention includes a target board 10, an evaluation microcomputer 18, an evaluation tool 14, and a personal computer 16. In addition, comparing with the case of FIG.
The evaluation microcomputer 12 is replaced with the evaluation microcomputer 18, but otherwise the same as in the case of FIG.

Here, the target board 10 is a printed wiring board of a system to be developed, in which a plurality of semiconductor devices, electronic parts and the like are arranged and a socket 10a into which a microprocessor is inserted is arranged. There is.

The evaluation microcomputer 18 has a function of a microprocessor to be inserted into the socket 10a and a function of monitoring the microprocessor. The evaluation microcomputer 18 is connected to the socket 10a by the cable 11 and exchanges data with the target board 10.
Further, the evaluation microcomputer 18 is connected to the evaluation tool 14 by the cable 13, receives the control data and executes the corresponding processing, and transmits the obtained data to the evaluation tool 14.

The evaluation tool 14 generates ROM data (firmware data stored in the ROM) based on the data supplied from the personal computer 16, supplies the ROM data to the evaluation microcomputer 18, and controls the evaluation microcomputer 18. A control signal for generating is generated and supplied to the evaluation microcomputer 18. Furthermore, the evaluation tool 14 supplies the data acquired from the evaluation microcomputer 18 to the personal computer 16.

The personal computer 16 supplies ROM data to the evaluation tool 14 and also supplies a control signal for controlling the evaluation microcomputer 18. Further, the personal computer 16 has an evaluation microcomputer 18
Obtain and analyze the data collected by.

FIG. 3 is a diagram showing a detailed configuration example of the evaluation microcomputer 18. As shown in this figure, the evaluation microcomputer 1
8 is terminals t1 to t12, buffers b1 to b10, CP
It is configured by a U (Central Processing Unit) 20, a level converter 21, an evaluation unit 22, a peripheral resource 23, a power supply line 24, and a power supply line 25.

Here, the terminal t1 is the target board 1
Power supply from 0, buffers b1 to b7, CP
It is supplied to the U20, the level converter 21, and the peripheral resource 23.

The terminals t2 to t6 are connected to the target board 10 via the cable 11, and the target board 1
The data output from 0 is supplied to the buffers b1 to b5, and the data output from the buffers b1 to b5 is supplied to the target board 10 via the cable 11.

The terminals t7 and t8 are connected to the target board 10 via the cable 11, and the target board 1
The data output from 0 is supplied to the buffers b6 and b7, and the data output from the buffers b6 and b7 is supplied to the target board 10 via the cable 11.

The buffers b1 to b5 absorb the difference in data transfer rate by temporarily storing data when data is transferred between the CPU 20 and the target board 10.

Similarly, the buffers b6 and b7 temporarily store the data when the data is transferred between the peripheral resource 23 and the target board 10 to absorb the difference in the data transfer rate.

The CPU 20 is a microprocessor to be mounted on the target board 10, has the same function as a mass-produced processor, and has the level converter 2
The process according to the ROM data supplied from 1 is executed,
The data obtained as the processing result is converted into the level converter 2
1 to the evaluation unit 22. Also, ROM
The target board 10 and the peripheral resources 23 are controlled according to the data.

The level converter 21 converts the signal level so that data can be accurately transmitted and received between the CPU 20 and the evaluation unit 22. The evaluation unit 22 has an interface function and also has a register for environment setting therein, and the register setting is performed by CP of the tool program supplied from the evaluation tool 14.
It is performed by the execution of U20. In addition, an interrupt is generated based on the data set in the register, and CP
It causes U20 to execute a predetermined process.

The peripheral resource 23 is a peripheral device of the CPU 20, for example, RAM (Random Access Memory),
It is composed of an I / F (Interface), a timer, and the like. The power supply line 24 supplies the power output from the target board 10 to the buffers b1 to b7, the CPU 20, the level converter 21, and the peripheral resource 23.

The power supply line 25 supplies the power output from the evaluation tool 14 to the buffers b8 to b10, the evaluation unit 22 and the level converter 21. Next, a detailed configuration example of the evaluation tool 14 shown in FIG. 2 will be described with reference to FIG.

As shown in FIG. 4, the evaluation tool 14 includes an evaluation signal interface 30, a ROM data generator 31,
The control signal generation unit 32 and the serial interface 33 are included.

The EVA signal interface 30 communicates with the evaluation microcomputer 18 by an Eva (Evaluation) signal, that is,
Send and receive evaluation signals. The ROM data generation unit 31 generates and stores ROM data from the data supplied from the personal computer 16 via the serial interface 33, and stores the ROM data specified by the address signal supplied via the evaluation signal interface 30. It is read and supplied to the evaluation microcomputer 18.

The control signal generator 32 generates a control signal from the data supplied from the serial interface 33, and sends the control signal and acknowledge to the evaluation microcomputer 18 via the evaluation signal interface 30.
Send and receive signals.

The serial interface 33 is, for example,
It is configured by a USB (Universal Serial Port) or the like, and converts the format of the data supplied from the personal computer 16 into the expression format inside the evaluation tool 14.

Next, the operation of the above embodiment will be described. In the following, the operation ((1.1) to (1.
5)), and then the operation ((2.1) to (2.2)) at the time of restart.

As a premise for the following operation to be executed, it is necessary that the tool program and the user program are created in the personal computer 16 and are stored in, for example, a built-in storage device. In the personal computer 16, these programs are described in, for example, a compiled language and are translated by a compiler to be converted into a group of instructions executable by the evaluation microcomputer 18.

(1) Operation when power is turned on for the first time (1.1) Operation at startup Power is turned on to the personal computer 16, then to the evaluation tool 14, and finally to the evaluation microcomputer 18. When the power is turned on, the target board 10
From the power supply line 24 to the CPU 20, the level converter 21, the peripheral resources 23, and the buffers b1 to b1.
Power is supplied to b7. Further, from the evaluation tool 14 via the power supply line 25, the buffers b8 to b10,
Power is supplied to the evaluation unit 22 and the level converter 21. As a result, the evaluation microcomputer 18 becomes operable.

(1.2) Reset Sequence Operation When the CPU 20 becomes operable, the reset sequence is executed. That is, first, a signal for designating whether to read data from the internal ROM or the external ROM is sent to the target board 1 to the mode terminal of the CPU 20.
Supplied from 0. In the present example, a signal for selecting the internal ROM is input.

Subsequently, the personal computer 16 supplies the data designating the start address of the tool program (the program for initializing the internal registers and the like of the evaluation unit), and this data is supplied to the evaluation tool 1.
After being temporarily stored in the ROM data generation unit 31 of No. 4, it is supplied to the CPU 20 of the evaluation microcomputer 18.

(1.3) Execution Operation of Tool Program The CPU 20 accesses the address corresponding to the start address of the ROM data generator 31 and requests the reading of data. At this time, since the tool program supplied from the personal computer 16 is stored in the ROM data generation unit 31 starting from the address corresponding to the start address, the ROM data generation unit 31 is supplied from the evaluation signal interface 30. The data corresponding to the specified start address is acquired, and the evaluation signal interface 30
Is supplied to the evaluation microcomputer 18 via.

The evaluation microcomputer 18 has terminals t10 to t12.
The data supplied via the
After being temporarily stored in b10, it is supplied to the level converter 21 via the evaluation unit 22.

The level converter 21 converts the received data into a signal level corresponding to the power supply voltage of the target board 10, and then supplies the signal level to the CPU 20. CPU20
Executes the received ROM data. Since this ROM data is the tool program as described above, C
In accordance with this program, the PU 20 sends data specifying the ROM area and data specifying the mask area,
Set in the register built into the evaluation unit. As a result, the CPU 20 can refer to the set data and read the data from an appropriate area. That is, the CPU 20 can obtain address space mapping information.

(1.4) Reset Sequence Operation When the environment setting data is stored in the evaluation unit as described above, the personal computer 16 sends a control signal for resetting the evaluation microcomputer 18 to the evaluation tool 1
Send to 4. The control signal generator 32 of the evaluation tool 14 acquires this control signal from the serial interface 33,
Evaluation microcomputer 18 via evaluation signal interface 30
Supply to.

The evaluation microcomputer 18 receives this control signal and supplies it to the CPU 20 via the evaluation unit 22 and the level converter 21. As a result, since the CPU 20 executes the reset, the second reset sequence is executed.

When the reset sequence is executed, first, the target board 10 supplies to the mode terminal of the CPU 20 a signal designating whether to read data from the internal ROM or the external ROM. In the present example, a signal for selecting the internal ROM is input.

Subsequently, a user program (program created by the user) is sent from the personal computer 16.
Is supplied to the CPU 20 of the evaluation microcomputer 18 after being temporarily stored in the ROM data generation unit 31 of the evaluation tool 14.

(1.5) Execution Operation of User Program The CPU 20 accesses the address corresponding to the start address of the ROM data generator 31 and requests the reading of data. At this time, since the user program supplied from the personal computer 16 is stored in the ROM data generation unit 31 starting from the address corresponding to the start address, the ROM data generation unit 31 is supplied from the evaluation signal interface 30. The data corresponding to the start address is acquired and supplied to the evaluation microcomputer 18 via the evaluation signal interface 30.

In the evaluation microcomputer 18, the supplied data is read via the terminals t10 to t12, temporarily stored in the buffers b8 to b10, and then supplied to the level converter 21 via the evaluation unit 22.

The level converter 21 converts the received data into a signal level corresponding to the power supply voltage of the target board 10, and then supplies the signal level to the CPU 20. CPU20
Executes the received ROM data, that is, the user program. As a result, the CPU 20 executes various arithmetic processes according to the user program and controls each unit of the target board 10.

At this time, by setting a break point from the personal computer 16, the user program can be stopped at an arbitrary position and the contents of the register at that time can be referred to. The user program can be debugged by arbitrarily setting the stop position and referring to the register value at that time.

(2) Operation at Reboot (2.1) Operation at Power Off The state in which the user program is being executed ((1.
In (5) state), when the power supply to the target board 10 is cut off, the power supply from the target board 10 is cut off, so that the CPU 20, the buffers b1 to b7,
The power supply to the level converter 21 and the peripheral resources 23 is cut off.

As a result, the CPU 20 and the peripheral resources 23
Etc. are stopped. At this time, since power is supplied to the level converter 21 from the evaluation tool 14 side, even if the power from the target board 10 is suddenly cut off, noise that causes a malfunction may occur. It can be prevented from being transmitted to the evaluation tool 14 side.

(2.2) Operation when power is turned on again When the target board 10 is turned on again, the CPU 20, the level converter 21, the peripheral resources 23, and the buffers b1 to b1 are supplied via the power supply line 24.
Power is supplied to b7. As a result, the evaluation microcomputer 18
Is ready for operation.

(2.3) Reset Sequence Operation When the CPU 20 becomes operable, the reset sequence is executed. That is, first, a signal for designating whether to read data from the internal ROM or the external ROM is sent to the target board 1 to the mode terminal of the CPU 20.
Supplied from 0. In the present example, a signal for selecting the internal ROM is input.

Subsequently, data specifying the start address of the user program is supplied from the personal computer 16, and this data is temporarily stored in the ROM data generator 31 of the evaluation tool 14 and then the evaluation microcomputer 18
Is supplied to the CPU 20.

(2.4) Execution Operation of User Program The CPU 20 accesses the address corresponding to the start address of the ROM data generator 31 and requests the reading of data. At this time, the ROM data generator 31
Since the user program stored in (1.5) is held as it is, the ROM data generation unit 31 acquires the data corresponding to the start address supplied from the evaluation signal interface 30, and outputs the evaluation signal interface. It is supplied to the evaluation microcomputer 18 via 30.

In the evaluation microcomputer 18, the supplied data is read via the terminals t10 to t12, temporarily stored in the buffers b8 to b10, and then supplied to the level converter 21 via the evaluation unit 22.

The level converter 21 converts the received data into a signal level according to the power supply voltage of the target board 10 and then supplies the signal level to the CPU 20. CPU20
Executes the received ROM data, that is, the user program. As a result, the user program will be executed again.

According to the above-described embodiment, even if the power is cut off, the evaluation tool 22 is provided in the evaluation unit 22.
Since the power is supplied from the device and the data set in the internal register is retained, the user program can be directly executed without executing the tool program when restarting. Here, in the case of a mass-produced chip, the user program is directly executed upon restarting as in the embodiment of the present invention, so that it is possible to perform an operation check under the same conditions as the mass-produced chip.

Further, since the level converter 21 is arranged between the CPU 20 and the evaluation unit 22, noise generated when the power source of the target board 10 is cut off is transmitted to the evaluation tool 14 side to induce a malfunction. Can be prevented. Also, the target board 10 is
Since various types of power supply voltages are used, the evaluation microcomputer 18 can be normally operated regardless of what voltage is selected.

Next, the flow of the above processing will be briefly described with reference to a flowchart. FIG. 5 is a flowchart for explaining the operation when the power is turned on in the embodiment of the present invention. The flow of processing when the power is turned on will be described below. It should be noted that this flowchart corresponds to (1.1) to (1.5) described above.

Step S10: The user turns on the personal computer 16, the evaluation tool 14, and the target board 10 (corresponding to (1.1) described above).

Step S11: A signal for selecting the external ROM or the internal ROM is supplied to the mode terminal of the CPU 20, and a reset sequence for supplying the start address of the tool program is executed (the above-mentioned (1.2)). Corresponding to).

Step S12: For the internal register of the evaluation unit 22, data designating the ROM area and R
The tool program for setting the data designating the mask area of the OM is executed (corresponding to (1.3) described above).

Step S13: The signal for selecting the external ROM or the internal ROM is supplied to the mode terminal of the CPU 20, and the reset sequence for supplying the start address of the user program is executed (the above-mentioned (1.4)). Corresponding to).

Step S14: The user program to be debugged is executed (corresponding to (1.5) above).

Next, with reference to FIG. 6, the operation when the power of the target board 10 is once cut off and then restarted will be described. It should be noted that this flowchart corresponds to (2.1) to (2.4) described above.

Step S20: The power of the target board 10 is turned on by the user (corresponding to the above (2.2)).

Step S21: A signal for selecting the external ROM or the internal ROM is supplied to the mode terminal of the CPU 20, and a reset sequence for supplying the start address of the user program is executed ((2.3) described above). Corresponding to).

Step S22: The user program to be debugged is executed (corresponding to (2.4) above).

By the way, the flow chart shown in FIG.
This embodiment corresponds to the operation when the mass-production chip is restarted as well as the operation when the mass-production chip is restarted. Therefore, even in the case of restarting, it becomes possible to perform debugging under an operating environment closer to that of the actual product as compared with the conventional example in which the operation shown in FIG. 5 is executed.

Next, a second embodiment of the present invention will be described. FIG. 7 is a diagram showing a configuration example of the second exemplary embodiment of the present invention. In this figure, parts corresponding to those of the first embodiment of the present invention shown in FIG. 3 are designated by the same reference numerals, and detailed description thereof will be omitted.

In the second embodiment shown in FIG. 7, the evaluation unit 22 is different from the evaluation unit 40 in comparison with the case of FIG.
Has been replaced by. In addition, the CPU 20 and the evaluation unit 2
The level converter 21 disposed between the two is excluded, the level converter 41 and the register macro 42 are newly added, and the evaluation unit 40 and the buffer b8 to
The level converter 43 is newly added between b10. The other configurations are the same as those in the case of FIG.

Here, the evaluation unit 40 does not include the registers built in the evaluation unit 22. The excluded register is the register macro 42.
Is arranged outside the evaluation unit 40.

The level converter 41 comprises the evaluation unit 4
0 and the register macro 42, the signal output from the evaluation unit 40 is converted into a signal level corresponding to the power supply voltage of the register macro 42, and the signal output from the register macro 42 is evaluated. Four
The signal level corresponding to the power supply voltage of 0 is converted.

The register macro 42 corresponds to the register built in the evaluation unit 22 shown in FIG. The register macro 42 is supplied with power from the evaluation tool 14.

The level converter 43 includes the evaluation unit 4
The signal level is converted so that the signal level of 0 and the signal levels of the buffers b8 to b10 match each other. The power supply line 24 receives the current output from the target board 10 from the buffers b1 to b7, the CPU 20, and the peripheral resources 2.
3, evaluation unit 40, and level converter 4
1, 43, and the power supply line 25 is connected to the evaluation tool 14
The power output from the buffers b8 to b10, the level converters 41 and 43, and the register macro 42 are supplied.

The operation of the above embodiment will be briefly described below while clarifying the difference from the case of FIG. In the embodiment shown in FIG. 7, in (1.3) described above, the data to be stored in the evaluation unit 40 is
It is stored in the register macro 42 via the level converter 41. In addition, (1.5) and (2.4) described above
3 is the same as the operation of the first mode shown in FIG. 3 except that the CPU 20 refers to the register macro 42 via the level converter 41 to grasp the mapping status of the address space.

By the way, the CPU 20 and the evaluation unit 40
The wiring between and is connected to the evaluation unit 40 and the register macro 4.
Wiring between the two, the evaluation unit 40 and the buffers b8 to b
More than the total number of wires between 10 and. Therefore, as shown in FIG. 3, the level converter 21 arranged between the CPU 20 and the evaluation unit 22 is excluded, and as shown in FIG. 7, between the register macro 42 and the evaluation unit 40,
By arranging between the evaluation unit 40 and the buffers b8 to b10, it becomes possible to reduce the number of level converter elements required for each wiring. As a result, the circuit scale can be reduced.

Needless to say, the above embodiments are merely examples, and the present invention is not limited to such a circuit configuration. In addition, the evaluation microcomputer 18 in the above-described embodiment is, for example, a CMOS
It can also be implemented as a semiconductor device by a process or the like.

Furthermore, although the evaluation microcomputer 18 and the evaluation tool 14 have different structures in the above-described embodiments, they may be integrated into a single structure. (Supplementary Note 1) In a semiconductor device that emulates a function of a microprocessor mounted on a target board to be evaluated and supplies an emulation result to an evaluation tool, an emulation circuit that emulates the function of the microprocessor and the emulation. An interface circuit having a function as an interface when transmitting data between a circuit and the evaluation tool and holding predetermined data relating to the microprocessor, and a power supply from the target board to the emulation circuit. A semiconductor device comprising: a first power supply circuit for supplying power; and a second power supply circuit for supplying power from the evaluation tool to the interface circuit.

(Supplementary Note 2) The semiconductor device according to Supplementary Note 1, wherein a level converter is arranged between the emulation circuit and the interface circuit.

(Additional remark 3) The peripheral circuit of the microprocessor is further provided, and the first power supply circuit also supplies power to the peripheral circuit from the target board. Semiconductor device.

(Supplementary Note 4) In a semiconductor device that emulates the function of a microprocessor mounted on a target board to be evaluated and supplies an emulation result to an evaluation tool, an emulation circuit that emulates the function of the microprocessor is provided. , An interface circuit having a function as an interface when transmitting data between the emulation circuit and the evaluation tool, a holding circuit for holding predetermined data relating to the microprocessor, the emulation circuit and the interface circuit A semiconductor device comprising: a first power supply circuit that supplies power to the target board from the target board; and a second power supply circuit that supplies power to the holding circuit from the evaluation tool. .

(Supplementary Note 5) The semiconductor device according to Supplementary Note 4, wherein level converters are respectively arranged between the interface circuit and the holding circuit and between the interface circuit and the evaluation tool.

(Additional remark 6) The peripheral circuit of the microprocessor is further provided, and the first power supply circuit also supplies power to the peripheral circuit from the target board. Semiconductor device.

(Supplementary Note 7) In an evaluation device having a semiconductor device that emulates a function of a microprocessor mounted on a target board to be evaluated, and an evaluation tool that evaluates a result emulated by the semiconductor device, The semiconductor device has an emulation circuit that emulates the function of the microprocessor and a function as an interface when data is transmitted between the emulation circuit and the evaluation tool, and also has a predetermined function related to the microprocessor. An interface circuit that holds data, a first power supply circuit that supplies power to the emulation circuit from the target board, and a second power supply circuit that supplies power to the interface circuit from the evaluation tool. And have An evaluation device characterized in that

(Supplementary Note 8) The evaluation apparatus according to Supplementary Note 7, wherein a level converter is arranged between the emulation circuit and the interface circuit. (Supplementary Note 9) The evaluation device according to Supplementary Note 8, further comprising a peripheral circuit of the microprocessor, wherein the first power supply circuit supplies power to the peripheral circuit from the target board. .

(Supplementary Note 10) In an evaluation device having a semiconductor device that emulates a function of a microprocessor mounted on a target board to be evaluated, and an evaluation tool that evaluates a result emulated by the semiconductor device, The semiconductor device relates to an emulation circuit that emulates a function of the microprocessor, an interface circuit that functions as an interface when data is transmitted between the emulation circuit and the evaluation tool, and the microprocessor. A holding circuit that holds predetermined data, a first power supply circuit that supplies power to the emulation circuit and the interface circuit from the target board, and a power supply that supplies power to the holding circuit from the evaluation tool. Second An evaluation device, comprising: a power supply circuit.

(Additional remark 11) A level converter is arranged between the interface circuit and the holding circuit, and between the interface circuit and the evaluation tool.

(Additional remark 12) The peripheral circuit of the microprocessor is further provided, and the first power supply circuit supplies power to the peripheral circuit from the target board. Evaluation device.

[0117]

As described above, according to the present invention, in the semiconductor device that emulates the function of the microprocessor mounted on the target board to be evaluated and supplies the emulation result to the evaluation tool, the function of the microprocessor is A target for the emulation circuit, which has a function as an interface for transmitting data between the emulation circuit and the evaluation tool, and which holds predetermined data related to the microprocessor, and the emulation circuit. Since the first power supply circuit that supplies power from the board and the second power supply circuit that supplies power from the evaluation tool to the interface circuit are provided, the power supply to the target board is cut off and the power is restored. If started Also, since the predetermined data stored in the interface does not disappear, without performing the reconfiguration, it is possible to emulate. Therefore, it becomes possible to perform emulation in a state close to that when using a normal mass-produced chip.

In a semiconductor device that emulates the function of a microprocessor mounted on a target board to be evaluated and supplies the emulation result to an evaluation tool, an emulation circuit that emulates the function of the microprocessor and an emulation circuit. Interface circuit that has a function as an interface when transmitting data between the evaluation tool and the evaluation tool, a holding circuit that holds predetermined data related to the microprocessor, and a power supply from the target board to the emulation circuit and the interface circuit. Since the first power supply circuit for supplying power and the second power supply circuit for supplying power from the evaluation tool to the holding circuit are provided, the circuit scale can be reduced.

In addition, in the evaluation device having the semiconductor device that emulates the function of the microprocessor mounted on the target board to be evaluated and the evaluation tool that evaluates the result emulated by the semiconductor device, the semiconductor device is An emulation circuit that emulates the function of the microprocessor, and an interface circuit that has a function as an interface when transmitting data between the emulation circuit and the evaluation tool and that holds predetermined data related to the microprocessor, Since the first power supply circuit that supplies power from the target board to the emulation circuit and the second power supply circuit that supplies power from the evaluation tool to the interface circuit are provided, Accurate operation at closing It is possible to evaluate.

In addition, in the evaluation device having the semiconductor device that emulates the function of the microprocessor mounted on the target board to be evaluated and the evaluation tool that evaluates the result emulated by the semiconductor device, the semiconductor device is , An emulation circuit that emulates the function of a microprocessor, and an interface circuit that has a function as an interface when transmitting data between the emulation circuit and the evaluation tool,
A holding circuit that holds predetermined data relating to the microprocessor, a first power supply circuit that supplies power to the emulation circuit and the interface circuit from the target board, and a first power supply circuit that supplies power to the holding circuit from the evaluation tool. Since the second power supply circuit is provided, it is possible to accurately evaluate the operation when the power is turned on again and reduce the circuit scale.

[Brief description of drawings]

FIG. 1 is a principle diagram illustrating an operation principle of the present invention.

FIG. 2 is a diagram showing a configuration example of an embodiment of the present invention.

FIG. 3 is a diagram showing a detailed configuration example of the evaluation microcomputer shown in FIG.

4 is a diagram showing a detailed configuration example of the evaluation tool shown in FIG.

FIG. 5 is a flowchart showing a flow of operations when the power is turned on in the embodiment shown in FIG.

FIG. 6 is a flowchart showing a flow of operations when the power is turned on again in the embodiment shown in FIG.

7 is a diagram showing a configuration example of a second embodiment of the evaluation microcomputer shown in FIG.

FIG. 8 is a diagram showing a configuration example of a conventional evaluation system.

[Explanation of symbols] 1 Semiconductor device 1a Emulation circuit 1b interface circuit 1c First power supply circuit 1d Second power supply circuit 2 target board 3 evaluation tools 10 target board 10a socket 11 cable 12 Evaluation microcomputer 13 cables 14 Evaluation tool 15 cables 16 personal computer 18 Evaluation microcomputer 20 CPU 21 level converter 22 Evaluation unit 23 peripheral resources 24 power lines 25 power lines 30 EVA signal interface 31 ROM data generator 32 control signal generator 33 Serial interface 40 evaluation units 41 level converter 42 register macro 43 level converter

Continued front page    (72) Inventor Norihiro Nakatsuhama             4-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa             No. 1 within Fujitsu Limited (72) Inventor Naoya Watanabe             4-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa             No. 1 within Fujitsu Limited F-term (reference) 5B011 DB21 EA08 EB01                 5B048 AA12 AA13 BB02 DD08 FF01                 5B062 DD00 HH03 JJ05

Claims (10)

[Claims] 1. A semiconductor device that emulates a function of a microprocessor mounted on a target board to be evaluated and supplies an emulation result to an evaluation tool; and an emulation circuit that emulates the function of the microprocessor. An interface circuit that has a function as an interface when transmitting data between the emulation circuit and the evaluation tool, and that holds predetermined data related to the microprocessor, and a power supply from the target board to the emulation circuit. And a second power supply circuit that supplies power to the interface circuit from the evaluation tool. 2. The semiconductor device according to claim 1, wherein a level converter is arranged between the emulation circuit and the interface circuit. 3. The microprocessor according to claim 1, further comprising a peripheral circuit of the microprocessor, wherein the first power supply circuit also supplies power to the peripheral circuit from the target board. Semiconductor device. 4. A semiconductor device that emulates a function of a microprocessor mounted on a target board to be evaluated and supplies an emulation result to an evaluation tool; and an emulation circuit that emulates the function of the microprocessor. An interface circuit having a function as an interface when transmitting data between the emulation circuit and the evaluation tool, a holding circuit that holds predetermined data related to the microprocessor, and the emulation circuit and the interface circuit. A semiconductor device, comprising: a first power supply circuit that supplies power from the target board to the target board; and a second power supply circuit that supplies power to the holding circuit from the evaluation tool. 5. The semiconductor device according to claim 4, wherein level converters are respectively arranged between the interface circuit and the holding circuit and between the interface circuit and the evaluation tool. 6. The microprocessor according to claim 4, further comprising a peripheral circuit of the microprocessor, wherein the first power supply circuit supplies power to the peripheral circuit from the target board. Semiconductor device. 7. An evaluation device having a semiconductor device that emulates a function of a microprocessor mounted on a target board to be evaluated, and an evaluation tool that evaluates a result emulated by the semiconductor device, The device has an emulation circuit that emulates the functions of the microprocessor, and a function as an interface when data is transmitted between the emulation circuit and the evaluation tool, and stores predetermined data related to the microprocessor. An interface circuit for holding, a first power supply circuit for supplying power from the target board to the emulation circuit, and a second power supply circuit for supplying power from the evaluation tool to the interface circuit, To have Evaluation device characterized by. 8. The evaluation device according to claim 7, wherein a level converter is arranged between the emulation circuit and the interface circuit. 9. An evaluation device having a semiconductor device that emulates a function of a microprocessor mounted on a target board to be evaluated, and an evaluation tool that evaluates a result emulated by the semiconductor device, wherein the semiconductor The apparatus includes an emulation circuit that emulates the functions of the microprocessor, an interface circuit that functions as an interface when transmitting data between the emulation circuit and the evaluation tool, and a predetermined microprocessor related to the microprocessor. A holding circuit that holds data, a first power supply circuit that supplies power to the emulation circuit and the interface circuit from the target board, and a second power supply circuit that supplies power to the holding circuit from the evaluation tool Power supply An evaluation device comprising: a circuit. 10. The evaluation device according to claim 9, wherein level converters are arranged between the interface circuit and the holding circuit and between the interface circuit and the evaluation tool, respectively.