JPH09331316A - Phase adjustment circuit for uninterruptible changeover system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the transmission quality and maintenance performance by preventing 2nd momentary interruption in an uninterruptible changeover block when the changeover is conducted at the outside of the uninterruptible changeover block. SOLUTION: When phase adjustment at start is finished, a delay adjustment control circuit 5 stores a relation of a phase of a write timing to a memory 2 at that time and a phase of a read timing from the memory 2 to a start time phase storage circuit 6. In the case that a relation of write and read phases to/from the memory 2 is not clear in a phase adjustment section of both an active system and a standby system, the delay adjustment control circuit 5 compares the current relation of the phase of the write timing to the memory 2 and the read timing from the memory 2 with the relation of the phase stored in the start time phase storage circuit 6. When the difference between the phase relations exceeds a preset criterion, the delay adjustment control circuit 5 executes the phase adjustment and when the difference between the phase relations does not exceed the preset criterion, the delay adjustment control circuit 5 does not execute the phase adjustment.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase adjusting circuit for a hitless switching system, and more particularly to a phase adjusting circuit for a hitless switching system for switching between a working transmission line and a standby transmission line without any interruption. The present invention relates to a phase adjustment technique for matching the delay amounts of a transmission path and a protection transmission path.

[0002]

2. Description of the Related Art Conventionally, in a hitless switching system of this type, as shown in FIG. 3, two signals, an active system and a standby system, are interfaced (IF) from outside the non-interruptible switching section.
When received by the units 11 and 12, the interface unit 11,
Phase information adding section 1 for each of the signals received at 12
At 3 and 14, phase information for delay time adjustment of non-instantaneous interruption switching is added.

Here, the phase information added by the phase information adding sections 13 and 14 is generally a frame pattern having a cycle sufficiently longer than the difference in transmission line delay time between the active system and the standby system in the non-instantaneous interruption switching section. Is used and this frame pattern is inserted by utilizing the unused bit portion in the data signal.

That is, since the transmission path length is not always the same in the active system and the standby system, and the delay times in the interface units 11 and 12 have some variations, as shown in FIG. Even if the transmitted information is the same for the standby system signal and the standby system signal, the signals do not always arrive at exactly the same time.

In general, the transmitted signal, in addition to the information signal I,
Various management information such as a frame synchronization byte F for separating the information signal I and various management information in the receiving unit and an unused spare byte R are time-division multiplexed [FIG. See a)].

In the non-instantaneous-interruption switching method, a part of the management information (spare byte R) is used to transmit a frame pattern P as phase information, and the receiving unit receives this frame pattern P.
Phase adjustment is performed based on the above [see FIG. 5 (b)]. The frame synchronization byte F, the spare byte R, and the frame pattern P have a size of 1 byte.

The active system phase information adding section 13 and the standby system phase information adding section 14 receive the same signal, but some time lags occur. In the receiving section, the phase adjustment sections 21 and 22 synchronize the frames by using the phase adjustment frame patterns P inserted on the transmission side, respectively, and the delay time difference generated due to the difference in the transmission path length or the like is used for the phase adjustment sections 21 and 22. It is absorbed by the internal memory, and signals having the same phases in the active system and the standby system are sent to the selection units 23 and 24.

The signals to which the phase information is added by the phase information adding units 13 and 14 are selected by the selecting units 15 and 16, and then the active system transmission of the non-interruption switching section is performed by the interface units 17 and 18. And the protection transmission line. The selection units 15 and 16 are units that perform redundant system switching of transmission lines outside the non-interruption switching section, and the selection units 15 and 16 are controlled so as to always select the same system.

That is, the selection units 15 and 16 belong to both the non-instantaneous-interruption switching section and the non-instantaneous-interruption switching section, and the switching sections partially overlap at the boundary section (selection sections 15 and 16). , Which constitutes a seamless redundant system. Note that the selection units 23 and 24 also belong to both the non-instantaneous-interruption switching section and the non-instantaneous-interruption switching section, like the selection units 15 and 16.

As a result, in the non-instantaneous interruption switching section, the signal to which the same phase information is added is always sent to both the working transmission path and the protection transmission path.

In the receiving section of the signal transmitted through the active transmission path and the standby transmission path in the non-instantaneous interruption switching section, the interface sections 19 and 20 receive the signals from the active transmission path and the standby transmission path, respectively. Then, the signals are sent to the phase adjusters 21 and 22, respectively.

The phase adjusters 21 and 22 align the signal phases of the working transmission path and the protection transmission path using the phase information inserted on the transmission side. As shown in FIG. 4, the phase adjustment units 21 and 22 include a frame synchronization circuit 31, a memory 32, a write counter (W ADDRCTR) 33, a read counter (RADDDR CTR) 34, and a delay adjustment control circuit 35. It consists of

The frame synchronization circuit 31 detects the frame pattern inserted on the transmitting side, controls the write counter 33 using the detected frame pattern, and writes the write counter 3
In 2, a write address to the memory 32 (elastic store) is generated.

For example, the head of the frame is written in the head address (address 0) of the memory 32, and then the received signals are sequentially written in the memory 32. When the frame synchronization circuit 31 receives the signal of the beginning of the next frame, the writing of the beginning of the frame is started from the beginning address of the memory 32, as described above.

The frame synchronization circuit 31 delays the synchronization detection signal indicating that the received signals are synchronized and the frame timing indicating that the phase information (frame pattern) is received for each frame as synchronization information. It outputs to the adjustment control circuit 35 and the delay adjustment control circuit 35 of the other system, respectively.

The delay adjustment control circuit 35 compares the frame timing output from the frame synchronization circuit 31 of its own system with the frame timing output from the frame synchronization circuit 31 of the other system, and based on the comparison result, the read counter 3
Control 4

For example, the delay time difference between the receiving frame patterns of the active system and the standby system is calculated, and the reading is performed with a delay of a certain time from the writing phase of the system that received the delay,
Control to prevent memory slip.

By the above operation, the same signal is output in the same phase from the active phase adjuster 21 and the standby phase adjuster 22. Therefore, even if the selectors 23 and 24 switch between the active system and the standby system, no instantaneous interruption of signals occurs at the outputs of the interface units 25 and 26.

Since the clocks on the transmitting side and the receiving side are normally synchronized, if the read counter 34 is controlled once when the apparatus is started, the read signal is read even if the received signal is temporarily cut off due to a transmission line failure or the like. By continuously operating the counter 34, the memory 32 can be recovered when the failure is recovered.
The phase relationship of writing and reading is restored to the initially set phase relationship.

When the failure occurs only in one of the working system and the standby system, the delay adjustment control circuit 35 of the system receiving the normal signal of either one writes to the memory 32 at the frame timing. And the timing of reading can be monitored. Therefore, it is not necessary to adjust the phase when the failure is recovered.

However, when a failure occurs in both the active system and the standby system at the same time, the phase relationship of writing and reading to and from the memory 32 becomes unknown in the phase adjusting units 21 and 22 of the active system and the standby system. If this occurs, it is necessary to adjust the phase when the fault is restored.

[0022]

In the above-mentioned conventional phase adjustment method, since the phase state is not stored even after the phase adjustment is completed once, the frame synchronization of both the active system and the standby system is lost, and the phase is lost. The phase is adjusted again when the information disappears.

In general, the signal input to the active phase information adding section (active system signal) and the signal input to the standby phase information adding section (spare system signal) are not aligned.
Therefore, the relative position of the empty bit for inserting the frame pattern is also different between the active system and the standby system.

In the case of the above-mentioned method, when the switching of the preceding stage (outside the non-interruption interruption switching section) is executed in the non-interruption interruption switching section input section, for example, the switching is executed by the selecting sections 15 and 16 of FIG. In this case, discontinuity occurs in the data sequence in the signal, and the instantaneous interruption of the signal occurs at the receiving sections of both the active system and the standby system in the non-instantaneous interruption switching section.

Further, since the insertion positions of the frame patterns are also different, as shown in FIG. 6, this switching causes a loss of synchronism in the frame synchronizing circuit in the phase adjusting section on the receiving side, and the synchronization pull-in operation is started.

After synchronization is established in the frame synchronization circuit, the phase adjustment is performed again as described above, and the read counter of the memory is set to the optimum read phase. The second interruption of the signal occurs due to the setting of the read counter. That is, in the conventional hitless switching method, if the switching operation is performed outside the hitless switching section, the hitless switching section input unit will generate two interruptions.

Therefore, an object of the present invention is to solve the above problems and prevent the second momentary interruption in the momentary interruption switching section input section when the switching operation is performed outside the momentary interruption switching section. Therefore, it is an object of the present invention to provide a phase adjustment circuit of a hitless switching system capable of improving transmission quality and maintainability.

[0028]

A phase adjustment circuit of a hitless switching system according to the present invention adjusts a phase difference between signals transmitted through each of an active transmission line and a standby transmission line by using a memory. A phase adjustment circuit of an uninterruptible switching system for switching between the active system transmission line and the standby system transmission line without interruption, for the memory obtained by the adjustment of the phase difference performed at start-up. Storage means for storing a phase relationship between writing and reading and comparing the current phase relationship between writing and reading with respect to the memory with the phase relationship stored in the storage means before the readjustment of the phase difference is performed. A comparing means, a judging means for judging whether or not the phase difference needs to be readjusted according to a comparison result of the comparing means, and a means for carrying out the readjustment of the phase difference when the judging means judges that the readjustment is necessary. I have it.

A phase adjusting circuit of another hitless switching system according to the present invention adjusts the phase difference of signals transmitted through the active transmission path and the standby transmission path using a memory,
A phase adjustment circuit of a non-interruptible switching system that performs switching between the active transmission line and the standby transmission line without instantaneous interruption,
Storage means for storing the delay time obtained by the adjustment of the phase difference performed at the time of startup and from the time the signal is written to the memory until the signal is read; and the current means before execution of the readjustment of the phase difference. Comparing means for comparing the delay time with respect to the memory with the delay time stored in the storing means; judging means for judging whether the phase difference is readjusted or not according to the comparison result of the comparing means; And a means for readjusting the phase difference when the judging means judges that the phase difference is necessary.

[0030]

First, the operation of the present invention will be described below.

In the phase adjustment circuit of the present invention, after the phase adjustment is performed at the time of start-up, the phase relationship between the writing and the reading in the memory after the completion of the phase adjustment (the delay time from the writing of the signal in the memory to the reading). Is stored in the phase memory circuit at startup. The phase adjustment by the phase adjustment circuit is performed at the time of starting the device or when the transmission line construction changes and the delay time of the transmission line changes.

When it becomes necessary to perform the phase adjustment again when the frame synchronization circuits of both the active system and the standby system are out of synchronization, for example, after the frame synchronization is restored, the current memory is read before the phase adjustment is performed. The relationship between the write timing and the read timing from the memory is compared with the phase relationship stored in the startup phase memory circuit, and if the phase difference is within a certain range, the phase adjustment was completed previously. Therefore, the phase is not adjusted.

As a result, it becomes possible to prevent the second momentary interruption in the momentary interruption switching section input section when the switching operation is performed outside the momentary interruption switching section, and improve the transmission quality and maintainability. It becomes possible.

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. In the figure, a phase adjustment unit according to an embodiment of the present invention includes a frame synchronization circuit 1, a memory 2, a write counter (W ADDRCTR) 3, a read counter (RADDDR CTR) 4, a delay adjustment control circuit 5, The start-up phase storage circuit 6 is included.

The frame synchronization circuit 1 detects the frame pattern inserted on the transmission side, controls the write counter 3 using the detected frame pattern, and the write counter 3 sets the write address to the memory 2 (elastic store). To generate.

For example, the head of the frame is written in the head address (address 0) of the memory 2, and then the received signals are sequentially written in the memory 2. When the frame synchronization circuit 1 receives the signal at the beginning of the next frame, it starts writing the beginning of the frame from the beginning address of the memory 2 in the same manner as above.

The frame synchronization circuit 1 delays the synchronization detection signal indicating that the received signals are synchronized and the frame timing indicating that the phase information (frame pattern) is received for each frame as synchronization information. It outputs to the adjustment control circuit 5 and the delay adjustment control circuit (not shown) of another system, respectively.

The delay adjustment control circuit 5 compares the frame timing output from the frame synchronization circuit 1 of its own system with the frame timing output from the frame synchronization circuit (not shown) of the other system, and based on the comparison result. Then, the read counter 4 is controlled.

For example, the delay time difference between the receiving frame patterns of the active system and the standby system is obtained, and the reading is performed with a delay of a certain time from the write phase of the system that received the delay,
Control to prevent memory slip.

When the phase adjustment at the time of start-up is completed, the delay adjustment control circuit 5 has a phase relationship between the write timing to the memory 2 and the read timing from the memory 2 at that time (a signal is written in the memory 2 and then read). The delay time until output) is stored in the startup phase storage circuit 6. This processing operation is performed only once when the phase adjustment at startup is completed.

FIG. 2 is a timing chart showing the operation of one embodiment of the present invention. The processing operation of the embodiment of the present invention will be described with reference to FIGS. It should be noted that the hitless switching system according to the embodiment of the present invention has the same configuration as that of the conventional hitless switching system shown in FIG. 3, and the phase adjusters 21 and 22 in the hitless switching section are shown in FIG. It is assumed that each of the circuits shown in FIG. 5 is included, and the transmission signal is formed of each of the signals shown in FIG.

When the signals of the two systems of the active system and the standby system are received from outside the non-instantaneous interruption switching section, the phase information adding unit is added to each of the signals received by the interface units 11 and 12. At 13 and 14, phase information for delay time adjustment of non-instantaneous interruption switching is added.

Here, the phase information added by the phase information adding sections 13 and 14 is generally a frame pattern having a cycle sufficiently longer than the difference in transmission line delay time between the active system and the standby system in the non-instantaneous interruption switching section. Is used and this frame pattern is inserted by utilizing the unused bit portion in the data signal.

In other words, the transmission path length is not always the same in the active system and the standby system, and the delay times in the interface units 11 and 12 have some variations, so that the active system signal and the standby system signal are different. Even if the transmitted information is the same, it does not always arrive at exactly the same time.

In general, the transmitted signal, in addition to the information signal I,
Various management information such as a frame synchronization byte F for separating the information signal I and various management information and an unused spare byte R are time-division multiplexed in the receiving section.

In the non-instantaneous-interruption switching method, a part of the management information (spare byte R) is used to transmit a frame pattern P as phase information, and the receiving unit receives this frame pattern P.
Phase adjustment is performed based on The frame sync byte F
The spare byte R and the frame pattern P have a size of 1 byte.

The active phase information adding section 13 and the standby phase information adding section 14 receive the same signal, but there is some time lag. In the receiving section, the phase adjustment sections 21 and 22 synchronize the frames by using the phase adjustment frame patterns P inserted on the transmission side, respectively, and the delay time difference generated due to the difference in the transmission path length or the like is used for the phase adjustment sections 21 and 22. It is absorbed by the internal memory, and signals having the same phases in the active system and the standby system are sent to the selection units 23 and 24.

The signals to which the phase information is added by the phase information adding units 13 and 14 are selected by the selecting units 15 and 16, and then the active system transmission of the non-interruption switching section is performed by the interface units 17 and 18. And the protection transmission line. The selection units 15 and 16 are units that perform redundant system switching of transmission lines outside the non-interruption switching section, and the selection units 15 and 16 are controlled so as to always select the same system.

That is, the selection units 15 and 16 belong to both the non-instantaneous-interruption switching section and the non-instantaneous-interruption switching section, and the switching sections partially overlap at the boundary section (selection sections 15 and 16). , Which constitutes a seamless redundant system. Note that the selection units 23 and 24 also belong to both the non-instantaneous-interruption switching section and the non-instantaneous-interruption switching section, like the selection units 15 and 16.

As a result, in the non-instantaneous interruption switching section, the signal to which the same phase information is added is always sent to both the working transmission path and the protection transmission path.

In the receiving section for the signals transmitted through the active transmission path and the standby transmission path in the non-instantaneous interruption switching section, the interface sections 19 and 20 receive the signals from the active transmission path and the standby transmission path, respectively. Then, the signals are sent to the phase adjusters 21 and 22, respectively.

The phase adjusters 21 and 22 align the signal phases of the working transmission path and the protection transmission path by using the phase information inserted on the transmitting side. The frame synchronization circuit 1 of the phase adjusters 21 and 22 detects the frame pattern inserted on the transmission side and uses the detected frame pattern to write the counter 3
The write counter 3 generates a write address for the memory 2.

For example, the head of the frame is written in the head address (address 0) of the memory 2, and then the received signals are sequentially written in the memory 2. When the frame synchronization circuit 1 receives the signal at the beginning of the next frame, it starts writing the beginning of the frame from the beginning address of the memory 2 in the same manner as above.

Further, the frame synchronization circuit 1 uses the synchronization detection signal indicating that the received signals are synchronized and the frame timing indicating that the phase information is received for each frame as synchronization information, and the delay adjustment control circuit 5 And the delay adjustment control circuit of another system.

The delay adjustment control circuit 5 compares the frame timing output from the frame synchronization circuit 1 of its own system with the frame timing output from the frame synchronization circuit of the other system, and based on the comparison result, the read counter 4 is set. Control.

For example, the delay time difference between the receiving frame patterns of the active system and the standby system is obtained, and the reading is performed with a delay of a certain time from the writing phase of the system that received the delay,
Control to prevent memory slip.

When the phase adjustment at startup is completed, the delay adjustment control circuit 5 stores the phase relationship between the write timing to the memory 2 and the read timing from the memory 2 at that time in the startup phase storage circuit 6. This processing operation is performed only once when the phase adjustment at startup is completed.

By the above operation, the same signal is output in the same phase from the active phase adjuster 21 and the standby phase adjuster 22. Therefore, even if the selectors 23 and 24 switch between the active system and the standby system, no instantaneous interruption of signals occurs at the outputs of the interface units 25 and 26.

Normally, the clocks on the transmitting side and the receiving side are synchronized, so if the control of the read counter 4 is performed once when the apparatus is started, the read signal is read even if the received signal is temporarily cut off due to a transmission line failure or the like. By continuously operating the counter 4, when the failure is recovered, the phase relationship of writing and reading of the memory 2 is restored to the initially set phase relationship.

When the failure occurs only in one of the active system and the standby system, the delay adjustment control circuit 5 of the system receiving the normal signal of either one writes it to the memory 2 at the frame timing. And the timing of reading can be monitored. Therefore, it is not necessary to adjust the phase when the failure is recovered.

When a failure occurs in both the active system and the standby system at the same time, the phase relations of writing and reading to and from the memory 2 are such that the phase adjusting units 21 of both the active system and the standby system.
If it becomes unclear in 22, it is necessary to perform the phase adjustment at the time of restoration of the failure. However, before performing the phase adjustment, the delay adjustment control circuit 5 writes the current timing to the memory 2 and The phase relationship with the read timing of is compared with the phase relationship stored in the startup phase memory circuit 6. In this comparison, the read counter 4 is controlled to execute the phase adjustment only when the difference between the phase relationships exceeds the preset criterion.

On the other hand, when the difference between the phase relationships does not exceed the preset criterion, it is judged that the re-phase adjustment is unnecessary and the phase adjustment is not executed. In this case, if the judgment reference is set in advance so that the re-phase adjustment is not necessary for the phase difference of the delay time difference of the input sections of the interface sections 19 and 20, the phase generated by the switching in the selection sections 15 and 16 is set. In the fluctuation of 1, the rephase adjustment is not executed, and the instantaneous interruption occurs only once (see FIG. 2).

As described above, the phase difference between the signals transmitted through the active transmission path and the standby transmission path is adjusted by using the memory 2 so that the active transmission path and the standby transmission path are not switched. In the non-instantaneous-interruption switching system performed by instantaneous interruption, the phase relationship between writing and reading with respect to the memory 2 obtained by the adjustment of the phase difference performed at the time of starting is stored in the starting-time phase storage circuit 6, and at the time of recovery from the failure Before the readjustment of the phase difference is performed, the delay adjustment control circuit 5 compares the current phase relation between writing and reading with respect to the memory 2 with the phase relation stored in the startup phase storage circuit 6, and the comparison result. By determining whether or not the phase difference needs to be readjusted according to the above, if the difference in the phase relationship is within the criterion, the phase difference is not readjusted, so the switching operation is performed outside the non-interruption switching section. Non-interruption switching section when performed It is possible to prevent the second interruption in the force unit. Therefore, transmission quality and maintainability can be improved.

[0064]

As described above, according to the present invention, the phase difference between the signals transmitted through each of the active transmission line and the standby transmission line is adjusted by using a memory, and the active transmission line and the standby transmission line are adjusted. In an uninterruptible switching system that switches to the system transmission line without interruption, the phase relationship between writing and reading to and from the memory, which was obtained by adjusting the phase difference at startup, is stored and the phase difference is restored. Before the adjustment is performed, it is possible to determine whether or not the phase difference needs to be readjusted according to the result of comparison between the current writing and reading phase relations to the memory and the stored phase relation. It is possible to prevent the second momentary interruption in the non-instantaneous interruption switching section input unit when the switching operation is performed outside the switching section, and it is possible to improve the transmission quality and maintainability.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional hitless switching system.

FIG. 4 is a block diagram showing a configuration of a conventional phase adjustment unit.

5A is a diagram showing an input signal example of the phase information adding unit of FIG. 3, and FIG. 5A is a diagram showing an output signal example of the phase information adding unit of FIG.

FIG. 6 is a timing chart showing an operation of a conventional example.

[Explanation of symbols]

 1 frame synchronization circuit 2 memory 3 write counter 4 read counter 5 delay adjustment control circuit 6 phase memory circuit at startup

Claims (4)

[Claims] 1. A phase difference between signals transmitted through each of the working transmission path and the protection transmission path is adjusted using a memory,
A phase adjustment circuit of a non-interruptible switching system that performs switching between the active transmission line and the standby transmission line without instantaneous interruption,
Storage means for storing the phase relationship between writing and reading with respect to the memory obtained by the adjustment of the phase difference performed at the time of startup; and writing and reading with respect to the current memory before execution of the readjustment of the phase difference. Comparing means for comparing the phase relationship with the phase relationship stored in the storage means, judging means for judging necessity / unnecessity of readjustment of the phase difference according to the comparison result of the comparing means, and the judging means. And a means for performing readjustment of the phase difference when it is determined to be necessary. 2. The judging means judges that the readjustment of the phase difference is unnecessary when it is detected by the comparison by the comparing means that the difference between the phase relationships is within a predetermined range set in advance, and 2. The constitution according to claim 1, wherein when the comparison by the comparison means detects that the difference between the phase relationships exceeds a preset predetermined range, it is determined that the readjustment of the phase difference is necessary. Phase adjustment circuit. 3. A memory is used to adjust the phase difference between signals transmitted through each of the working transmission path and the protection transmission path,
A phase adjustment circuit of a non-interruptible switching system that performs switching between the active transmission line and the standby transmission line without instantaneous interruption,
Storage means for storing the delay time obtained by the adjustment of the phase difference performed at the time of startup and from the time the signal is written to the memory until the signal is read; and the current means before execution of the readjustment of the phase difference. Comparing means for comparing the delay time with respect to the memory with the delay time stored in the storing means; judging means for judging whether the phase difference is readjusted or not according to the comparison result of the comparing means; A phase adjusting circuit having means for readjusting the phase difference when the judging means judges that it is necessary. 4. The determination means determines that the readjustment of the phase difference is unnecessary when the comparison by the comparison means detects that the difference between the delay times is within a preset predetermined range, and 4. The structure according to claim 3, wherein when the comparison by the comparison means detects that the difference between the delay times exceeds a preset predetermined range, it is determined that the phase difference needs to be readjusted. Phase adjustment circuit.