JP2997643B2 - Dual processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a duplex processing apparatus for performing duplex switching in a duplex transmission path of an ATM network.

[0002]

2. Description of the Related Art ATM (Asynchronous T)
In a duplex transmission path of a transfer mode (transfer mode) network, it is required to switch without any instantaneous interruption when duplex switching is performed. In order to respond to such a request, for example, a method described in IEICE Technical Report CS92-48 in 1992 and CS88-55 in 1988 has been proposed. These methods will be described below as conventional examples.

In order to realize the duplex switching in the conventional system, it is necessary to establish synchronization between the active cell flow and the standby cell flow, maintain the synchronization, and reliably detect the loss of synchronization. Is required. FIG. 1 is a system configuration diagram showing the configuration of the entire system including a conventional duplex switching device. In FIG. 1, reference numeral 11 denotes an opposite device that performs transmission or reception, 12 denotes a receiving device that receives a signal from the opposite device 11, and 121 denotes an SDH (Sy) provided in the receiving device 12.
nchronous Digital Hierarc
hy) The processing unit 122 is a conventional duplex switching device provided in the receiving device 12 and at a stage subsequent to the SDH processing unit 121. The SDH processing unit 121 is the active SDH processing unit 1
21a and a standby SDH processing unit 121b. Reference numeral 101 denotes a working SDH frame transmitted from the opposing device 11 to the receiving device 12; 102, a standby SDH frame transmitted from the opposing device 11 to the receiving device 12;
Reference numeral 3 denotes a duplex switching device 1 from the active SDH processing unit 121a.
The active cell flow sent to 22, 104 is the standby cell flow sent from the standby SDH processing unit 121 b to the duplex switching device 122, 105 is the output cell flow after switching output from the duplex switching device 122 It is.

[0004] FIG. 24 shows a conventional system shown in FIG.
FIG. 2 is a configuration diagram showing a configuration of a DH processing unit 121. FIG.
1, the same reference numerals as those in FIG. 1 denote the same or corresponding parts.
Reference numeral 2401a denotes an active SDH / cell conversion circuit for creating a cell flow from an active SDH frame, and 2401b denotes a standby SH.
A standby SDH / cell conversion circuit that creates a cell flow from a DH frame, 2402a is an active buffer that stores the active cell flow, 2402b is a standby buffer that stores the standby cell flow, and 2403a is a speed controller for the active system. An idle cell insertion circuit 2403b is a standby speed adjustment idle cell insertion circuit for the standby system.

FIG. 25 is a configuration diagram showing the configuration of the conventional duplex switching device shown in FIG. 1 or FIG.
25, the same symbols as those in FIG. 1 indicate the same or corresponding parts. Reference numeral 2501 denotes a phase measuring circuit for measuring a phase difference (delay difference) between the active cell flow and the standby cell flow, 2502a denotes a variable delay circuit for delaying the active cell flow, and 2502b denotes a variable delay circuit for delaying the standby cell flow. , 2503 is a working / standby selection circuit for selecting either the working cell flow or the protection cell flow, and 2504 is a phase measurement circuit 2501, variable delay circuits 2502a and 250b, and a working / standby selection circuit 2.
503 is a control unit for controlling the 503.

FIG. 26 is a flowchart showing the operation of the conventional duplex switching device shown in FIG.

Next, the operation of the conventional duplex switching device will be described with reference to FIG. 1 and FIGS. First, from the opposing device 11 shown in FIG. 1, an active SDH frame 1 composed of an overhead section and payload information containing cell information.
01 is transmitted and input to the working SDH processing unit 121a. Also, a standby SDH frame 102 containing an overhead section and cell information and including payload information is transmitted from the opposing apparatus 11 shown in FIG. 1 and input to the standby SDH processing section 121b. In the SDH processing unit 121a,
The working SDH / cell conversion circuit 2401a is the working SDH
The payload information of the frame is taken out on a cell-by-cell basis to create a working cell flow, and the standby SDH / cell conversion circuit 240
1b takes out the payload information of the standby SDH frame in cell units and creates a standby cell flow. Also, SDH
In order to absorb the synchronization deviation between the SDH frame and the cell flow generated when the cell flow is created from the frame, the active cell flow extracted from the payload information is used as the active buffer 24.
At 02a, the spare cell flow is temporarily stored in the spare buffer 2402b.

In this case, the transmission rate of the cell input to the duplex switching device 122 is slightly higher than the transmission rate of the payload information excluding the overhead information of the input SDH frame (however, the rate error is Since the writing speed to the buffer 2402 cannot keep up with the reading speed from the buffer 2402,
402 underflow may occur. Therefore, each time a cell is received, the above-mentioned speed error is accumulated, and when the accumulated speed error reaches one cell, the buffer 24
After stopping reading from the cell stream 02, the rate adjusting idle cell insertion circuit 2403 inserts one rate adjusting idle cell into the cell stream in order to adjust the transmission rate.

As a result, underflow in the buffer 2402 can be prevented. Next, the current cell flow 103 into which the speed adjustment idle cells are inserted.
And the standby cell flow 104 are input to the duplex switching device 122. In the duplex switching device 122, these cell flows 10
3 and 104 are input to the phase measurement circuit 2501 shown in FIG.

In FIG. 25, a phase measuring circuit 2501 detects a phase difference between the active cell flow 103 and the standby cell flow 104. This phase difference is nd. Next, in order to prevent erroneous synchronization due to a coincident cell, the phase measurement circuit 2501 repeats a predetermined number of times (L) at the same interval as the measured phase difference nd (ie, every nd cell) as shown in FIG. -1) times) and continuously compare cells (step S2601), and determine the result of the comparison (step S26).
02) and (L-1) times when the comparison results match, it is considered that synchronization has been established with the phase difference nd between the active cell flow and the standby cell flow, and the control unit 2504 is notified of the value nd. I do. If the comparison result does not match even at least one of the (L-1) consecutive times, the process returns to step S2601 to start over again from the phase difference detection between the active cell flow 103 and the standby cell flow 104. The above operation is a synchronous search process. Note that invalid cells (idle cells) that do not include user information are not compared.

After the phase difference nd between the working cell flow and the protection cell flow has been established in the synchronization search process, if the working cell flow 103 is ahead of the protection cell flow 104 by nd cells, the variable delay The circuit 2502a inserts a delay (for example, an idle cell) according to a command from the control unit 2504, and conversely, the standby cell flow 104 is nd from the working cell flow 103.
If the phase is advanced by the cell, the variable delay circuit 250
2b inserts nd delays at the head of the cell stream.

Next, the working cell flow and the backup cell flow synchronized in this way are compared a predetermined number of times (M times) (step S2603). As a result of comparing the synchronized active cell flow and the standby cell flow, it is determined whether the cells match M times consecutively (step S2604). This is performed to prevent erroneous synchronization due to a coincident cell. If the comparison result matches M times consecutively, it is considered that synchronization has been established. If there is a case where even one of the M consecutive times does not match, the process returns to step S2601 and starts again from the phase difference detection between the active cell flow 103 and the standby cell flow 104. The above operation is a synchronization confirmation process. Note that invalid cells are not compared.

Next, even after the synchronization between the active cell flow and the standby cell flow is established, the current cell flow and the standby cell flow are compared in order to find out that the synchronization is not lost (step). S2605). As a result of comparing the synchronized active cell flow and the standby cell flow, it is determined whether or not a mismatch occurs continuously a predetermined number of times (N times) (step S260).
6). This is performed in order to prevent erroneous synchronization from being lost due to a cell that is accidentally mismatched due to a bit error or the like. in this case,
If N times of non-coincidence occur consecutively, it is regarded as out of synchronization, and the process returns to step S2601 to start again from the phase difference detection between the active cell flow 103 and the standby cell flow 104. If there is a case in which both cells match at least once among N consecutive times, it is determined that the cells are only temporarily inconsistent due to a bit error or the like, and that synchronization is still maintained. Note that invalid cells are not compared.

Next, when a switching instruction signal is externally output from the control unit 2504 to the active / standby selecting circuit 2503 in a state where the synchronization is established,
The standby system selection circuit 2503 switches the active system cell flow to the standby system cell flow. At the time of this switching, cell loss and cell duplication do not occur in the active system, and instantaneous interruption switching is realized.

[0015]

The conventional duplex switching device is constructed as described above. In order to absorb the phase difference between the working cell flow and the protection cell flow generated on the transmission path,
Since the same idle cell as the idle cell sent from the opposite device is used, and the variable delay circuit performs deletion / insertion without distinguishing between the idle cell from the opposite device and the idle cell for absorbing the phase difference, There is a problem that valid cells are likely to appear continuously in the cell stream output from the variable delay circuit, and in the process of processing the valid cells, an overflow may occur in a subsequent circuit and the processing may become impossible. There was a point.

In addition, since the current system cell flow and the standby system cell flow are input as they are, if the transmission line cell flow becomes faster, the processing time becomes severe. Further, when a plurality of transmission line cell flows exist, there is a problem in that a duplex switching device is required for each of the transmission line cell flows, so that the number of devices becomes enormous.

Further, when cells are transmitted using the payload information of the SDH transmission frame, the working cell flow and the protection cell flow operate independently of each other.
The phase measurement circuit 21 detects that the insertion position of the idle cell for speed adjustment inserted to adjust the transmission speed of the payload information and the transmission speed of the generated cell is asynchronous between the active system and the standby system. There is a problem that the phase difference is different from the phase difference of the processing in the variable delay circuit, and normal operation cannot be guaranteed.

For example, as shown in FIG. 27, the structure of a cell flow in which idle cells for speed adjustment are inserted is a cell flow 2701.
Assuming that the current cell flow is one cell ahead of the backup cell flow, the phase difference detected by the phase measurement circuit is one cell. However, this cell flow 2701 has not yet established synchronization after “cell C”. Therefore,
In order to establish synchronization, the variable delay circuit places one idle cell for speed adjustment between “cell C” and “cell D” of the active system.
Even if a cell is inserted to create a cell stream 2702, synchronization of the cell stream after “cell D” cannot be established yet. Therefore, in order to establish synchronization, the variable delay circuit further includes “cell D”
Even if one cell for speed adjustment is inserted between the cell flow and the "cell E" to create the cell flow 2703, synchronization of the cell flow after "cell G" cannot be established yet. As described above, in order to establish synchronization, the variable delay circuit repeatedly inserts the idle cells for speed adjustment many times, and depending on the configuration of the cell flow, there is a problem that synchronization may not be established forever. there were.

SUMMARY OF THE INVENTION The present invention has been made to solve these problems, and it is an object of the present invention to provide a small-scale dual processing device capable of processing a transmission line cell flow regardless of whether the flow speed is high or low. With the goal.

Further, even when the phases of the speed adjusting cells inserted into the active system and the standby system are asynchronous, processing such as phase search for the active system cell flow and the standby system cell flow, absorption of the phase difference, establishment of synchronization, etc. It is an object of the present invention to obtain a duplex processing device that can operate normally. This will be described below. Fig. 2
As shown in FIG. 8, the same cell flow 2801 as the cell flow 2701 is used.
In this case, the cell flow 2802 is created by adjusting the position of the speed adjustment cell of the non-reference system (here, the standby system) to the reference system (here, the current system) before inserting the delay, If the phase measuring circuit does not count the cells for speed adjustment, the phase difference of the phase measuring circuit becomes one cell, and the variable delay adjusting circuit also inserts a one-cell delay to establish synchronization between the working system and the standby system. it can. It is an object to obtain such a duplex processing apparatus.

[0021]

When a duplex processing apparatus according to the first invention receives the same duplicated SDH frame from an opposite apparatus, the duplex processing apparatus converts bayload information excluding an overhead portion of the SDH transmission frame into a cell. An SDH processing unit that takes out the unit and generates the same active system and standby system cell flows, searches for the phase difference between the active system and the standby system cell flows, synchronizes the phases, and then performs cell omission and cell duplication. And a switching device that switches from the working system to the standby system without an instantaneous interruption without causing the like, and the like. Cell flow division control means for dividing and outputting a low-speed cell flow, or transmitting a plurality of low-speed transmission cell flows without dividing and outputting the transmission flow as it is;
A cell flow selection circuit is provided corresponding to the number of cell flows output from the division control means, and selects one cell flow from a plurality of cell flows output from the division control means; By comparing the cell flows of the working system and the protection system, the phase difference between the two systems is searched for, the phase difference is absorbed and synchronization is established, and then the transmission path is changed to the working system. A switching circuit that switches from instantaneously to standby for standby,
When the input transmission line cell flow is high-speed, the cell flow output by the switching circuit is multiplexed and output again.When a plurality of low-speed transmission line cell flows are input, a plurality of input cell flows are output. Multiplexing control means for returning to the original cell sequence by transmitting and outputting as it is, a plurality of the cell flow selection circuits and the switching circuits are controlled by control signals so as to cooperate with each other, and the cell The flow selection circuit selects a different current cell flow in advance, and when searching for a phase difference with the standby cell flow, if the current cell flow and the standby cell flow do not match, the cell flow selection circuit The selection system of the backup cell flow is changed, the comparison is performed again, and the change of the selection system is repeated until a phase difference is searched. The section divided by the division control means After confirming that the values of the selection system of the backup cell flow do not overlap between the cell flow selection circuits provided for each flow and that they are in the same series as the working cell flow, a plurality of The cooperative operation of the switching circuit absorbs the searched phase difference, synchronizes the phases, establishes the synchronization, and switches the transmission line system from the working system to the standby system.

[0022]

Also, in the duplex processing apparatus according to the second invention, the SDH processing section comprises: a speed of the payload information generated when a cell stream is generated from the SDH transmission frame; Is superimposed with a phase shift from the cell speed input to the SDH transmission frame, and the overhead portion of the received SDH transmission frame inserts a speed adjusting cell when the phase shift reaches a predetermined number of cells. The switching circuit includes a speed adjusting cell detecting means for detecting the speed adjusting cell; a means for clearly identifying the speed adjusting cell and the idle cell; And delay inserting means for inserting a delay into the system in which the phase is advanced by using the speed adjusting cell.

Further, in the duplex processing apparatus according to the third invention, the SDH processing section includes: a speed of the payload information generated when a cell stream is generated from the SDH transmission frame; The shift of the phase with the cell speed to be performed is superimposed, and the overhead portion of the received SDH transmission frame causes the speed shift to be performed when the phase shift reaches a predetermined number of cells. A speed adjusting cell detecting means for detecting a speed adjusting cell; a means for clearly identifying a speed adjusting cell and an idle cell; and a phase shifter in a working system and a standby system. And a delay removing means for removing a delay from a system having a delay by using a speed adjusting cell or by using a speed adjusting cell and an idle cell.

[0025]

Further, the dual processing apparatus according to the fourth invention, when switching from the active system to the standby system, selects the cell flow of the standby system even when synchronization between the active system and the standby system is not established. There is provided a cell flow selecting means for adjusting the value of the cell flow sequence selected by the circuit to the same value as the value of the cell flow sequence selected by the active cell flow selection circuit.

Further, in the duplex processing apparatus according to the fifth invention, when the division control means performs processing by dividing the transmission path cell stream into a plurality of cells, the SDH processing section sets the overhead area of the received transmission frame to: When the number of cells corresponding to the number of switching circuits has been reached, a speed adjusting cell insertion circuit for continuously inserting speed adjusting cells for the number of switching circuits is provided.

Further, the duplex processing apparatus according to the sixth invention, when receiving the same duplicated SDH frame from the opposite apparatus, extracts the bayload information excluding the overhead part of the SDH transmission frame in units of cells. An SDH processing unit that generates the same active and standby cell flows, and when creating a cell flow from the bay load information, superimposes the difference between the speed of the bay load information and the speed of the generated cell. when the deviation reaches a predetermined number of cells, the rate adjusting cell Le insertion means for inserting the rate adjusting cells to the cell flow of both systems,
A variable delay circuit that establishes synchronization by absorbing the phase difference between the working cell flow and the protection cell flow by the speed adjustment cell, and the cell fluctuations that occur when the phase search for the working system and the protection system is performed separately from the variable delay circuit A phase measurement circuit that searches in advance for a phase difference to be absorbed by the variable delay circuit in order to suppress the switching, and a duplexing switching device that switches from the working system to the standby system without an instantaneous interruption without causing cell overlap or the like. The duplexing switching device comprises a speed adjusting cell detecting means for detecting a speed adjusting cell, a means for clearly identifying a speed adjusting cell and an idle cell, and one of an active system and a standby system. A speed adjusting cell inserted in the reference system as a reference system, and a speed adjusting cell displacement absorbing means for adjusting the position of the speed adjusting cell of the other system. The cell shift absorbing means is The system for matching the position is provided with a memory for holding the cell when matching, and when the speed adjusting cell detecting means detects the speed adjusting cell in the reference system, the other system which does not become the reference is used. Without reading from the memory, insert the speed adjustment cell into the non-reference system according to the position of the speed adjustment cell in the reference system, and detect cells other than the speed adjustment cell in the reference system In this case, reading from the memory is performed, and if a speed adjustment cell is detected in a non-reference system, the speed adjustment cell is not written in the memory, and a non-reference system other than the speed adjustment cell is used. When a cell is inserted, a control means for writing data to the memory is provided.

Further, in the duplexing apparatus according to the seventh invention, the speed control cell control means may include a speed control cell inserted into a non-reference system having an abnormally high frequency and a reference system. When the frequency of the speed adjustment cells inserted into the memory is abnormally low, conversion control means for converting the speed adjustment cells of the non-reference system into idle cells, and write control for writing the converted idle cells to the memory. Means.

In the duplexing apparatus according to an eighth aspect of the present invention, the speed control cell control means may include a system in which the frequency of the speed control cell inserted into the reference system is abnormally high and is not used as the reference. Read control means for reading from the memory when the frequency of the speed adjustment cells inserted into the memory is abnormally low, and conversion control means for converting the speed adjustment cells inserted into the reference system into idle cells. It is provided with.

[0031]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. FIG. 1 is a system configuration diagram showing a configuration of an entire system including a duplex switching device according to the present invention.
In FIG. 1, reference numeral 11 denotes an opposite device that performs transmission or reception,
12 is a receiving device for receiving a signal from the opposing device 11;
Reference numeral 1 denotes an SDH processing unit provided in the receiving device 12, and reference numeral 122 denotes a duplex switching device according to the present invention provided in the receiving device 12 and at a stage subsequent to the SDH processing unit 121. In addition,
The SDH processing unit 121 includes a working SDH processing unit 121a and a standby SDH processing unit 121b. Also, 1
01 is an active SDH frame sent from the opposing device 11 to the receiving device 12, and 102 is a working SDH frame from the opposing device 11 to the receiving device 1.
2 is a standby SDH frame sent to 2;
The working cell flow sent from the DH processing unit 121a to the duplexing switching device 122, 104 is the standby SDH processing unit 121b
Cell flow sent to the duplexing switching device 122 from the
05 is an output cell flow after switching output from the duplex switching device 122.

FIG. 2 is a configuration diagram showing the configuration of the SDH processing unit 121 when the transmission speed is 600 Mbps.
2, the same reference numerals as those in FIG. 1 denote the same or corresponding parts. Reference numeral 21a denotes an SDH / cell conversion circuit for extracting the payload information of the active SDH frame in units of cells, 21b denotes an SDH / cell conversion circuit for extracting the payload information of the standby SDH frame in units of cells, and 22a stores the cell flow of the active system. A buffer 22b for storing a standby cell stream; and 23a an active system speed adjusting cell insertion circuit for continuously inserting four cells for speed adjustment in order to adjust the transmission rate of the active system cell stream. Reference numeral 23b denotes a standby system speed adjusting cell insertion circuit for continuously inserting four cells for adjusting the transmission speed of the standby system cell stream.

FIG. 3 is a block diagram showing an embodiment of the duplex switching device according to the present invention. In FIG.
1 denote the same or corresponding parts. A high-speed (600 Mbps) active cell flow 103 arriving from a preceding active SDH processing unit 121 a (not shown) is input to the low-speed (150 Mbps) active cell flow 106 to 31.
9 and outputs the data to the standby SDH processing unit 12.
A DMUX circuit that inputs the high-speed (600 Mbps) backup cell stream 104 arriving from 1b, divides it into low-speed (150 Mbps) backup cell streams 110 to 113, and outputs
32a to 32d are switching control units.

A cell flow selection circuit 33a is provided in the switching control section 32a, selects one of the divided working cell streams 106 to 109 and outputs 132, and 33b is a switching cell control section 32a. One of the provided and divided standby cell streams 110 to 113 is selected and the standby cell stream 13 is selected.
3 is a cell flow selection circuit that outputs 3;
b, the divided active cell streams 106 to 109
A cell flow selection circuit 33d for selecting one of the cell flows and outputting 134 is provided in the switching control unit 32b, and selects one of the divided standby cell flows 110 to 113 to generate a standby cell flow. The cell flow selection circuit 33e that outputs the flow 135 is provided in the switching control unit 32c, and the divided active cell flow 1
A cell flow selection circuit 33f that selects one of the cells 06 to 109 and outputs 136 is provided in the switching control unit 32c.
A cell flow selection circuit that selects one of the divided standby cell flows 110 to 113 and outputs a standby cell flow 137;
33g is provided in the switching control unit 32d, selects one of the divided working cell flows 106 to 109 and outputs 138, and 33h is provided in the switching control unit 32d and provided with the switching control unit 32d. A cell flow selection circuit that selects one of the standby cell flows 110 to 113 and outputs the standby cell flow 139.

A switching circuit 34a is provided in the switching control unit 32a, and switches from the working cell flow 132 to the standby cell flow 133 according to an external switching command signal 118 after cell synchronization is established, and outputs a cell flow 141. A switching circuit 34b is provided in the switching control unit 32b, switches from the active cell flow 134 to the standby cell flow 135 according to an external switching command signal 118 after cell synchronization is established, and outputs a cell flow 142. 34c is a switching control unit. A switching circuit for switching from the active cell flow 136 to the standby cell flow 137 in accordance with an external switching command signal 118 after cell synchronization is established, and outputting a cell flow 143; a switching control unit 32d provided for the switching control unit 32d; After the cell synchronization is established, the active cell flow 138 is switched to the standby cell flow 139 in accordance with the external switching command signal 118. Instead, a switching circuit for outputting a cell stream 144.

A MUX 35 multiplexes the switched cell streams 141 to 144 output from the switching circuits 34a to 34d and outputs an output cell stream 105.

The active cell streams 106, 107, 108, and 109 are divided by the DMUX circuit 31 on the basis of the active cell stream 103, 110, 111, 112, 1
Reference numeral 13 denotes a standby cell flow divided by the DMUX circuit 31 based on the active cell flow 104, 114 to 117 control signals, 118 an external switching command signal, and 132 to 139.
Are output signals of the cell flow selection circuits 23a to 23h, 141 to 14
4 is an output signal from the switching circuits 34a to 34d.

FIG. 4 is a cell transition diagram showing a transition state of a cell flow handled by the DMUX 31 and the MUX 35 shown in FIG. In FIG. 4, reference numeral 421 denotes a cell flow of 600 Mbps, and the cell flow 103 or 104 or 10 shown in FIG.
5 corresponds to FIG. 422 is 600 bps
FIG. 3 shows a 150 Mbps cell flow obtained by dividing the cell flow into four parts.
Correspond to the cell flows 106 to 109 or 110 to 113 shown in FIG. Also, 401a, b, 402a,
b, 403a, b, 404a, b, 405a, b, 40
6a, b, 407a, b, 408a, b, 409a,
Reference numerals b, 410a, b, 411a, and 412a denote cells other than the speed adjusting cells, and 413a to h denote speed adjusting cells.

FIG. 5 shows the switching circuit 34a shown in FIG.
FIG. 2 is a configuration diagram showing the configuration of FIG. The configurations of the switching circuits 34b, c, and d are the same. In FIG. 5, reference numeral 51 denotes the phase of the speed adjustment cell inserted into the active cell stream 132 by the SDH processing unit 121a, the phase of the speed adjustment cell inserted into the standby cell stream 133 by the SDH processing unit 121b, The cell offset absorbing circuit for speed adjustment which outputs the standby system cell stream 151, the phase measurement circuit 52 for measuring the phase difference (delay difference) between the active system cell stream 132 and the standby system cell stream 151, and 53a is the active system flow Cell flow 132 (of valid cells)
A variable delay circuit that inserts a speed adjusting cell into the working cell stream and outputs the working cell stream 152 in order to match the phase when the phase is ahead of the (active cell) phase of the standby cell stream 151. , 53b insert a speed adjustment cell into the standby cell stream 151 when the phase (of the active cell) of the standby cell stream 151 is ahead of the phase (of the active cell) of the working cell stream 132. A variable delay circuit that outputs the system cell stream 153 and the active cell stream 152 and the standby cell stream 15
3, a working / standby system selection circuit 55 for selecting any one of the three and outputting the output cell stream 141; 55, a phase measuring circuit 52, variable delay circuits 53a, 53b, and a working / standby system selection circuit 5;
4 is a control unit for controlling the control unit 4. Reference numeral 119 denotes a switching command signal output from the control unit 55 based on a switching command signal from the outside.

FIG. 6 shows the switching circuit 34a in FIG.
FIG. 3 is a configuration diagram showing a configuration of a speed adjustment cell shift absorption circuit 51 shown in FIG. The same applies to the configuration of the speed adjustment cell shift absorbing circuit provided in each of the switching circuits 34b, c, and d. In FIG. 6, reference numeral 61 a denotes a speed adjustment cell detection unit that detects a speed adjustment cell included in the active system cell stream 132, and 61 b denotes a speed that detects a speed adjustment cell included in the standby system cell stream 133. Adjustment cell detector, 62 is a memory for storing the standby cell flow, 63 is a speed adjustment cell insertion for inserting a new speed adjustment cell into the standby cell flow in order to perform phase matching with the active cell flow. A circuit 64 is a control unit that controls the speed adjustment cell detection units 61a and 61b, the memory 62, and the speed adjustment cell insertion circuit 63. Note that the memory 62 is provided for two cells for preventing underflow and for two cells for preventing overflow.

FIG. 7 is an operation explanatory diagram showing a transition state of a cell flow in the configuration of the speed adjusting cell shown in FIG. 7, reference numerals 78a to 78h denote speed adjusting cells, 71a to d (cell A), 72a to d (cell B), 7
3a-d (cell C), 74a-d (cell D), 75a-
d (cell E), 76a to c (cell F), 77a to c (cell G), 79 (cell Y), and 70 (cell Z) are cells (valid cells and idle cells) other than the speed adjustment cell, 132
And 133 are the active cell flow and the standby cell flow before adjusting the phase of the speed adjustment cell, and 151 and 152 are the active cell flow and the standby cell flow after adjusting the phase of the speed adjustment cell. It is a flow. Note that the standby cell flow 152
The phase other than the cell for speed adjustment is delayed by two cells from the phase of the active system cell stream 151 because it is via the memory 42.

FIG. 8 is a diagram showing various cell configurations showing the configurations of a valid cell, an idle cell, and a speed adjusting cell.

FIG. 9 is a flowchart showing the operation of the duplex switching device shown in FIG.

Next, the operation of the duplex switching device according to the present invention will be described with reference to FIGS. First, an active SDH frame 101 including an overhead section and payload information containing cell information is transmitted from the opposing apparatus 11 shown in FIG.
Is transmitted to the active SDH processing unit 121a. Also, a backup SDH frame 102 containing the overhead information and the cell information and including the payload information is transmitted from the opposite device 11, and is input to the backup SDH processing unit 121b. In the SDH processing unit 121a, the active SDH /
The cell conversion circuit 2401a extracts the payload information of the active SDH frame on a cell-by-cell basis to create an active cell flow, and the standby SDH / cell conversion circuit 2401b outputs the standby SDH frame.
The payload information of the DH frame is taken out in cell units to create a standby cell flow. Further, in order to absorb the synchronization deviation between the SDH frame and the cell flow generated when the cell flow is created from the SDH frame, the working cell flow extracted from the payload information is stored in the working buffer 22a, and the backup cell flow is stored in the backup buffer. The data is temporarily stored in the system buffer 22b.

In this case, the transmission speed of the cell input to the duplex switching device 122 is slightly higher than the transmission speed of the payload information excluding the overhead information of the input SDH frame (however, the speed error is (Within one cell), the writing speed to the buffer 22 is
There is a possibility that the buffer 22 cannot catch up with the read speed from the buffer 2 and an underflow of the buffer 22 occurs. Therefore, each time a cell is received, the above-mentioned speed error is accumulated, and when the accumulated speed error reaches four cells, reading from the buffer 22 is stopped, and the speed adjusting cell insertion circuit 23 adjusts the transmission speed. For this purpose, four cells for speed adjustment are continuously inserted into the cell flow.

The reason why the cells for rate adjustment are inserted continuously for four cells instead of one cell is that the transmission rate is 600 Mbp.
In the case of s, the DMUX circuit 3
1 is divided into four cell flows, and the switching control units 32a shown in FIG.
Each cell operates for each of b, c, and d.
When only cells are inserted, the speed adjustment cell is input to one switching control unit, but the speed adjustment cell at that time is not input to the other three switching control units. for that reason,
This is because when the phases of the speed adjusting cells of the active system and the standby system are adjusted, the four switching control units do not operate in cooperation, and the order of the cells may be disordered. In order to avoid such a situation, four cells for speed adjustment are inserted continuously.

For example, as shown in the cell flow 421 of FIG.
.., CDEFGH speed-speed IJ...
1 (not shown) has four 150 Mbps cell streams # 1 "A
# 2 "BF speed J ..." and #
3 "CG speed K ..." and # 4 "DH speed L ..."
And the speed adjustment cells 413e, f, g, and h are inserted one by one into the same phase of each of the cell streams # 1 to # 4, and the four switching control units 32a, b, c, d cooperates to absorb the phase. Note that the above “A”, “B”,.
“L” means a cell other than the speed adjustment cell, and “speed” means a speed adjustment cell.

As a result, even in a duplex switching device in which a high-speed (600 Mbps) cell stream is divided into a plurality of low-speed (150 Mbps) cell streams and controlled, underflow can be prevented without disturbing the cell order. Can be prevented.

In the duplex switching device 122, the DM shown in FIG.
The UX circuit 31 inputs a cell flow in which the speed adjustment cells output from the SDH processing unit 121 and the valid cells including the idle cells transmitted from the opposing device 11 are mixed. Note that in the conventional example, the SDH processing unit 121
Since the phase shift between the active cell flow and the standby cell flow at the time of taking out the TM cell is absorbed by using the idle cell, the cell flow does not include the speed adjusting cell, and the duplex switching device 1
The cell flow input to 22 differs from the present invention in that it has a configuration in which only idle cells and valid cells are mixed.

The DMUX 31 receives the input working cell stream 10
3 to four 150 Mbps active cell streams 106 to 10
9 and the preliminary cell stream 104 is divided into four 150 Mbp
s of the standby system cell streams 110-113. In this case, the DMUX circuit 31 divides the input working cell stream 103 into the working cell streams 106 to 109 equally. The same applies to the standby cell flow.

For example, the first input cell 103 of the active system is input to 106, and the input cell 104 of the standby system is input to 110.
The next input cell 103 of the active system is output to 107, the input cell 104 of the standby system is output to 111, the next input cell 103 of the active system is output to 108, and the input cell 104 of the standby system is output to 112. Then, the next active input cell 103 is set to 109
, The input cell 104 of the standby system is output to 113, the input cell 103 of the next active system is output to 106, and the input cell 1 of the standby system is output.
04 to 110, the next active input cell 103 to 107, the standby input cell 104 to 111,
The next input cell 103 of the active system is output to 108, the input cell 104 of the standby system is output to 112, and the next input cell 1 of the active system is output.
03 is output to 109, the standby input cell 104 is output to 113, the next active input cell 103 is output to 106, the standby input cell 104 is output to 110, and so on. Output in minutes.

Next, the 150 Mbps active cell flows 106 to 109 divided by the DMUX circuit 31 are supplied to the cell flow selection circuit 33a and the switching control unit 32 of the switching control unit 32a.
b, the cell flow selection circuit 33e of the switching control unit 32c, and the cell flow selection circuit 33g of the switching control unit 32d. 33b, switching control unit 32
b, the cell flow selection circuit 33f of the switching control unit 32c, and the cell flow selection circuit 33h of the switching control unit 32d.

Next, in the switching control section 32a, the cell flow selection circuit 33a selects one of the active cell flows from the active cell flows 106 to 109, outputs the selected one as the active cell flow 132, and outputs the cell flow. The selection circuit 33b sets the standby cell flow 1
One standby cell flow is selected from 10 to 113 and output as the standby cell flow 133. Switching control unit 3
In 2b, the cell flow selection circuit 33c sets the active cell flow 106
To 109 are selected and output as the active cell flow 134, and the cell flow selection circuit 3
3d selects one standby cell flow from the standby cell flows 110 to 113 and outputs it as the standby cell flow 135. In the switching control unit 32c, the cell flow selection circuit 33
e selects one active cell flow from the active cell flows 106-109 and outputs it as the active cell flow 136, and the cell flow selection circuit 33f outputs the standby cell flow 110-1.
One of the standby system cell flows is selected from 13 and output as the standby system cell flow 137. In the switching control unit 32d, the cell flow selection circuit 33g outputs the active cell flow
9 and outputs it as the active cell flow 138, and the cell flow selection circuit 33h selects one standby cell flow from the standby cell flows 110-113. This is output as the standby cell flow 139. At this time, the active system cell flow selection circuits 33a, c, e, and g select the four active system cell flows 106 to 109 so as not to overlap each other. Further, the standby system cell flow selection circuits 33b, d, f,
h is also selected so that the four standby cell streams 110 to 113 do not overlap each other.

For example, for the active cell flow, the cell flow selection circuit 33a of the switching control unit 32a outputs the active cell flow 106
Is selected, the cell flow selection circuit 3 of the switching control unit 32b
3c selects the active cell flow 107, and selects the switching control unit 32c.
The cell flow selection circuit 33e selects the working cell flow 108, and the cell flow selection circuit 33g of the switching control unit 32d selects the working cell flow 109. When the cell flow selection circuit 33a of the switching control unit 32a selects the working cell flow 107, the cell flow selection circuit 33c of the switching control unit 32b selects the working cell flow 108 and the cell flow of the switching control unit 32c. The selection circuit 33e selects the current cell flow 109, and the cell flow selection circuit 33g of the switching control unit 32d selects the current cell flow 106. Further, the cell flow selection circuit 3 of the switching control unit 32a
When 3a selects the working cell flow 108, the cell flow selection circuit 33c of the switching control unit 32b selects the working cell flow 109, and the cell flow selection circuit 33e of the switching control unit 32c selects the working cell flow 106. Then, the cell flow selection circuit 33g of the switching control unit 32d selects the active cell flow 107. When the cell flow selection circuit 33a of the switching control unit 32a selects the working cell flow 109, the cell flow selection circuit 33c of the switching control unit 32b selects the working cell flow 106, and the cell flow of the switching control unit 32c. The selection circuit 33e outputs the current cell flow 1
07, and selects the cell flow selection circuit 33 of the switching control unit 32d.
g selects the working cell stream 108.

The same applies to the case of the standby system. That is, when the cell flow selection circuit 33b of the switching control unit 32a selects the standby cell flow 110, the cell flow selection circuit 33d of the switching control unit 32b selects the standby cell flow 111 and the cell flow of the switching control unit 32c. The selection circuit 33f selects the standby cell flow 112, and the cell flow selection circuit 33h of the switching control unit 32d selects the standby cell flow 113. Also, the switching control unit 32a
When the cell flow selection circuit 33b selects the standby cell flow 111, the cell flow selection circuit 33d of the switching control unit 32b selects the standby cell flow 112 and the cell flow selection circuit 33f of the switching control unit 32c selects the standby system flow. The cell flow 113 is selected, and the cell flow selection circuit 33h of the switching control unit 32d outputs the standby cell flow 11
Select 0. When the cell flow selection circuit 33b of the switching control unit 32a selects the standby cell flow 112, the cell flow selection circuit 33d of the switching control unit 32b outputs the standby cell flow 11
3 and the cell flow selection circuit 33f of the switching control unit 32c.
Selects the standby cell flow 110, and the cell flow selection circuit 33h of the switching control unit 32d selects the standby cell flow 111.
When the cell flow selection circuit 33b of the switching control unit 32a selects the standby system cell flow 113, the cell flow selection circuit 33d of the switching control unit 32b selects the standby system cell flow 110 and the cell flow of the switching control unit 32c. The selection circuit 33f selects the standby cell flow 111, and outputs the cell flow selection circuit 3 of the switching control unit 32d.
3 h selects the standby cell stream 112.

Next, the working cell flow 132 selected by the cell flow selection circuit 33a and the working cell flow 133 selected by the cell flow selection circuit 33b are input to the switching circuit 34a. In addition, the active cell flow 13 selected by the cell flow selection circuit 33c.
4 and the active cell flow 1 selected by the cell flow selection circuit 33d.
35 is input to the switching circuit 34b. The active cell flow 136 selected by the cell flow selection circuit 33e and the active cell flow 137 selected by the cell flow selection circuit 33f are input to the switching circuit 34c. The active cell flow 138 selected by the cell flow selection circuit 33g and the active cell flow 139 selected by the cell flow selection circuit 33h are input to the switching circuit 34d.

Next, the operation of the switching circuits 34a to 34d will be described. Since the operations of the switching circuits 34a to 34d are the same, the operation of the switching circuit 24a will be described here.
In the switching circuit 34a, the input active cell flow 13
Since the phase of the cell for speed adjustment 2 and the phase of the cell for speed adjustment in the backup system cell flow 133 are asynchronous, as shown in FIG. Working cell flow 132 and standby cell flow 1
The phase of the speed adjustment cell included in 33 is adjusted.
In this case, the speed adjustment cell shift absorption circuit 51 sets the phase of the speed adjustment cell of the standby system to the phase of the speed adjustment cell inserted into the current system, using the current system as a reference system.

Next, this speed adjustment cell shift absorbing circuit 5
One operation will be described with reference to FIGS. First, the active cell flow 132a shown in FIG. 7 is input to the speed adjustment cell detector 61a shown in FIG. 6, and the standby cell flow 133 shown in FIG.
Is input to the speed adjustment cell detector 61b shown in FIG. When the speed adjustment cell detection unit 61a detects the speed adjustment cell 78a of the active system cell stream 132a shown in FIG. 7, the detection is notified to the control unit 64. This allows
The control unit 64 prohibits the memory 62 from reading data. This memory 62 is a memory for temporarily storing valid cells when inserting a speed adjusting cell into the standby system cell flow 133. At this time, “cell A” and “cell B” are already stored in the memory 62.

The speed adjusting cell and the normal idle cell are clearly identified by the flag of the switching header shown in FIG.

Accordingly, the valid cell A of the standby cell flow 133
Reading is delayed. At this time, the current cell flow 1
The speed adjusting cell insertion circuit 63 adjusts the phase of the speed adjusting cell 78e so as to match the phase of the speed adjusting cell 78e.
8 g are newly inserted. Therefore, the valid cell 71d (cell A) of the standby cell flow 151 is output after the speed adjusting cell 78g. In addition, the speed adjustment cell detector 61 of the standby system
If b detects the speed adjusting cell 78c of the standby system cell flow 133, the speed adjusting cell 78c is stored in the memory 62.
Do not write to

As a result, the phase of the speed adjusting cell 78e of the working cell flow 132b (same as the phase of the speed adjusting cell 78a of the working cell flow 132) and the phase of the speed adjusting cell 78g are matched. Further, even when the standby system speed adjustment cell detection unit 61b detects the speed adjustment cell 78d of the standby system cell flow 133, the speed adjustment cell 78 is also detected.
When d is not written in the memory 62 and the speed-adjusting cell detector 61a of the active system detects the speed-adjusting cell 78b of the active cell flow 132a, the speed is adjusted to match the phase of the speed-adjusting cell 78b. Cell 78h is inserted. As a result, the phase of the speed adjusting cell 78f of the active system cell stream 132a (same as the phase of the speed adjusting cell 78b of the active system cell stream 132) matches the phase of the speed adjusting cell 78h of the backup system cell stream 151. Be included.

Therefore, when the cell stream is created from the SDH frame, even if the phase of the speed adjustment cell inserted into the working cell stream and the protection cell stream is asynchronous, the phase search and the phase search can be performed by taking synchronization. Normal operations such as phase absorption and synchronization establishment can be guaranteed.

Although the working system is used as the reference system here,
It goes without saying that the standby system may be used as the reference system. The above is the description of the operation of the speed adjustment cell shift absorbing circuit 51.

Next, the current cell flow 132 and the standby cell flow 15 output from the speed adjustment cell deviation absorbing circuit 51 are output.
1 is a phase measuring circuit 52 and a variable delay circuit 53 shown in FIG.
Input to a and b. The phase measurement circuit 52 compares the phase of the active cell stream 132 with the phase of the standby cell stream 151, and sets an initial value 0 to a counter nd (step s901 in FIG. 9). As a result of this comparison, it is checked whether or not the cells of both systems match (step s902 in FIG. 9). If the cells of both systems do not match, the process jumps to step s907 where the counter nd is larger than the maximum value. (Step s907 in FIG. 9), and if the counter nd is not larger than the maximum value, nd is incremented by one (step s910 in FIG. 9) to compare again with the next cell. The process returns to step s902. Step s90
In step 7, if the value of the counter nd is larger than the maximum value, it means that there is no match even when compared with all cells. After that (YES at 600 Mbps here), the standby cell flow selection circuits 33b, d, f, and h switch the standby cell flow selection system to another system (step s909).
Above, the process returns to step s901 in order to compare the working cell flow with the standby cell flow after switching.

For example, when the standby cell flow selection circuit 33b compares the active cell flow 106 with the standby cell flow 110 and the result of the comparison does not match, the standby cell flow 1
10 to the standby cell flow 111 (step s9
09), the active cell flow 106 and the standby cell flow 111
Are compared again (step s901). Further, when the comparison result is inconsistent, the standby cell flow selecting circuit 33b changes the standby cell flow from the cell flow 111 to the cell flow 112.
(Step s909), and the active cell flow 10
6 is compared with the standby system cell stream 112 again (step s).
901). In this way, the comparison between the active cell flow 106 and the switched standby cell flow is repeated while the sequence of the standby cell flow is switched one after another until the active cell flow 106 matches the standby cell flow.

As a result of the comparison in step s902, if the working system cell flow 151 and the protection system cell flow 152 match, the counter nd at that point (counter nd eventually determines the phase difference between the working system cell flow and the protection system cell flow). Will represent)
In order to determine the phase difference between the active cell flow and the standby cell flow, both cells are compared at (n-1) times nd cell interval (step s903), and both are (N-1) times It is checked whether or not they match continuously (step s904). As a result of this comparison, if the cells do not match even once, it means that the two cells just coincided and the phase difference has not yet been determined, so the process jumps to step s907 again, and the counter (phase difference) nd If the value does not exceed the maximum value, the counter nd is counted up and both cells are compared again with the next cell. If the value nd exceeds the maximum value, the standby cell flow is switched (step After performing step s709), the process jumps to step s901 to search again for the phase difference between the active cell flow and the standby cell flow from the beginning.

The result of the comparison in step s904 (N
-1) If the cells match successively, it can be determined that the phase difference has been determined, and then the control unit 3a of the switching control unit 32a
5 checks whether the transmission speed of the input cell stream is 600 Mbps (high speed) (step s905). in this case,
Since the transmission speed of the input cell flow is assumed to be 600 Mbps, the answer is yes.
Here, it is checked whether or not the order of the cell flow selection system selected by the cell flow selection circuit 33 is normal. In this case, the active and standby cell flow selection circuits selected by the active and standby cell flow selection circuits 23 do not overlap each other, and therefore the control unit 3
5 checks whether the sequence of the working cell flow and the sequence of the protection cell flow correspond in order.

For example, the active system flow selection circuit 33a selects the active system flow 106 for the active system flow SL1 and the active system flow selection circuit 33c selects the active system flow 107 for the active system flow SL2. , Working cell flow selection circuit 33
e is an active system selection system for selecting the active system cell stream 108.
3. The working cell flow selection circuit 33g outputs the working cell flow 109
, The standby system flow selecting circuit 33b selects the standby system flow 110, the standby system selection system SL1 selects the standby system flow 110, and the standby system flow selection circuit 33d selects the standby system flow 111. The system selection system is SL2, the standby cell flow selection circuit 33f is the standby system selection system for selecting the standby cell flow 112, and the standby cell flow selection circuit 33h is the standby system selection system for selecting the standby cell flow 113. Assuming that SL4 is, for example, each of the working cell flow selection circuits 33a, 33c, 33e, 33g for the working cell flow divided into four.
Are respectively the active system selection systems SL1, SL2, SL3, SL
When 4 is selected, each of the spare cell flow selecting circuits 33b, 33d, 33f,
33h are standby system selection systems SL1, SL2, SL respectively
3, the standby cell flow selection circuits 33b, 33d, 33f, 33h select the standby system selection systems SL2, SL3, SL4, SL1, respectively, or the standby cell flow selection circuits 33b, 33d. , 33f, 33
h is the standby system selection system SL3, SL4, SL1, S
L2 or a standby cell flow selection circuit 33
b, 33d, 33f, and 33h are spare system selection systems S, respectively.
If any one of the four methods of selecting L4, SL1, SL2, and SL3 is satisfied, it is considered that the sequence of the working cell flow and the sequence of the protection cell flow correspond in order. It is.

As a result of the above check in step s906, if the order of the cell flow sequence selected by the cell flow selection circuit 33 is normal, that is, if the sequence of the working cell flow and the sequence of the standby cell flow correspond in order, the synchronization is established. Proceed to the confirmation process.
As a result of the check, if the order of the cell flow sequence selected by the cell flow selection circuit 33 is not normal, the sequence of the standby cell flow selection circuit is switched (step s909), and the phase of the active cell flow is again determined. The process returns to step s901 to start over from the phase difference measurement with the phase of the standby cell flow.

As described above, only when the selection systems of the selection circuits in the active system and the standby system are all normal, the four switching control units 32 simultaneously end the synchronization search process and shift to the synchronization confirmation process. In the synchronization confirmation process, the variable delay circuits 53a and 53b shown in FIG. 5 insert or delete delays using the speed adjustment cells.
... D perform delay insertion or deletion while linking each other. Furthermore, after synchronization is established in the synchronization confirmation process,
When there is a switching command from the outside, the selection circuit 54 of each of the switching circuits 34a to 34d simultaneously performs the instantaneous interruption switching from the active cell flow to the standby cell flow. The switched cell stream is multiplexed again by the MUX circuit 25 and output as the output cell stream 105.

Even if the transmission line cell flow is faster than the above operation, it is possible to realize instantaneous interruption switching.

According to this embodiment, when a cell stream is created from an SDH frame, synchronization is achieved even if the phases of the speed adjustment cells inserted into the working cell stream and the standby cell stream are asynchronous. This has the effect that normal operations such as phase search, phase absorption and synchronization establishment can be guaranteed. In addition, even when the transmission path cell flow is at a high speed, there is an effect that instantaneous interruption switching can be realized.

Embodiment 2 Next, the transmission path cell flow is 60
150Mbps (low speed) instead of 0Mbps (high speed)
The case will be described. Transmission line cell flow is 150Mbp
1, 2 and 3 can also be used in the case of s (low speed). In this case, the DMUX circuit 31 transmits the input transmission line cell flow without dividing it and uses it as it is.
The current cell flow of Mbps and the standby cell flow of 150 Mbps are always selected. For example, the cell flow selection circuit 33a always selects the active cell flow 106, the cell flow selection circuit 33b always selects the backup cell flow 110, the cell flow selection circuit 33c always selects the active cell flow 107, The cell flow selection circuit 33d always selects the standby cell flow 111, the cell flow selection circuit 33e always selects the working cell flow 108, the cell flow selection circuit 33f always selects the standby cell flow 112, The selection circuit 33g outputs the current cell flow 10
9, the cell flow selection circuit 33h always selects the standby cell flow 113. As a result, the cell flow of the transmission line becomes 60
Processing can be performed in the same manner as in the case of 0 Mbps (high speed).

However, in this case, in FIG. 3, since only one of the four switching control units 32a to 32d is used, there is a waste in mounting. Therefore, it is necessary to eliminate such waste. FIG. 10 is a configuration diagram configured to eliminate such waste. 10, the same reference numerals as those in FIG. 3 denote the same or corresponding parts. 1
001 is transmitted through the input four active cell streams 103a to 103d without being divided, and is transmitted as it is to the current active cell streams 106 to
9, a DMUX circuit which outputs the input four spare cell streams 104a-d without splitting them and outputs the same as the spare cell streams 110-113.
02 denotes a cell flow 141 to 144 from the switching circuits 34a to 34d.
And outputs it as output cell streams 105a-105d as they are. Reference numerals 103a to 103d denote working cell flows # 1 to # 4, and 104a to d denote protection cell flows # 1 to # 4.
4, 105a to 105d are output cell streams # 1 to # 4.

Next, the operation of the duplex switching device shown in FIG. 10 will be described. DMUX circuit 1001 is SDH processing unit 1
When the four 150 Mbps active cell streams 103a-d and the standby cell streams 104a-d sent from 21 are input, the DMUX circuit 1001 transmits the cell streams as they are, and the current cell streams 106-109 and This is output as the standby cell flows 110 to 113. DMUX circuit 10
The cell streams 106 to 113 output from 01 are input to the switching controllers 32a to 32d. The cell flow selection circuits 33a to 33h provided in the switching control units 32a to 32d fixedly select the active cell flow and the standby cell flow to be used for each switching control unit 32, respectively. Thereafter, the same operation as described above is performed, and the cell flows output from the switching control units 32a to 32d are supplied to the MUX circuit 1002
Is input to The MUX circuit 1002 includes a switching control unit 32a
Ｄd through the cell flow, and output as output cell flows 105a〜105d.

According to the above operation, the cell flow of the transmission path is 150 M
In the case of bps, non-instantaneous switching of 150 Mbps cell flow of four lines can be realized.

According to this embodiment, it is possible to realize the instantaneous switching of the cell flow of the low-speed transmission path, and to improve the efficiency of mounting.

In the above embodiment, the case where the number of input cell flows is four is described. However, it is needless to say that the number of input cell flows is not limited to four.

Embodiment 3 1, 2 and 3 are also used in this embodiment. FIG. 11 is a block diagram showing the configuration of a delay inserting means for inserting a delay by using a speed adjusting cell when absorbing a phase difference between a current cell flow and a standby cell flow. The means is provided after the speed adjustment cell shift absorption circuit 51 and before the selection circuit 54 shown in FIG.
This corresponds to a portion composed of b and the controller 55. FIG. 12 is an operation explanatory diagram showing the operation of the delay insertion means shown in FIG. FIG. 13 is a cell flow transition diagram showing a transition state of a cell flow when a delay is inserted using the rate adjusting cell according to the present invention for explaining the operation of this embodiment, and FIG. FIG. 8 is a cell flow transition diagram showing a transition state of a cell flow when a delay is inserted using the idle cell of FIG.

In FIG. 11, the same symbols as those in FIG. 5 indicate the same or corresponding parts. 1101 is the current cell flow 13
2 and a speed adjustment cell detection circuit 1111 and 1111 for detecting a speed adjustment cell included in the standby system cell stream 151 output from the speed adjustment cell shift absorption circuit 51.
Is provided in the switching circuit 34, and the variable delay circuit 5 shown in FIG.
A delay insertion control unit 1102 corresponding to a circuit obtained by combining 3a, the variable delay circuit b, and the control circuit 55; an idle cell conversion circuit 1102 for converting a speed adjustment cell into an idle cell;
03 is a memory, 1104 is a write control circuit for controlling cell writing to the memory 1103, 1105 is a memory 1
A read control circuit for controlling the cell reading from 103, a speed adjustment cell insertion circuit 1106 for inserting a delay by using a speed adjustment cell, and a protection cell flow 151 or a speed adjustment cell insertion 1107 having a leading phase. A selector 1108 for selecting one of the outputs from the circuit is a control unit for controlling the idle cell conversion circuit 1102, the memory 1103, the write control circuit 1104, the read control circuit 1105, and the speed adjustment cell insertion circuit 1106. This configuration is the same for the other cell flow selection circuits 33b, c, and d.

In FIG. 12, reference numerals 1207a-e denote speed adjusting cells, 1208a and b denote idle cells converted from the speed adjusting cells, 1201a-c (cell A),
1202a to f (cell B), 2103a to f (cell C), 1204a to f (cell D), 1205a to f (cell E), 1206a and b are valid cells other than the speed adjustment cell and other than the idle cell, 132a Is the active system input cell flow with a delayed phase, 151 is the active system input cell flow with a advanced phase, 132b is the active system cell flow with a delayed phase in the variable delay insertion control unit 1110, and 11001 is stored in the memory 1103. The standby system flow having the advanced phase before the delay insertion, the active system flow 152 output from the variable delay insertion control unit 1110 and having a delayed phase, and 153 the speed adjustment cell insertion circuit of the delay insertion control unit 1111 1106
Is a backup cell flow after delay insertion, output from the selector 1107 through the selector 1107.

Next, the operation of the speed adjusting cell insertion means shown in FIG. 11 will be described with reference to FIG. The active cell flow and the standby cell flow transmitted from the opposite device 11 are processed in the same manner as in the first embodiment, and as shown in FIG. The cell stream 151 output from the cell shift absorbing circuit 51 is input to the delay insertion control units 1110 and 1111 together. In addition, the cell flows 132 and 151 correspond to the speed adjustment cell detection circuit 1.
The speed detection cell detection circuit 11
01 performs a phase comparison between the cell stream 132 and the cell stream 151. Here, it is assumed that the cell stream 151 is ahead of the cell stream 132 in phase. In the synchronization confirmation process, the speed adjustment cell detection circuit 1101 first detects a speed adjustment cell inserted into the cell stream 151 of the system whose phase is advanced.

When the speed adjustment cell detection circuit 1101 detects a speed adjustment cell, an idle cell conversion circuit 1102 provided in the delay insertion control unit 1111 converts the speed adjustment cell into an idle cell, and Avoid recognition. The converted idle cells are written into the phase absorption memory 1103 under the control of the write control circuit 1104. Further, when the speed adjustment cell detection circuit 1101 detects a speed adjustment cell inserted in the cell stream 132 of the system whose phase is delayed, the speed adjustment cell detection circuit 1101 notifies the control unit 1108 of the detection, and notifies the control unit 1108 of the detection. 110
8 instructs the read control circuit 1105 to prohibit read.

As a result, the memory 1103 does not read out the cells for speed adjustment in the cell stream 151 whose phase is advanced. At the same phase, a new cell for speed adjustment is inserted. By both the conversion 1208b to the idle cell and the insertion of the speed adjustment cell 1207e, 1
The phase difference can be absorbed by inserting a delay corresponding to a cell. The delay insertion control units 1110 and 11 shown in FIG.
11 has the same configuration as the cell flow 132 and the cell flow 151.
If the delay is further advanced, the delay insertion control unit 1110 performs the same delay insertion on the cell stream 132 as described above.

FIG. 12 shows FIGS. 1, 2, 3, and 11.
FIG. 4 is an operation explanatory diagram showing the operation of the cell flow shown in FIG. 12, reference numerals 1207a to 1207e denote speed adjustment cells, and 1208.
a and b are idle cells converted from the speed adjustment cell, 1
201a-c (cell A), 1202a-f (cell B),
1203 a to f (cell C), 1204 a to f (cell D), 1205 a to f (cell E), and 1206 a to b (cell F) are valid cells other than the speed adjustment cell and other than the idle cell.

Next, the above-mentioned operation will be specifically described with reference to the cell flow shown in FIG. The cell flow 151 is the cell flow 13
Assume that the phase is ahead of 2a by one cell. When the speed adjustment cell detection circuit 1101 detects the speed adjustment cell 1207b in the cell stream 151, the idle cell conversion circuit 1102 converts the speed adjustment cell 1207b into the idle cell 1208a. The converted idle cell 1208a is written to the memory 1103. Further, the speed adjustment cell detection circuit 1101 detects the cell flow 132a.
, When the speed adjustment cell 1207a is detected, the speed adjustment cell insertion circuit 1206
The cell for speed adjustment 1207e is added to the cell stream 11001 read from the memory 1103 so as to match the position of 7d.
Is newly inserted.

As a result, a delay of one cell can be inserted into the cell stream 151. The cell flow 153 shows the result of inserting a delay for one cell. As a result, cells 1204e (cell D) and 1204f (cell D)
Subsequent synchronization is established. Although the example of FIG. 11 shows a case where the delay difference is one cell, when the delay difference becomes one or more cells, the above processing is repeated until a cell for adjusting the speed of the delay difference to be inserted is received. .

Next, the reason for providing the speed adjusting cell will be described. FIG. 13 shows a transition state of a cell flow in a process of processing a cell flow in a case where a delay for two cells is inserted into a working cell flow using a speed adjustment cell by distinguishing a speed adjustment cell from an idle cell. FIG. 14 is a cell flow transition diagram. FIG. 14 shows a conventional example in which a delay of two cells is inserted into a working cell flow using an idle cell instead of a speed adjustment cell without distinguishing between a speed adjustment cell and an idle cell. FIG. 8 is a cell flow transition diagram showing a transition state of a cell flow when a cell flow is processed by a method.

In FIG. 13, reference numeral 1301 denotes the opposing device 11.
, A cell flow output from the speed adjustment cell shift absorbing circuit 51, a cell flow output from the idle cell conversion circuit 1102,
Reference numeral 304 denotes a cell flow output from the speed adjusting cell insertion circuit 1106. In FIG. 14, reference numeral 1401 denotes a cell flow transmitted from the opposite device 11, and here, the cell configuration is the same as that of the cell flow 1301 for the sake of comparison with the cell flow of FIG. Reference numeral 1402 denotes a cell flow input to the variable delay circuit 2502, and reference numeral 1403 denotes a cell flow output from the variable delay circuit 2502.

Next, a description will be given while comparing the cell flows shown in FIGS. As shown in FIG.
When a cell stream 1301 is input from the SDH processing unit 12
Numeral 1 designates a cell for adjusting the speed of both the active system and the standby system, and then the speed adjustment cell shift absorbing circuit 51 causes the position of the cell for adjusting the speed of the active system flow and the position of the speed adjusting cell of the standby system flow. And a cell flow 1302 is created. In this example, in the cell flow 1302, the current cell flow “AB”
Immediately after the “empty and empty CD” (the position indicated by “△” in the drawing) and immediately after “E-sky FGH empty IJ” in the working system flow (the position indicated by “△” in the diagram), both the working cell flow and the standby cell flow are used. Insert a cell for speed adjustment. Next, the cell flow 13 including this speed adjusting cell
02 is input to the idle cell conversion circuit 1102 of the delay insertion control section 1111 of the switching circuit 34, and the idle cell conversion circuit 1102 is a cell for adjusting the speed of the cell flow of the system whose phase is advanced (the current system cell flow in this example). Is converted to an idle cell and a cell stream 1303 is output. Next, the speed adjustment cell insertion circuit 806 inserts the speed adjustment cells into the current system cell flow so as to match the position of the speed adjustment cell in the standby system cell flow, and creates a cell flow 1304.

On the other hand, as shown in FIG. 14, in the conventional example, when the same cell flow 1401 as the speed adjustment idle cell flow 1301 is input from the opposing device 11, the SDH processing unit 121 performs speed adjustment for both the active system and the standby system. (In this example, at the position indicated by the triangle in the figure) to create a cell flow 1402. This cell flow 1402 and FIG.
The cell flow 1302 shown in FIG. 7 is only that the speed adjusting cell is replaced by the idle cell. The cell stream 1402 into which the idle cells for speed adjustment are inserted is supplied to the variable delay circuit 25.
02 is input. The variable delay circuit 2502 continuously detects the same number of idle cells for speed adjustment as the number of idle cells for speed adjustment inserted by the SDH processing unit 121 so as to adjust to the position when detecting idle cells in the standby cell flow. To create a cell flow 1403. Therefore, in this example, in the cell flow 1403, two idle cells for speed adjustment are continuously placed at the position of the active cell flow corresponding to the position of the idle cell at the beginning of the standby cell flow (the position indicated by the mark in the figure). Insert cells.

In the conventional idle cell insertion method for speed adjustment, the idle cells for speed adjustment are continuously inserted at the position of the first idle cell. Since the adjustment idle cell is deleted, the degree of continuous appearance of effective cells (burst property) is increased by that amount (this is referred to as large cell fluctuation). Since the burstiness of the valid cells increases as the number of idle cells for speed adjustment in the SDH processing unit 121 increases, an overflow occurs when a subsequent circuit (not shown) processes the valid cells. In some cases, processing becomes impossible. On the other hand, according to the rate adjusting cell insertion method according to the present invention, the rate adjusting cell insertion circuit 1106 disperses and inserts the rate adjusting cells between the valid cells, so that the degree to which the valid cells continuously appear is determined. (Burst property) can be suppressed accordingly (this is referred to as small cell fluctuation). Accordingly, when a subsequent circuit (not shown) processes a valid cell, an overflow is less likely to occur, and the normal operation can be guaranteed.
Note that the cell fluctuation refers to a shift between the effective cell before and after the speed adjustment cell or the speed adjustment idle cell is inserted.

According to this embodiment, it is possible to absorb the phase difference between the cell flows of both systems. Further, the use of the speed adjusting cell has an effect that the cell fluctuation can be suppressed as compared with the related art.

Embodiment 4 FIG. 15 illustrates a case where the phase difference between the active system and the standby system is absorbed in the first embodiment.
FIG. 4 is a configuration diagram illustrating a configuration of a delay removing unit that removes a delay using a cell for speed adjustment. FIG. 16 is an operation explanatory diagram showing the operation of the delay deletion means shown in FIG. FIG.
, The same reference numerals as those in FIG. 11 indicate the same or corresponding parts. Reference numerals 1510 and 1511 denote delay deletion control units that perform control to delete the delay. Also, in FIG.
a to c are speed adjusting cells, 1601a to 160d (cell A),
1602a-d (cell B), 1603a-d (cell C), 1604a-d (cell D), 1605a-c (cell E), 1607a-b (cell Z) are cells other than the speed adjustment cell, 132, 152 is a phase-advanced cell flow,
Reference numeral 151 denotes a cell flow whose phase is delayed before the delay is removed, 143
Is the cell flow after delay removal.

Next, the operation of the delay elimination means shown in FIG. 15 will be described. The cell stream 132 and the cell stream 151 are input to the delay elimination means in the same manner as in the third embodiment.
Assume 1 is out of phase with cell stream 132. In the synchronization confirmation process, when the speed adjustment cell detection circuit detects a speed adjustment cell inserted in the cell stream having a delayed phase, the speed adjustment cell detection circuit 1101 controls that the speed adjustment cell has been detected. Notifying the control unit 1108
Command the write control circuit 1104 to prohibit writing of the speed adjustment cell to the memory. Memory 110
3 does not write the speed adjustment cell when the write inhibit command is input. This makes it possible to eliminate the delay from the cell stream 151 of the system whose phase is delayed.
The delay deletion control units 1510 and 1511 shown in FIG.
Have the same configuration. For example, the cell flow 132 is
If the phase is later than 1, the above-described delay removal is performed on the cell stream 132.

Next, the above operation will be described in detail with reference to the cell flow shown in FIG. In FIG. 16, cell flow 1
51 assumes that the phase is behind the cell stream 132 by one cell. When the speed adjustment cell detection circuit 1101 detects the speed adjustment cell 1606b in the cell stream 151, the speed adjustment cell 1606b is not written into the memory 1103, so that the phase of the cell stream 151 is changed to the cell 1
After 602d (cell B), the process proceeds by one cell (cell flow 153). As a result, the cell 1603c of the cell flow 153
(Cell C) and synchronization after the cell 1603d (cell C) are established. Although the example of FIG. 16 shows a case where the delay difference is one cell, when the delay difference becomes one or more cells, the above processing is repeatedly performed until a cell for adjusting the speed of the delay difference to be deleted is received. Thereby, the phase difference between the two systems can be absorbed.

Further, by using the speed adjusting cell, it is possible to suppress the fluctuation of the cell. The reason will be described below.

FIG. 17 is an explanatory diagram showing an example in which a delay of two cells is deleted from the cell stream of the standby system by using the speed adjustment cell while distinguishing between the speed adjustment cell and the idle cell. FIG. 18 shows an example of a case where the delay for two cells is deleted from the standby cell flow by using the idle cells instead of the speed adjustment cells without distinguishing between the speed adjustment cells and the idle cells. FIG.

In FIG. 17, reference numeral 1701 denotes a cell flow from the opposing device, and 1702, a cell shift absorbing circuit 51 for speed adjustment.
1703 is an input cell flow inputted to the delay elimination means, and 1703 is an output cell flow from the delay elimination means. In FIG. 18, reference numeral 1801 denotes a cell flow from the opposing device,
It is the same as 01. Reference numeral 1802 denotes an input cell flow input to the delay elimination unit after an idle cell for speed adjustment is added by the SDH processing unit 121, and reference numeral 1803 denotes an output cell flow from the delay elimination unit.

Next, a description will be given while comparing the cell flows shown in FIGS. As shown in FIG.
When a cell stream 1701 is input from the SDH processing unit 12
Reference numeral 1 denotes a cell for adjusting the speed in both the active system and the standby system, and then the speed adjustment cell shift absorbing circuit 51 detects the phase of the cell for adjusting the speed of the active cell flow and the phase of the cell for adjusting the speed of the standby cell flow. Are combined to create a cell flow 1702. In this example, in the cell flow 1702, the current cell flow “AB”
Both the current cell flow and the standby cell flow immediately after the “empty and empty CD” (the position indicated by “△” in the figure) and immediately after the “active EGH FGH empty IJ” (the position indicated by “△” in the diagram). Insert the cell for speed adjustment into. Next, the cell flow 1 including the speed adjusting cell
702 is input to the delay elimination control unit 1511 memory 1103 of the switching circuit 34 and the speed adjustment cell detection circuit 1101. When the speed adjusting cell detecting circuit 1101 detects a standby speed adjusting cell having a delayed phase, it notifies the control unit 1108 of this fact, and in accordance with a command from the control unit 1108, the speed adjusting cell of the standby system flow. Delete cell flow 170
Create 4.

On the other hand, as shown in FIG. 18, in the conventional example, when the same cell flow 1801 as the speed adjustment idle cell flow 1701 is input from the opposing device 11, the SDH processing unit 121 performs speed adjustment for both the active system and the standby system. (In this example, the cell flow 1802 is added at the position indicated by the triangle in the figure). The cell flow 1802 and the cell flow 1702 shown in FIG. 17 are different from the cell flow 1802 only in that the speed adjusting cells are replaced by idle cells. The cells of the standby system are “YZAB empty, empty, empty,...”, But this is combined with the cell flow 1702 for simplicity of explanation, and this is not always the case. The cell stream 1802 into which the idle cells for speed adjustment are inserted is input to the variable delay circuit 2502. The variable delay circuit 2502 is
When an idle cell in the standby cell flow is detected, the same number of idle cells for speed adjustment as the number of idle cells for speed adjustment inserted by the SDH processing unit 121 are continuously deleted by adjusting the position to the position thereof. 1803 is created. Therefore, in this example, in the cell stream 1803, two idle cells for speed adjustment are continuously arranged at the position of the active cell stream corresponding to the position of the leading idle cell of the backup system cell stream (the position indicated by a mark in the figure). Delete cells. Therefore, the cell flow 180
The cell flow of the standby system of No. 3 is “YZAB empty CDE empty FGH empty empty IJKL empty ...”. When this is compared with the standby system of the cell flow 1802, “CDE” after “YZAB empty / empty / empty”
The sky FGH sky sky IJKL sky ... "has a fluctuation of two cells.

In the conventional idle cell for speed adjustment, the idle cells for speed adjustment are continuously deleted at the position of the first idle cell. Therefore, the degree of continuous appearance of effective cells (burst property) depends on that. (The cell fluctuation is large). Since the burstiness of the valid cells increases as the number of idle cells for speed adjustment in the SDH processing unit 121 increases, an overflow occurs when a subsequent circuit (not shown) processes the valid cells. In some cases, processing becomes impossible. On the other hand, according to the rate adjustment cell deletion method according to the present invention, the delay deletion control unit 1
Since the cell 111 deletes only the cells for speed adjustment dispersed among valid cells, the idle cells are not deleted and the degree of continuous appearance of valid cells (burst property) is suppressed correspondingly (cell fluctuation is small). ). Accordingly, when a subsequent circuit (not shown) processes a valid cell, an overflow is less likely to occur, and the normal operation can be guaranteed.

According to this embodiment, it is possible to absorb the phase difference between the cell flows of both systems. Further, the use of the speed adjusting cell has an effect that the cell fluctuation can be suppressed as compared with the related art.

Embodiment 5 FIG. FIG. 19 is a configuration diagram showing a configuration in the case where delay elimination means eliminates a delay using a speed adjustment cell and an idle cell in the fourth embodiment. FIG. 20 is an operation explanatory diagram showing the operation of the delay deletion means shown in FIG. In FIG. 19, FIG.
The same reference numerals as 5 indicate the same or corresponding parts. 1901 is an idle cell detection circuit.

In FIG. 20, 2008a-c denote idle cells, 2009a-c denote speed adjustment cells,
01a-d (cell A), 2002a-d (cell B), 2
003a-d (cell C), 2004a-d (cell D),
2005a-d (cell E), 2006a-c (cell F), 2007a-c (cell G), 2010a-b (cell Y), 2011a-b (cell Z) are cells other than the speed adjustment cell, and 132 is Input cell stream with advanced phase, 15
1 is an input cell flow having a delayed phase before delay removal, 152
Is an output cell flow with advanced phase, and 153 is an output cell flow after delay elimination.

Next, the operation of the delay elimination means shown in FIG. 19 will be described. In the synchronous search process, the cell stream 132 and the cell stream 151 are compared in phase, and it is assumed that the cell stream 151 is behind the cell stream 132 in phase. Thereafter, in the synchronization confirmation process, when the speed adjustment cell detection circuit 1101 detects a speed adjustment cell inserted in the cell stream 151 of the system with a delayed phase, the control unit 110
Notify 8. Upon detecting an idle cell inserted in the cell stream 151, the idle cell detection circuit 1901 notifies the control unit 1108 that the idle cell has been detected. When the control unit 1108 is notified that the speed adjustment cell or the idle cell has been detected, the control unit 1108 instructs the write control circuit 1104 to prohibit the writing of the speed adjustment cell or the idle cell to the memory 1103. Command. The memory 1103 does not write the speed adjustment cell or the idle cell according to the write inhibit command.

As a result, the delay of the cell stream 151 having a delayed phase can be eliminated more rapidly than in the fourth embodiment. The delay insertion control unit 1 shown in FIG.
510 and 1511 have the same configuration.
If 51 is behind the phase of the cell stream 132, the delay insertion control unit 1510 performs the above-described delay deletion on the cell stream 132.

Next, the reason why the data can be quickly deleted will be described with reference to the cell flow shown in FIG. 20 as an example. It is assumed that the cell stream 151 is behind the cell stream 132 by two cells in phase. In the cell stream 151, when the idle cell detection circuit 1901 detects the idle cell 2008b, the phase is advanced by one cell from the cell 1512b by not writing the idle cell 2008b to the memory 1103. Similarly, when the speed adjustment cell detection circuit 1101 detects the speed adjustment cell 2009b, the phase of the cell 2003d (cell C) is further shifted from the cell 2003d (cell C) by not writing the speed adjustment cell 2009b to the memory 1103. The synchronization is established after the cell 2004c (cell D) of the cell stream 152 and the cell 2004d (cell D) of the cell stream 153. Although the example of FIG. 20 shows the case where the delay difference is two cells, when the delay of a plurality of cells is deleted, the above-described steps are repeated until a cell for speed adjustment or an idle cell for the cell to be deleted is detected. Perform processing.

According to this embodiment, when the delay is eliminated by using the idle cell, the cell fluctuation occurs.
The phase difference between the two systems can be absorbed faster than in the third embodiment.

Embodiment 6 FIG. FIG. 21 is a flowchart illustrating a processing flow relating to forced switching of the duplex system switching device when synchronization is not established in the first embodiment. The operation of the dual system switching device will be described below with reference to the flowchart shown in FIG. This flowchart shows a flow of a forcible switching process that is executed when the device itself fails. First, it is determined whether or not the external switching command is significant (indicating that the external switching command has been received) (step S2101).
If the switching instruction is not significant, the determination is repeated until it becomes significant. When the switching instruction becomes significant, it is determined whether or not the synchronization between the active cell flow and the standby cell flow has been established (step S2102). If the synchronization has been established, the switching is possible, so that the active system is switched to the standby system according to the switching command (step S2103). Also, if synchronization is not established,
Since switching cannot be performed in this state, the cell flow selection circuits 33a, c, e, and g of the active system select the values of the series of cell flows selected by the standby cell flow selection circuits 33b, d, f, and h shown in FIG. After the cell values are adjusted to the same values as the series values of the cell flow, the active system is switched to the standby system (step S2104).

The reason for this is that, in the synchronous search process, since the four switching control units 32 operate independently, if a mismatch occurs in the comparison in the synchronous search process, the sequence of the cell flow to be searched is changed. In order to switch, the same cell flow sequence occurs repeatedly in the four standby cell flow sequences selected as they are, and some sequences of the original cell flow are lost instead. If switching from the active system to the standby system is performed in such a state, the data of the multiplexed active cell flow becomes erroneous data.

For example, the switching control units 33a and 33 shown in FIG.
The active cell flows selected by 3c, 33e, and 33g are 106, 107, 108, and 109, respectively, and the standby cell flows selected by the switching control units 33b, 33d, 33f, and 33h are 110, 111, and 112. , 113, the result of the comparison of each series indicates that the active cell flow 106 and the standby cell flow 1
10 does not match, current cell flow 107 and standby cell flow 11
1, the active system cell flow 108 and the standby system cell flow 112 match, and the active system cell flow 109 and the standby system cell flow 113 match.
Switching from 10 to another series, for example, 111 is performed, and the comparison is made again between the active cell stream 106 and the standby cell stream 111.

After the inconsistency in the series comparison between the active system and the standby system, when the switching instruction from the outside becomes significant in a state where the synchronization has not been established yet, the switching control unit 32a sets the cell flow of the active system. Switching from 106 to the standby cell flow 111, the switching control unit 32b switches from the active cell flow 107 to the standby cell flow 111, and the switching control unit 32c switches from the active cell flow 108 to the standby cell flow 112, and switching control The unit 32d converts the active system cell stream 109 to the standby system cell stream 11
It will be switched to 3. In this case, the switching control unit 32
Since both the active cell flows a and 32b overlap as the cell flow 11, there is no 110 in the cell flow after multiplexing these cell flows, and the overlap 111 remains, and the original 111 remains. The result is abnormal data completely different from the cell flow.
That is, the normality of the data in the cell flow cannot be guaranteed. The process in step S2104 is performed to prevent such a problem from occurring.

According to this embodiment, the cell flow selection circuit 3 can be switched even when the synchronization is not established.
3 normal operation can be guaranteed.

Embodiment 7 FIG. FIG. 22 is a configuration diagram showing a configuration in the seventh embodiment in which the phase of a speed adjustment cell that abnormally arrives in a system that is not the reference is adjusted. In FIG. 22, the same reference numerals as those in FIG. 6 indicate the same or corresponding parts. 2201 is an idle cell conversion circuit.

The phase shift of the speed adjustment cell depends on the shift generated in the speed adjustment cell insertion circuit for inserting the speed adjustment cell.
It can be absorbed by the speed adjustment cell shift absorption circuit in the first embodiment. This can be achieved by mounting a memory having a capacity enough to cope with the speed adjustment cells input asynchronously. However, since the memory area is limited, if the phase shift between the speed adjusting cells of the active system and the standby system is abnormally large, the normality of the cells may not be guaranteed. For example, if the active system is used as a reference system, no effective cells will arrive at all in the standby system due to a failure, etc. There is a case where the service cell does not arrive at all. In this case, no cells can be stored in the memory 62, and each time a cell in the active cell flow arrives, the memory 62
Since only reading of cells stored in the memory 62 continues, an underflow may occur in the memory 62.

A circuit configuration for preventing such a situation from occurring will be described with reference to FIG. When the standby system detects a speed adjustment cell in a state where underflow may occur, the detected speed adjustment cell is
Conversion into an idle cell is performed by an idle cell conversion circuit 2301. The converted idle cells are written to the memory 62. Therefore, the operation is performed as if the idle cells arrived at the memory 62. Therefore, even if an abnormally large number of speed adjustment cells arrive at the standby system, they can be read as idle cells from the memory 62 each time. Can be avoided. Since the cell for speed adjustment and the idle cell are the same as cell information, they do not affect the processing of the subsequent circuit (not shown) at all.

According to this embodiment, no effective cells arrive at the standby system due to a failure or the like, only abnormally many cells for speed adjustment arrive, and only valid cells arrive at the active system. When no use cell arrives, underflow in the memory 62 can be prevented.

Embodiment 8 FIG. FIG. 23 is a configuration diagram showing a configuration in the seventh embodiment in which the phase of the speed adjustment cell that abnormally arrives in the reference system is matched. 23, the same reference numerals as those in FIG. 23 indicate the same or corresponding parts. Reference numeral 2301 denotes an idle cell conversion circuit.

The phase shift of the speed adjustment cell depends on the shift generated in the speed adjustment cell insertion circuit for inserting the speed adjustment cell.
It can be absorbed by the speed adjustment cell shift absorption circuit in the first embodiment. This can be achieved by mounting a memory having a capacity enough to cope with the speed adjustment cells input asynchronously. However, since the memory area is finite, it is conceivable that the cell is not guaranteed if the phase difference between the speed adjusting cells of the active system and the standby system is abnormally large. For example, if the active system is used as the reference system, no effective cells arrive in the active system due to a failure or the like, only abnormally many cells for speed adjustment arrive, and only valid cells arrive in the standby system. When no cells for use arrive at all, the cells for speed adjustment are written to the memory 62 each time the cells for speed adjustment in the active cell flow are detected, so that overflow may occur in the memory 62.

A circuit configuration for preventing such a situation from occurring will be described with reference to FIG. When the working side detects a speed adjustment cell in a state where overflow may occur, the idle cell conversion circuit 23
01 are all converted into idle cells, so even if an abnormally large number of speed adjustment cells arrive at the active system, they can be read from the memory 62 as idle cells each time. Overflow can be avoided. Since the cell for speed adjustment and the idle cell are the same as cell information, they do not affect the processing of the subsequent circuit (not shown) at all.

According to this embodiment, it is possible to prevent overflow in the memory 62.

In the above description, 150 Mbps and 600 Mbps are taken as examples of the cell flow on the transmission line, but it goes without saying that the present invention can be used for a transmission line having a higher speed.

[0124]

According to the first aspect of the present invention, when the input transmission line cell flow is high-speed, it is divided into a plurality of low-speed cell flows on a cell-by-cell basis and output. Cell flow division control means for transmitting the cell stream without dividing the cell flow and outputting the cell flow as it is, and one cell out of a plurality of cell flows outputted from the division control means, provided by the number of cell flows outputted from the division control means. A cell flow selection circuit for selecting a flow and the number of cell flows output from the division control means are provided. By comparing the cell flows of the active system and the standby system, a phase difference between the two systems is searched for. A switching circuit that switches the transmission line from the working system to the standby system without interruption after absorbing and synchronizing the phase difference, and a cell output by the switching circuit when the input transmission line cell flow is fast. Stream is multiplexed and output, and multiple low-speed When input, the multiplexing control means returns to the original cell sequence by transmitting and outputting a plurality of input cell streams as they are, and the plurality of cell flow selection circuits and the switching circuits cooperate with each other. Since control is performed by the control signal as described above, there is an effect that instantaneous interruption switching can be realized not only when the transmission path cell flow is low speed but also when it is high speed.

[0125]

According to the second aspect of the present invention, the SDH processing section determines the speed of the payload information generated when the cell stream is generated from the SDH transmission frame and the cell input to the duplex switching device. Speed adjustment cell inserting means for inserting a speed adjustment cell when the overhead of the received SDH transmission frame reaches a predetermined number of cells. The switching circuit comprises a speed adjustment cell detecting means for detecting a speed adjustment cell, a means for clearly identifying a speed adjustment cell and an idle cell, and a phase advance in the working system and the standby system. And a delay insertion means for inserting a delay into the system using the speed adjustment cell, so that the phases of the working system flow and the standby system flow are absorbed, and the cell of the cell is inserted by inserting the speed adjustment cell. Suppress fluctuation An effect that can be.

According to the third aspect of the present invention, a speed adjusting cell detecting means for detecting a speed adjusting cell, a means for clearly identifying a speed adjusting cell and an idle cell, And a delay elimination means for eliminating a delay from a system having a phase delayed in the system using a speed adjustment cell or using a speed adjustment cell and an idle cell. By absorbing the phase and removing only the speed adjusting cell, there is an effect that the fluctuation of the cell can be suppressed.

[0128]

Further, according to the fourth aspect, the cell flow selecting means, when switching from the working system to the protection system, selects the protection system cell flow even when the synchronization between the working system and the protection system is not established. Since the value of the cell flow sequence selected by the circuit is set to the same value as the value of the cell flow sequence selected by the active cell flow selection circuit, the switching when synchronization is not established by the above means. This also has the effect of eliminating malfunction of the cell flow selection circuit.

According to the fifth aspect of the present invention, when the division control means divides a transmission path cell flow into a plurality of parts and performs processing, the division control means
H processing unit, when the overhead area of the received transmission frame reaches the number of cells corresponding to the number of switching circuits,
Since a speed adjusting cell insertion circuit for continuously inserting the speed adjusting cells for the number of the switching circuits is provided, it is possible to prevent the disorder of the cell order when absorbing the delay difference using the speed adjusting cells. It works.

According to the sixth aspect of the present invention, even if the phase of the speed adjustment cell inserted in the active system cell stream and the backup system cell stream is shifted, the phase is upstream of the phase measurement circuit and the variable delay circuit. By matching the phases of the cells for adjusting the speeds of the active system cell flow and the standby system cell flow, it is possible to ensure a normal operation such as phase search, phase absorption and synchronization establishment.

According to the seventh aspect of the present invention, the speed adjusting cell control means may include an abnormally high frequency of the speed adjusting cell inserted into the non-reference system and the speed inserted into the reference system. When the frequency of the adjustment cells is abnormally low, the system includes a conversion control unit that converts the speed adjustment cells of the system that is not used as a reference into idle cells, and a write control unit that writes the converted idle cells into the memory. Therefore, an effect of preventing underflow in the memory is provided.

According to the eighth aspect of the present invention, the speed adjusting cell control means may include an abnormally high frequency of the speed adjusting cell inserted in the reference system and the speed inserted in the non-reference system. When the frequency of the adjustment cell is abnormally low, the read control unit that reads from the memory and the conversion control unit that converts the speed adjustment cell inserted into the reference system into an idle cell are provided. This has the effect of preventing overflow in the memory.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram showing a configuration of an entire system including a duplex switching device according to the present invention.

FIG. 2 is a configuration diagram showing a configuration of an SDH processing unit 121 when a transmission speed is 600 Mbps.

FIG. 3 is a configuration diagram showing an embodiment of a duplex switching device according to the present invention.

FIG. 4 is a cell transition diagram showing a transition state of a cell flow handled by the DMUX 31 and the MUX 35 shown in FIG.

FIG. 5 is a configuration diagram illustrating a configuration of a switching circuit 34a illustrated in FIG. 3;

6 is a configuration diagram illustrating a configuration of a speed adjustment cell shift absorption circuit 51 illustrated in FIG. 5 in the switching circuit 34a.

FIG. 7 is an operation explanatory diagram showing a transition state of a cell flow in the configuration of the speed adjusting cell shown in FIG. 6;

FIG. 8 is a diagram illustrating various types of cells showing the configurations of a valid cell, an idle cell, and a cell for rate adjustment.

FIG. 9 is a flowchart showing an operation of the duplex switching device shown in FIG. 2;

FIG. 10 is a configuration diagram configured to eliminate useless mounting when the transmission speed is low.

FIG. 11 is a configuration diagram showing a configuration of a delay insertion unit that inserts a delay by using a speed adjustment cell when absorbing a phase difference between a current cell flow and a standby cell flow.

FIG. 12 is an operation explanatory diagram showing an operation of the delay insertion unit shown in FIG. 11;

FIG. 13 is a cell flow transition diagram showing a transition state of a cell flow when a delay is inserted using the rate adjusting cell according to the present invention for explaining the operation of this embodiment.

FIG. 14 is a cell flow transition diagram showing a transition state of a cell flow when a delay is inserted using a conventional idle cell.

FIG. 15 illustrates a case where a phase difference between an active system and a standby system is absorbed.
FIG. 4 is a configuration diagram illustrating a configuration of a delay removing unit that removes a delay using a cell for speed adjustment.

16 is an operation explanatory diagram showing the operation of the delay deletion unit shown in FIG.

FIG. 17 is an explanatory diagram showing an example of a case where a delay for two cells is deleted from a standby cell flow using a speed adjustment cell by distinguishing the speed adjustment cell from an idle cell.

FIG. 18 is a diagram illustrating an example in which a delay of two cells is deleted from a standby cell flow by using an idle cell instead of a speed adjustment cell without distinguishing between a speed adjustment cell and an idle cell. FIG.

FIG. 19 is a configuration diagram showing a configuration in a case where delay elimination means eliminates a delay using a cell for rate adjustment and an idle cell.

FIG. 20 is an operation explanatory diagram showing an operation of the delay deletion unit shown in FIG. 19;

FIG. 21 is a flowchart illustrating a processing flow regarding forced switching of the duplex system switching device when synchronization is not established.

FIG. 22 is a configuration diagram showing a configuration in a case where the phase of a speed adjustment cell that abnormally arrives in a system that is not a reference is adjusted.

FIG. 23 is a configuration diagram showing a configuration in a case where a phase of a speed adjustment cell that abnormally arrives in a reference system is matched.

FIG. 24 shows a conventional SDH processing unit 12 shown in FIG.
1 is a configuration diagram showing a configuration of FIG.

FIG. 25 is a configuration diagram showing a configuration of the conventional duplex switching device shown in FIG. 1 or FIG. 24;

FIG. 26 is a flowchart showing the operation of the conventional duplex switching device shown in FIG.

FIG. 27 is a diagram illustrating the insertion position of the idle cell for adjusting the speed for adjusting the transmission speed of the payload information and the transmission speed of the generated cell being asynchronous between the active system and the standby system.
FIG. 4 is a diagram illustrating a problem that occurs.

FIG. 28 is a view for explaining that an object of the present invention is to obtain means for solving the problem in FIG. 27;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Opposing apparatus 12 Receiving apparatus 21 SDH / cell conversion circuit 22 Buffer 23 Speed adjustment cell insertion circuit 31 DMUX circuit 32 Switching control unit 33 Cell flow selection circuit 34 Switching circuit 35 MUX circuit 51 Speed adjustment cell shift absorption circuit 52 Phase measurement Circuit 53 Variable delay circuit 54 Selection circuit 55 Control unit 61 Speed adjustment cell detection unit 62 Memory 63 Speed adjustment cell insertion circuit 64 Control unit 121 SDH processing unit 122 Duplex switching device 1101 Speed adjustment cell detection circuit 1102 Idle cell Conversion circuit 1103 Memory 1104 Write control circuit 1105 Read control circuit 1106 Speed adjustment cell insertion circuit 1107 Selector 1108 Control unit 1110 Delay insertion control unit 1111 Delay insertion control unit 1510 Delay deletion control unit 1511 Delay deletion control unit 1 01 idle cell detecting circuit 2201 idle cell detection circuit 2301 idle cell detection circuit 2401 SDH / cell conversion circuit 2402 buffer 2403 the rate adjusting idle cell insertion circuit 2501 phase measuring circuit 2502 variable delay circuit 2503 active / standby selection circuit 2504 control unit

──────────────────────────────────────────────────続 き Continued on front page (51) Int.Cl. ⁷ Identification code FI H04Q 3/00 H04L 11/20 D (72) Inventor Hiroyuki Sato 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation (72) Inventor Takamasa Suzuki 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation (72) Inventor Isno Oshima 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 1/22 H04J 3/00 H04J 3/06 H04L 12/28 H04Q 3/00

Claims (8)

(57) [Claims] 1. The same duplicated SDH from an opposite device
Upon receiving the frame, the SDH processing unit that extracts the bay load information excluding the overhead part of the SDH transmission frame in units of cells and generates the same active and standby cell flows, and an SDH processing unit for the active and standby cell flows. Search for the phase difference,
A duplex switching device that switches from the working system to the standby system without an instantaneous interruption without causing cell loss, cell duplication, etc. after phase synchronization, and the duplexing switching device comprises: When the cell flow is high speed, it is divided into a plurality of low-speed cell flows for each cell and output.
Cell flow division control means for transmitting the transmission cell stream without dividing it and outputting it as it is, and a plurality of cell streams divided by the number of cell streams outputted from the division control means are provided . A cell flow selection circuit for selecting one cell flow from the cell flows; and a plurality of cell flows provided by the number of the cell flows output from the division control means. A switching circuit that switches the transmission line from the working system to the standby system without instantaneous interruption after absorbing and synchronizing the phase difference, and when the input transmission line cell flow is high speed, The cell stream output by the switching circuit is multiplexed and output again ,
If a high-speed transmission cell flow is input, multiple input cells
Multiplexing control means for returning the original cell sequence by transmitting the flow as it is, and a plurality of the cell flow selecting circuits and the switching circuits cooperating with each other.
Is controlled by a control signal to operate tone, the cell stream selection circuit selects in advance different working system cell flow, when searching the phase difference between the standby system cell flow, active system cell stream and a standby system If the cell flows do not match, the cell flow selection circuit changes the selection system of the standby cell flow, performs a comparison again, and repeats the change of the selection system until searching for a phase difference. When the flow and the standby cell flow coincide with each other, the value of the selection system of the standby cell flow overlaps between the cell flow selection circuits provided for each of the cell flows divided by the division control means. No, and after confirming that it is the same series as the working cell flow, while cooperating the plurality of switching circuits, absorb the searched phase difference, take phase synchronization, and after establishing synchronization Switching the transmission line system from the working system to the standby system is special. Duplicate processing equipment. 2. An SDH processing section detects a phase difference between a speed of the payload information generated when a cell stream is generated from an SDH transmission frame and a speed of a cell input to a duplex switching device. The overhead section of the superimposed and received SDH transmission frame has a rate adjusting cell insertion means for inserting a rate adjusting cell when the phase shift reaches a predetermined number of cells, and the switching circuit comprises: Speed adjusting cell detecting means for detecting an adjusting cell; means for clearly identifying a speed adjusting cell and an idle cell; and a speed adjusting cell for a system whose phase is advanced in a working system and a standby system. 2. The duplex processing apparatus according to claim 1, further comprising: a delay inserting unit that inserts a delay by using the delay processing unit. 3. The SDH processing unit superimposes a phase shift between a speed of the payload information generated when a cell stream is generated from an SDH transmission frame and a speed of a cell input to a duplex switching device. The overhead portion of the received SDH transmission frame has a speed adjusting cell insertion means for inserting a speed adjusting cell when the phase shift reaches a predetermined number of cells; Means for detecting cells for speed adjustment for detecting cells, means for clearly distinguishing between cells for speed adjustment and idle cells, and cells for speed adjustment from the system whose phase is delayed in the working system and the standby system. Or a cell for speed adjustment and an idle cell
2. The duplex processing apparatus according to claim 1, further comprising: a delay removing unit that removes a delay by using the delay processing unit. 4. A cell Nagaresen-option means when to switch to the backup system from the working, even if the active and standby systems is not established synchronization, the cells flow auxiliary system cell stream selection circuit selects system
The column value is the cell selected by the active cell flow selection circuit.
2. The duplex processing apparatus according to claim 1 , wherein the value is set to be the same as the value of the stream sequence . 5. When the division control means divides a transmission path cell stream into a plurality of parts and performs processing, the SDH processing unit reaches an overhead area of a received transmission frame equal to the number of cells corresponding to the number of switching circuits. 2. The dual processing apparatus according to claim 1, further comprising a speed adjusting cell insertion circuit for continuously inserting speed adjusting cells for the number of said switching circuits. 6. The same duplicated SDH from the opposite device
Upon receiving the frame, the SDH processing unit for extracting the bay load information excluding the overhead part of the SDH transmission frame in units of cells and generating the same active and standby cell flows, and generating the cell flow from the bay load information When the speed difference between the speed of the bay load information and the speed of the generated cell is superimposed, and when the difference reaches a predetermined number of cells, a speed adjustment cell for inserting a speed adjustment cell into the cell flow of both systems. and Le insertion means, a variable delay circuit for establishing synchronization absorbed by the rate adjusting cell phase difference of the working system cell stream and a standby system cell stream, separately from the variable delay circuit, a phase search for active and standby systems A phase measurement circuit for searching in advance for a phase difference to be absorbed by the variable delay circuit in order to suppress the fluctuation of the cell occurring at the time is provided.
A duplex switching device that switches from the working system to the standby system without interruption without causing cell duplication or the like, the duplex switching device comprising: a speed adjustment cell detection unit that detects a speed adjustment cell; Means for clearly distinguishing between the speed adjusting cell and the idle cell; and setting one of the working system and the standby system as a reference system, wherein the other system is connected to the speed adjusting cell inserted in the reference system. A speed adjustment cell shift absorbing means for adjusting the position of the speed adjustment cell, wherein the speed adjustment cell shift absorption means waits for the cell when adjusting to the system for adjusting the position of the speed adjustment cell. If the speed adjustment cell detection means detects a speed adjustment cell in the reference system, the memory of the other system that is not the reference is not read, and the speed of the reference system is not read. According to the position of the adjustment cell If a cell other than the speed adjustment cell is inserted into the non-reference system and a cell other than the speed adjustment cell is detected in the reference system, the cell is read from the memory and the speed adjustment cell is detected in the non-reference system. In the case where the cell for speed adjustment is not written to the memory, and a cell other than the cell for speed adjustment is inserted in a non-reference system,
A duplex processing device comprising a control unit for writing data to the memory. 7. The speed control cell control means, wherein the frequency of a speed control cell inserted into a non-reference system is abnormally high,
And if the frequency of the speed adjustment cells inserted into the reference system is abnormally low, a conversion control means for converting the speed adjustment cells of the non-reference system into idle cells; and 7. The duplex processing apparatus according to claim 6 , further comprising a writing control unit for performing writing. 8. The speed control cell control means may include an abnormally high frequency of a speed adjustment cell inserted into a reference system and an abnormally high frequency of a speed adjustment cell inserted into a non-reference system. 7. The method according to claim 6 , further comprising: reading control means for reading data from the memory when the speed is low, and conversion control means for converting a speed adjusting cell inserted into a reference system into an idle cell. Duplexing equipment.