JPH0823334A - No-hit switching method in duplicate transmission system and no-hit switching device - Google Patents

Abstract

PURPOSE:To switch standby system from/to an active system in no-hit by establishing the synchronization of the standby system and the active system in a short time and keeping the synchronization surely even after the synchronization is established. CONSTITUTION:Idle cell detection sections 104, 105 detect idle cells contained in the input from 0, 1 systems. A signal other than the detected idle cell is stored in memories 108, 120. The signal of the active system such as the system 0 to be stored is sequentially read and outputted via a selector 122. In this case, the idle cell detected by an idle cell insert section 115 is inserted to the same position. One cell is latched to either of cell buffers 112, 121 for that time, and a comparator section 111 detects a cell coincident with other read cell. When the coincidence is detected, the difference from the stored quantity in the memories 108, 120 is obtained and an idle cell counter is set as a delayed cell and the idle cell is inserted by an idle cell insert section 115. Then a selector 122 selects the system of the other system to switch to the system in no-hit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an uninterruptible switching method and an uninterruptible switching device in a duplex transmission system, and more particularly, for example, ATM (Broadband Digital Communication Service Network) ATM (elemental technology). The present invention relates to a non-instantaneous-interruption switching method and a non-instantaneous-interruption switching device in a duplicated transmission system used in a transmission system to which an asynchronous transfer mode) transmission method is applied.

[0002]

2. Description of the Related Art In a communication network such as a public communication network, its transmission device is required to have high reliability. For this reason, the main signal system is duplicated in the transmission line or in the main part in the device, and the redundancy is taken to improve the reliability. In such a transmission device, one system is usually used as an active system, and the signal is transmitted by switching to the other standby system for reasons such as wiring work of a transmission line or maintenance of the device. In this case, the transmission line is in operation because the user is actually communicating,
It is desirable to switch the system without interruption. Non-interruption means that there is no loss of signals, their order is guaranteed, and they do not overlap.In particular, asynchronous transfer mode (AT) in which signals are transmitted in packets called fixed-length cells
M) In the transmission method, it is desirable that loss of cell order, reversal, and double feeding of cells do not occur.

Conventionally, as a non-instantaneous interruption switching method in the above-mentioned duplex transmission apparatus, for example, the "ATM network non-existence method" described in IEICE Technical Report (Vol.92, No.287) is used. "Interruption Transmission Line Switching Method" or the 3rd 192 of the Proceedings of the Autumn Meeting of the Institute of Electronics, Information and Communication Engineers (1992) "Volume 3"
Several methods are listed in "Examination of non-instantaneous-duplex switching method in ATM transmission device" described on the page.

In the first method, switching cells for switching the system are simultaneously input to both the working system and the standby system, the switching timing is determined when the switching cells arrive, and the duplex transmission is performed without interruption. This is a switching cell timing method for switching paths. However, in this case, as described in both documents, the signal delay variation is concentrated at the time of switching the system, so that it is not advantageous as a non-instantaneous switching method compared to other devices.

The second method is a switching cell synchronization method in which switching cells are periodically input to both systems to establish synchronization of both systems and then the systems are switched without interruption.
In this case, the delay variation of the signal is gradually absorbed and switching is performed, which is superior to the first method. But,
This second method, like the first method, requires extra hardware for generation and detection of switching cells.

The third method is a cell sequence synchronization method in which user cells input to both systems are bit-compared to establish synchronization, and synchronization is always maintained and the system is switched without interruption. In this case, it is superior to the above two devices in that no switching cell is used, and in this respect, the second document mentions two more methods. One of them is a batch insertion method in which the phase difference between both systems is detected, and the phase difference is collectively inserted into the system that is proceeding after the phase difference is established to establish synchronization. However, this method has a drawback that the synchronized state cannot be maintained when the cell arrangements and cell flows of both systems differ due to empty cells or the like.

Therefore, as another method, when it is assumed that one of the systems is advanced and a delay is inserted in that system, cells that are synchronized in both systems are detected, and a cell that is synchronized cannot be detected. On the other hand, a sequential insertion method has been proposed which repeats this on the other hand to establish synchronization. In this case, there is an advantage that the synchronized state can be maintained even when the cell flow of the active system and the cell flow of the standby system are different, which is superior to the batch insertion method.

[0008]

However, in the above-mentioned conventional technique, it is assumed that the phase of one of the systems is advanced, and the delay is actually inserted in the system to search for a synchronizing cell. There was a problem that it took time to establish synchronization.

That is, for example, when the active system is delayed, if the search is performed assuming that the active system is advanced, the search is continued until the memory for the active system is full. However, in this case, no match is detected in the cells, and the search is restarted on the assumption that the backup system is proceeding again. However, since the delay has already been inserted in the active system, it is necessary to wait until this delay can be removed, that is, until the memory for the active system becomes empty. In order to empty the memory, empty cells of the memory capacity or more must arrive at the active system, but if the empty cells do not come easily due to traffic congestion, the memory becomes empty. Takes time,
As a result, the establishment of synchronization between both systems will also be delayed.
Therefore, when switching the system without interruption, there is a problem that it takes time to switch.

The present invention solves the above-mentioned drawbacks of the prior art, enables synchronization to be established in a short time using a user cell, and maintains the synchronization state even when the cell arrangement is different due to the insertion of an empty cell or the like. It is an object of the present invention to provide a non-interruption switching method and a non-interruption switching device in a duplex transmission device capable of switching the system to non-interruption without interruption.

[0011]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention selects and switches between at least two transmission systems, a working system and a standby system, depending on the situation. In the non-interruption switching method in the duplex transmission system for switching to non-interruption, an empty cell detection step of detecting an empty cell that does not contain information in the signals transmitted in each system, and an empty cell detection step are detected. The signal accumulation step of accumulating signals other than the empty cells for each system, the signal reading step of sequentially reading the signals accumulated in the accumulation step in each system, and latching either of the read signals Then, the synchronization establishment process that synchronizes the active system and the standby system while detecting the signal of the other system that matches the signal, and the synchronization of both systems is maintained after the signal synchronization is established in the synchronization establishment process. Sync maintainer And a signal switching step that performs system switching according to a system switching instruction by a system switching signal while maintaining synchronization in the synchronization maintaining step, and an empty signal output between the synchronization maintaining step and the signal switching step. It is characterized by including an empty cell detected in the cell detecting step and an empty cell inserting step of inserting an empty cell having a delay corresponding to the system proceeding in the synchronization establishing step.

In this case, in the synchronization establishing step, the signal of the working system is latched when the working system is advancing, the signal is compared with the signal from the protection system, and coincidence detection is executed. It is assumed that one of the systems is in progress in the process of establishing synchronization by latching the signal of the standby system while proceeding and comparing the signal with the signal from the active system to perform signal coincidence detection. Then, both processes may be repeatedly executed.

In addition, in the empty cell insertion step, when the signal coincidence detection is being executed in the synchronization establishment step, the empty cell from the empty cell detection step in the active system is inserted in the output to perform the synchronization establishment step. When a signal coincidence is detected as a result, an empty cell corresponding to the difference in the signal accumulation amount at that time may be inserted in the output.

On the other hand, the non-interruptible switching apparatus according to the present invention has at least two transmission systems, that is, a working system and a standby system, and selects and outputs a signal of any system according to the situation. In an uninterruptible switching device for switching the switching of the system to an uninterrupted system, an empty cell detecting means for detecting an empty cell containing no information among signals transmitted in each system, and an empty cell detecting means. Signal storage means for accumulating signals other than the empty cells detected in each system for each system, signal reading means for sequentially reading out the signals accumulated by the storage means in each system, and either of the read signals. A synchronization establishing means that synchronizes the working system and the standby system while detecting the signal of the other system that matches the signal, and a synchronization that maintains the synchronization of both systems after the signal synchronization is established. Maintaining means and system switching when maintaining synchronization Signal switching means for switching the system in accordance with the system switching instruction by the signal, and a signal output between the synchronization maintaining means and the signal switching means to proceed to the empty cell detected by the empty cell detecting means or the synchronization establishing means. An empty cell inserting means for inserting an empty cell with a delay corresponding to the number of lines in the open system.

In this case, the synchronization establishing means includes a first latch means for latching the spare system signal, a second latch means for latching the working system signal, and a comparing means for comparing these signals. Good.

Further, the empty cell inserting means counts the empty cells from the empty cell detecting means in the active system to the output when the synchronization establishing means is executing the signal coincidence detection, and the empty establishing means is used as the synchronization establishing means. It is preferable to have a counting means for setting the empty cell insertion amount by further counting the empty cells corresponding to the difference in the signal storage amounts at that time when the signal coincidence is detected.

Further, as the signal storage means, a dual port memory capable of simultaneously writing and reading signals is applied, and the write address generation means and the read address are individually controlled in accordance with the synchronization establishment process and after the synchronization establishment. And a generating unit.

The signal storage means may be a multiport memory having at least two or more inputs and outputs, respectively, and signals of two or more systems can be stored at the same time, and one of them can be used. It is advisable to read the data as the system and read the other data as the standby system.

[0019]

According to the non-interruption switching method and the non-interruption switching device in the duplex transmission system of the present invention, when the system is switched from the active system to any of the standby systems, the signals of the respective systems are empty without information. The signals are stored in the signal storage means excluding the cells, one of the signals read out in that order is latched, the signal is compared with the signal of the other system, and a matching signal is detected,
The synchronization of each system is established, and after that, the empty cells detected at the input and the empty cells for the delayed system are inserted and output. At this time, for example, when the active system is ahead of the standby system, the active system signal is output and latched, the latched signal and the standby system signal are compared, and a matching signal is detected. When a signal match is detected, the delay amount is calculated from the difference in the signal accumulation amount at that time,
The difference between the empty cells and the number of empty cells detected by the empty cell detecting means is inserted as a delay amount given to the output. If the backup system is advanced, the standby system signal is latched, the active system signal is output, and the latched standby system signal is compared to detect a matching signal, and the active system and the standby system are synchronized. Establish. An empty cell detected by the empty cell detecting means is inserted in the output current system signal to keep the input and output synchronized. After that, according to the system switching instruction by the system switching signal,
The system is switched from the active system to the standby system without interruption.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a hitless switching method and a hitless switching device in a duplex transmission system according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows an embodiment of a system switching device in a duplicated transmission system to which the non-interruptive switching method according to the present invention is applied. The transmission apparatus according to the present embodiment is, for example, an asynchronous transfer mode (ATM) transmission system signal,
It has two transmission lines, system 0 and system 1 for transmitting ATM cells formed into so-called fixed length signals, and either system is selected as the output of the active system by the system switching device shown in FIG. When the system is switched to another system during maintenance or construction of the device, the system is switched without interruption without interrupting the signal transmission by synchronizing the 0 system and the 1 system.

Specifically, the system switching device of the present embodiment has a compulsory switching signal input terminal 101 to which a compulsory switching signal is supplied from the main control unit of the transmission device when switching the system and a transmission line of the 0 system. 0-system input terminal 102 to which the transmitted ATM cell is supplied
And ATM cells transmitted through the 1-system transmission line are supplied 1
And a system input terminal 103. 0 system input terminal 102 has AT
Empty cell detection unit 104 for detecting empty cells included in M cells
And the 0-system memory 108 for accumulating ATM cells are connected. Similarly, the 1-system input terminal 103 is connected to the empty cell detection unit 105 and the 1-system memory 120, which are similar to those of the 0-system. Further, the switching signal input terminal 101 is connected to a switching control unit 113 that controls each unit to control synchronization and switching of the system.

The empty cell detection units 104 and 105 are empty cell detection circuits that monitor the ATM cells supplied from the 0-system or 1-system input terminals 102 and 103 and detect whether or not empty cells are included. When the switch is detected, the switching control unit 113
Send a detection signal to.

The switching control unit 113 includes empty cell detection units 104 and 105.
In response to the detection signal from the 0 system and 1 system memory 108,
Each ATM cell except the empty cell is stored in 120 and the synchronization establishment described later is controlled.

That is, the 0-system memory 1 and the 1-system memory 108 are connected to the write address generating units 106 and 107 and the read address generating units 109 and 110, respectively.
Generate each address according to the control from 113,
Accumulate and read ATM cells excluding empty cells. The write address generation units 106 and 107 have counters for generating addresses, and by resetting, starting and stopping the counters in accordance with instructions from the switching control unit 113, the input terminals 102 and 103 of the 0-system and 1-system are connected. An address is generated for recording the signal excluding the supplied empty cell in the memory. The read address generation units 109 and 110
Similarly, it has a counter for generating an address, and responds to an instruction from the switching control unit 113 to reset, start and stop the counter, and return the counter value by a designated value. An address for reading the target cell recorded in each memory 108, 120 of the 1-system is generated.

The 0-system and 1-system memories 108 and 120 are memory circuits formed by dual port memories capable of simultaneously performing writing and reading, respectively, and input at that time according to the addresses given to the input ports P1 and P2, respectively. The cells being written are written to the output ports P3, P
According to the address given in 4, the cell corresponding to that address is read. These 0-system and 1-system memories 10
The outputs of 8,120 are connected to the selector 122, the 0-system memory 108 is connected to the cell buffer 112 that latches the output, and similarly, the output of the 1-system memory 120 is connected to the cell buffer 121. .

The cell buffers 112 and 121 are latched ATMs.
It is a latch circuit that outputs a cell to the cell coincidence comparison unit 111. That is, the cell buffers 112 and 121 have the switching control unit 113.
0-system or 1-system memory 108, according to the mode instruction from
The mode is switched whether the output from the 120 is latched in that order and output sequentially, or one of the outputs from the 0-system or 1-system memories 108 and 120 is latched and repeatedly output. The comparing unit 111 compares the cells. Specifically, in the synchronization search process, if it is assumed that the phase of the 1st system is advanced, the cell buffer 121 latches the first passed cell among the signals output from the 1st system memory 120, and the 1st system is While the search is performed on the assumption that the cell is advancing, this initially latched cell is continuously output to the cell coincidence comparison unit 111, and other cells are not recorded. At this time, the cell buffer 112 sequentially latches the cells output from the 0-system memory 108 and passes the cells as they are,
The same signal as the signal given to the selector 122 is given to the cell coincidence comparison unit 111. When the synchronization search is started on the assumption that the phase of the 0-system is advanced, the reverse of the above procedure may be performed. In other words, the cell buffer 112 records the cell that has passed first in the signal output from the 0-system memory 108, and the cell that is recorded first is assumed during the search assuming that the 0-system is advanced. Match comparison unit 111
Output to the other cells, and other cells are not recorded. At this time, the cell buffer 121 passes the cell output from the 1-system memory 120 as it is, and supplies the cell coincidence comparing unit 111 with the same signal as the signal supplied to the selector 122.

The cell coincidence comparison unit 111 includes a cell buffer 112.
And output of cell buffer 121, that is, 0-system data (cell)
This is a synchronization detection circuit that compares the data (cell) of 1 system and 1 system and sends a match detection signal to the switching control unit 113 when a match is detected. At this time, there are the following methods for determining whether they match. (1) When all bits of the ATM cell are compared and they all match. (2) When all bits are compared and they match more than the preset number. (3) If the number of bits to be compared is small and they all match, either of these judgment methods can be applied.

The selector 122 is a 2-input / 1-output selection circuit, and is a 0-system memory according to an instruction from the switching control unit 113.
This is a switching circuit for switching the output from 108 and the output from the system 1 memory 120. In other words, is the active system 0 system or 1
A system selection signal is supplied from the switching control unit 113 depending on whether the system is a system, the output signal of the system 0 memory 108 is selected when the system 0 is the active system, and the system 1 signal is selected when the system 1 is the active system.
Select the output signal of 120 and use it as the output. When the system is switched, the system selection signal is also instructed, and when the system selection signal instructs to select a system different from the currently selected system, the output can be instantaneously switched at the cell break.

The output of this selector 122 is the empty cell insertion unit.
It is output from the output terminal 116 via 115. The empty cell inserting unit 115 inserts an empty cell when instructed by the empty cell counter 114, and outputs the output signal of the selector 122 to the active system output terminal 116 when there is no instruction.

The empty cell counter 114 has an active system output terminal 116.
Is a counter that counts the number of empty cells to be inserted by the empty cell insertion unit 115 into the output to, and is basically formed by a down counter, and is instructed by the switching control unit 113. The empty cell insertion number is decremented by one, and the empty cell insertion unit 115 is continuously instructed to insert the empty cell until the number becomes zero. Normally empty cell counter 11
The count value of 4 is 0, and the empty cell inserting unit 115 is not instructed to insert an empty cell. When an instruction to insert an empty cell is issued from the switching control unit 113, the count value is added by the instructed amount, and each time the instruction is given to the empty cell insertion unit 115, the count value is subtracted by one. . When the count value is other than 0, the empty cell insertion unit 115 always inserts an empty cell, and when the count value returns to 0, the empty cell insertion unit 115 stops the insertion of the empty cell and allows the output of the selector 112 to pass through. become.

The switching control unit 113 is a forced switching signal input terminal.
Forced switching signal supplied from 101 and empty cell detection unit 104,10
Receive the empty cell detection result of 0 system, 1 system input signal in 5 and the comparison result of 0 system, 1 system cell in the cell coincidence comparing unit 111,
Based on these information, the 0-system write address generation unit 106,
The write address generation control of the 1-system write address generation unit 107, the 0-system read address generation unit 109, the control of the read address generation of the 1-system read address generation unit 110, the mode control of the cell buffers 112 and 121, and the selector 12
The system selection control 2 and the instruction of the number of empty cells inserted into the empty cell counter 114 are performed.

Hereinafter, the non-instantaneous interruption switching method in this embodiment will be described based on the control of the switching control section 113. (1) Empty cell control When the phase of the active system is delayed (the standby system is advanced), the active system input signal will always be the active system output regardless of whether synchronization is established or not. .
However, since the empty cell is not recorded in the memory, it is necessary to insert the empty cell at the same position as the empty cell position at the time of input at the time of output. Therefore, the active system input is set to the empty cell detection unit 104,
The empty cell can be inserted at the same position by monitoring by 105 and counting up the empty cell counter 114 by 1 when an empty cell is input. When the phase of the active system is advanced, the active system input signal is used as it is as the active system output signal until synchronization is established, so empty cell processing is performed in the same way as when the phase is delayed, but after synchronization is established. Since the signal of the working system is output according to the input pattern of the signal of the delayed backup system, the empty cell counter 114 does not count up even if an empty cell is input to the working system. (2) Phase synchronization establishment control FIGS. 2 and 6 show flowcharts of the phase synchronization establishment method. In this figure, the 0 system is the active system and 1 is the precondition.
Suppose the system is a standby system. First, one cell is latched in the cell buffer 121 from the output signal of the first system memory (standby system memory) 120 (step S101). Next, the latched cell is read from the cell buffer 121 (step S102) and supplied to the cell coincidence comparison unit 111. Next, in the cell buffer 112, the output signals of the 0-system (active system) memory 108 are latched in the order of reading and sequentially supplied to the cell coincidence comparison unit 111. As a result, the cell coincidence comparing unit 111 compares the cells of both systems (step S103).

If a match is detected in step S103, the process proceeds to FIG. 6 and the 1-system (spare-system) read address generation unit 11
The address generated at 0 is returned by the number of cells stored in the spare memory 120 minus 1 (step S104), that is, the address is changed so as to indicate the stored address of the cell to be compared. As a result, the phases of the outputs of both systems are established, and thereafter, if there is a switching instruction, the active system and the standby system can be switched without any interruption.

Further, the fact that the match is detected in step S103 means that the standby system is ahead of the active system, and until the synchronization of steps S101 to S104 is established, that is, during the synchronization search process. Even after the synchronization is established, the signal supplied from the 0-system (active system) input terminal 102 is output to the output terminal 116 as it is. Further, thereafter, the following control is performed to maintain the phase synchronization state.

The empty cell detection unit 104 monitors whether or not an empty cell enters the input signal of the 0-system (working system) from the next cell where synchronization is established (step S105), and the empty cell comes in. In this case, the count up of the address counter generated by the 1-system (spare-system) read address generator 110 is stopped, the empty cell counter is incremented by 1 (step S106), and the process returns to step S105. As a result, the fluctuation of the phase (in this case, the phase difference increases) due to the entry of an empty cell into the active system having the delayed phase is absorbed.

Next, in step S105, when no empty cell is inserted in the 0-system (active system) input, the 1-system (standby system) read counter is started, and the 1-system (standby system) is sequentially read.
The signals of the first system (standby system) are read from the memory 120 (step S107). However, if the counter is already operating, it continues to count up.

The cell coincidence comparing unit 111 compares the read 1-system signal with the simultaneously-read 0-system signal,
It is confirmed whether the synchronization is out of sync (step S117). At this time, the cell buffers 112 and 121 pass the 0-system output signal and the 1-system output signal as they are. Then, when it is determined in step S117 that the synchronization is not out of sync (in the synchronized state), the process returns to step S105, and the operation for maintaining the phase synchronization is repeated. Step S117
If it is determined that the synchronization is out of sync, the process returns to step S101 in FIG. 2 to resynchronize again. Here, the judgment of out-of-synchronization refers to the case where the cell coincidence comparing unit 111 detects non-coincidence N times in succession, and the value of N is determined by the reliability required for the apparatus.

If no match is detected in step S103, it is confirmed whether or not the first system (standby system) memory is full (step S108). If not, step S1
Returning to 02, if it is FULL, it is determined that the active system is in progress rather than the standby system in progress, and all the contents of the standby system memory are discarded.

Then, one cell is latched in the cell buffer 112 from the output signal of the 0-system memory 108 (step S109). Next, the latched cell is transferred to the cell buffer 11
Read from 2 (step S110), cell match comparison unit 111
And the cell buffer 121 in the 1-system memory 12
The output signal of 0 is directly used as the input signal to the cell coincidence comparison unit 111, and the cells of both systems are compared by the cell coincidence comparison unit 111 (step S111).

If no match is detected in step S111, it is confirmed whether or not the active memory is FULL (step S112).
If so, it is determined that the active system is not advanced and the standby system is advanced, and all the contents of the active memory are discarded, and the process returns to step S101 and starts over.

If a match is detected in step S111, the process proceeds to FIG. 6 and the 0-system (active-system) read address generation unit
The address generated in 109 is returned by the number of cells stored in the active memory minus 1, that is, the address is changed to indicate the stored address of the cell to be compared, and the empty cell counter The 114 is instructed to count up by the difference in the number of cells stored in the memories of both systems (step S113).

As a result, the synchronism of the outputs of both systems is established, and after that, the switching between the active system and the standby system can be performed without any interruption whenever there is a switching instruction.

Further, the fact that the coincidence is detected in step S111 means that the active system is ahead of the standby system, so that the output to the output terminal 116 is performed in steps S101 to S111.
Until the synchronization is established (synchronization search process), the signal input from the 0-system (active system) input terminal 102 is output as it is. After the synchronization is established, the empty cell counter 114 is instructed at the moment when the synchronization is established. The empty cells are output by the set amount and the value of the empty cell counter is 0, that is, after the insertion of the empty cells is completed, the 0-system (active system) signal sequentially delayed is output.

After that, the following operation is performed to maintain the phase locked state. The empty cell detection unit 105 monitors whether or not there is an empty cell in the input signal of the 1st system (standby system) from the next cell for which synchronization has been established (step S114). The system (current system) read address generation unit 109 stops counting up the address counter and instructs the empty cell counter 114 to increment the count value by one (step
S115) and returns to step S114. This allows the output terminal 11
An empty cell is output to 6 and absorbs the fluctuation of the phase (in this case, the phase difference increases) due to the empty cell entering the standby system whose phase is delayed.

When no empty cell is inserted in the 1-system (standby system) input in step S114, the counter of the 0-system (active system) read address generating unit 109 is started to sequentially set the 0-system (active system). ) The 0-system signal is read from the memory 108 (S116). However, if the counter is already in operation, it continues to count up.

The 1-system signal read at the same time as the 0-system signal thus read is compared by the cell coincidence comparing section 111 to check whether the synchronization is lost (step S118). At this time, the cell buffers 112 and 121 pass the 0-system output signal and the 1-system output signal as they are. Then, if it is determined in step S118 that the synchronization is not out of sync (in the synchronized state), the process returns to step S114, and the operation for maintaining the phase synchronization is repeated. If it is determined in step S118 that the synchronization is lost, the process returns to step S101 to resynchronize again.

FIG. 3 and FIG. 4 show an example in which the operation is performed assuming signals actually input to the active system and the standby system. In these drawings, the vertical direction represents time t, and the horizontal method represents the state at that time t. When the active system is the 0 system and the standby system is the 1 system, the meaning of each element is as follows. Working system input ··· Time t from the 0 system input terminal 102
Input cell in standby system input: time t from input terminal 103 of system 1
Input cell in the active system memory content: Cell content stored in the 0 system memory 108 Spare system memory content: Cell content stored in the 1 system memory 120 Active system output:・ 0 system output of 0 system memory 108 standby system output ・ ・ ・ 1 system output of 1 system memory 120 active system buffer ・ ・ ・ ・ ・ ・ output of 0 system cell buffer 112 spare system buffer ・ ・ ・ ・ ・ ・ 1 system Output of the cell buffer 121 of the final output ... Output to the active system output terminal 116 Number of cells in current system memory Number of cells stored in 0 system memory 108 Number of cells in spare system memory Number of cells stored in system memory 120 Empty cell count number ... Count value of empty cell counter 114 (empty cell insertion number) First, refer to FIG. 3 for an operation example when the phase of the standby system is advanced. To explain, no matter which system is advanced,
First, the phase-locked search is started assuming that the backup system is advanced. At time t = 0, the active system input cell Y and the standby system input cell A are written in the active system memory and the standby system memory, respectively, and immediately read out as the active system output and the standby system output. Here, the output of the spare system is recorded in the cell buffer to search for the advance of the spare system (step S101), and the output Y of the cell buffer of the active system is compared with the output A of the cell buffer of the spare system (step S101). S103). At this time, the number of cells in the active system memory is 1, the number of cells in the standby system memory is 1, and the empty cell count value is 0. In this case, Y is output as the final output,
The cells do not match, so move to the next.

At time t = 1, the active system input is an empty cell,
The backup system input is an empty cell, and neither system writes anything to memory. At this time, in the spare memory, the cell A input at t = 0 is not deleted, and the active memory becomes empty. Therefore, the number of cells in the active system memory is 1, and since the active system input is an empty cell, the empty cell counter is incremented by 1 (empty cell count value is 1) and the empty cell is output as the final output.

At time t = 2, the active system input is cell Z,
The input of the spare system is the cell B, which is written in the memories of the active system and the spare system, respectively, and is immediately read as the output of the active system and the spare system. At this time, the spare memory stores the input cell B following the already written cell A. Next, cell A recorded at t = 0 in the spare cell buffer
And the output Z of the active system are compared (step S103). At this time, the number of cells in the active system memory is 1, the number of cells in the standby system memory is 2, and the empty cell count value is 0. Then, Z is output as the final output, and since the cells do not match, the process moves to the next.

At time t = 3, the active system input is an empty cell,
The backup system input is an empty cell, and the operation is the same as when t = 1. Therefore, the number of cells in the active system memory is 0, the number of cells in the standby system memory is 2 (cells A and B), and since the active system input is an empty cell, the empty cell counter is incremented by 1 (the empty cell count value is 1), an empty cell is output as the final output.

At time t = 4, the active system input is cell A,
The spare system input is an empty cell, cell A is stored in the active system memory and immediately read out, and the spare system empty cell is not stored. Next, the cell A recorded at t = 0 in the cell buffer of the standby system is compared with the output A of the active system (step
S103). At this time, the number of cells in the active system memory is 0, the number of cells in the standby system memory is 2, and the empty cell count value is 0. Then, A is output as the final output, and since the cells match, the spare system read address counter is returned by the number of cells in the spare system memory minus 1 (step S104). In other words, the contents are changed to show the stored address of the comparison target cell of the spare system, so that the contents of the cell indicated by the active read address (A) and the contents of the cell indicated by the spare read address are changed. (A) becomes the same and the phase synchronization of the cell is established.

At time t = 5, the active system input is an empty cell,
The spare system input is cell C, the empty cell of the working system is not stored, and cell C is stored at the end of the spare system memory, that is, after cell B. At this time, since the standby system memory has already established synchronization, cell A is read and cell B is at the top. Therefore, at this time, the number of cells in the active system memory is 0, the number of cells in the standby system memory is 2, and since the active system input is an empty cell, the standby system read address counter is stopped and the empty cell counter is counted by one. Up (step S106) The empty cell is output as the final output by setting the empty cell count value to 1. As a result, phase fluctuations due to the input of empty cells to the active system are absorbed.

At time t = 6, the active system input is cell B,
The spare input is an empty cell, cell B is written to the active memory and is immediately read as the active output, and the empty cell is not written to the spare memory. Then, since the active input is not an empty cell (step S105)
The standby system read address counter is restarted (step S107), and the cell B is output as the final output.

Since the same operation is repeated at times t = 7 to 10, its explanation is omitted. In this way, when the backup system is advanced, the standby system memory is used to adjust the phase for empty cells entering the active system, and the final output is the active system input as it is. Become.

Next, FIG. 4 shows an operation example when the active system is advanced. In this figure, the phase synchronization search is started on the assumption that the standby system is advanced, but the same cell cannot be detected even if the standby system memory becomes full, so the active system is advanced. Re-assume and start the search (step S108).

At time t = 0, the active system input cell A and the standby system input cell Y are written in the active system memory and the standby system memory, respectively, and immediately read out as the active system output and the standby system output. Here, the output of the active system is recorded in the cell buffer in order to search for the active system being advanced (step S109), and the output Y of the cell buffer of the standby system is compared with the output A of the cell buffer of the active system (step S109).
S111). At this time, the number of cells in the active system memory is 1, the number of cells in the standby system memory is 1, and the empty cell count value is 0. In this case, A is output as the final output, and since the cells do not match, the process moves to the next.

At time t = 1, the active system input is an empty cell,
The backup system input is an empty cell, and neither system writes anything to memory. At this time, in the active memory, the cell A input at t = 0 is not deleted, and the standby memory becomes empty. Therefore, the number of cells in the active system memory is 1, the number of cells in the standby system memory is 0, and since the active system input is an empty cell, the empty cell counter is incremented by 1 (empty cell count value is 1) and the final output is made. To output an empty cell.

At time t = 2, the active system input is cell B,
The input of the spare system is the cell Z, which is written in the memories of the active system and the standby system, respectively, and is immediately read as the output of the active system and the standby system. At this time, the active memory stores the input cell B following the already written cell A. Next, cell A recorded at t = 0 in the active cell buffer
And the output Z of the standby system are compared (step S111). At this time, the number of cells in the active system memory is 2, the number of cells in the standby system memory is 1, and the empty cell count value is 0. Then, B is output as the final output, and since the cells do not match, the process moves to the next.

At time t = 3, the active system input is an empty cell,
The backup system input is an empty cell, and the operation is the same as at time t = 1. Therefore, the number of cells in the active memory is 2 (cells A, B
), The number of cells in the spare system memory becomes 1, and since the current system input is an empty cell, the empty cell counter is incremented by 1 (empty cell count value is 1) and the empty cell is output as the final output.

At time t = 4, the active system input is an empty cell,
The spare system input is the cell A, the empty cell of the working system is not stored, and the cell A is stored in the spare system memory and is immediately read. Next, time t = 0 in the active cell buffer.
The cell A recorded in step S1 is compared with the output A of the backup system (step S111). Since the cells match here, the active read address counter is returned by the number of cells in the active memory minus one, and at this time, the number of cells in the active memory is 2,
Since the number of cells in the spare system memory is 0, the empty cell counter is counted up by the difference 1 (2-1) of the number of cells in the memory of both systems (step S113), and the empty cell count value is set to 1. Further, since the active system input is an empty cell, the empty cell count value is further incremented by one. After all, the empty cell count value here is 2. Here, by returning the current system read address counter value, it becomes possible to indicate the stored address of the cell to be compared with the current system, whereby the contents (A) of the cell indicated by the current system read address and , Contents of cell indicated by spare read address
(A) becomes the same and the phase synchronization of the cell is established. Then, as the final output, since the empty cell count value is 2, an empty cell is output.

At time t = 5, the active system input is cell C,
The spare input is an empty cell, cell C is stored at the end of the active memory, that is, after cell B, and the empty cell is not stored in the spare memory. At this time, since the active memory has already established synchronization, cell A is read and cell B is at the top. Therefore, the number of cells in the active system memory at this time is 2, the number of cells in the standby system memory is 0, and since the standby system input is an empty cell, the active system read address counter is stopped and the empty cell counter is counted by one. Up (step S115)
, The empty cell count value is 2 (it was 2 at time t = 4, but it is decremented (counted down) by 1 at time t = 5 to be 1, so it is counted up here. When it becomes 2), an empty cell is output as the final output. As a result, phase fluctuations due to the input of empty cells to the backup system are absorbed.

At time t = 6, the active system input is an empty cell,
The spare system input is the cell B, the empty cell is not written in the active system memory, and the cell B is written in the spare system memory and immediately read out as the spare system output. Then, since the backup system input is not an empty cell (step S114)
, The active read address counter is restarted (step S116). Here, although an empty cell is input to the active system, the active system is advanced and is in a synchronized state, so the empty cell counter does not count up.

Since the same operation is repeated from time t = 7 to 10, the description thereof is omitted. In this way, when the active system is advanced, the standby system memory is used to adjust the phase corresponding to the empty cells entering the standby system, and the final output is the input of the active system to the input of the standby system. Will be output according to.

When the above-described phase synchronization establishment method is used and the synchronization state is always maintained, that is, when the cell match signal is given from the cell match comparison unit 111, the switching signal supplied from the forced switching signal input terminal 101 is switched. Selector by signal
A system selection signal is output to 122, and the selector 122 changes the selection of the two input systems from the system used as the active system to the system used as the standby system. As a result, the system can be switched instantaneously without interruption. Further, before the synchronization is established by the phase synchronization establishing method described above, the cell discrepancy signal is given from the cell coincidence comparison unit 111, and switching cannot be performed during this period. Therefore, when the switching signal is input at this time, it is stored that the switching request has been made, and the system selection signal is sent to the selector 122 after the synchronization is established, that is, after the cell matching signal is given from the cell matching comparison unit 111. And switch.

As described above, according to this embodiment, the switching control unit 113 inserts an empty cell in the synchronous search process (the process of searching for the phase difference) when the active system is advanced. The search is not performed while inserting the delay in the active system, and after the synchronization search process is completed, the delay of the phase difference is given by inserting an empty cell to establish the synchronization, so that the The input of the active system is output as it is as the final output even during the synchronous search assuming that the phase is advanced. Therefore, even if there is no matching cell and the search is performed again assuming that the backup system is proceeding again, the search can be started immediately without waiting for the current system memory to become empty, and It has no effect on the output (final output). In other words, the input signal is directly output as it is until the synchronization is established, so that it has no effect on the active output. Also,
By providing the empty cell counter 114, the synchronization state can be maintained without any contradiction in the phase difference even when an empty cell is input during the synchronization search process, the delay insertion after the completion of the synchronization search, and the synchronization establishment. You can

Next, FIG. 5 shows another embodiment of the system switching device in the duplex system to which the non-interruptive switching method according to the present invention is applied. In the above embodiment, the 0-system cells and the 1-system cells are respectively stored in the dual port memories 108 and 120,
Although the selector 122 selects the final output, the multi-port memory 208 is used as a memory for commonly accumulating cells of the 0 system and the 1 system in the present embodiment, and the reading is performed by the active system. The difference from the above embodiment is that the final output is performed by controlling the address generation units 209 and 210 of the standby system.

More specifically, the multiport memory 208 in this embodiment is a two-input, two-output multiport memory and is capable of performing two-system writing and two-system reading simultaneously. The internal address space of the memory is divided into, for example, 0 system and 1 system. Therefore, the signal input from the 0-system input terminal 202 is recorded in the multi-port memory 208 from the 0-system port P1 according to the address signal generated by the 0-system write address generator 206. At this time, the 0-system input is monitored by the empty cell detection unit 204 as to whether or not an empty cell is included, and the empty cell is not recorded in the memory 208.

Similarly, the signal input from the 1-system input terminal 203 is recorded in the multi-port memory 208 from the 1-system input port P2 in accordance with the address signal generated by the 1-system write address generator 207. At this time, the empty cell of the 1-system input is detected by the empty cell detection unit 205, and the empty cell becomes 0.
Like the system, it is not recorded in the memory 208.

ATM recorded in the multiport memory 208
The signal of one system of the cell is the active system read address generator 20.
It is read from the active system output port P3 according to the address generated by 9 and supplied to the empty cell insertion unit 215 and the cell buffer 212. The ATM cell of the other system is read from the standby system output port P4 according to the address generated by the standby system read address generation unit 210 and supplied to the cell buffer 221.

The read address generation unit 209 in this embodiment,
Reference numeral 210 denotes a switching control unit 213, which has two counters each for generating a 0-system read address and a counter for generating a 1-system read address.
In order to read the target cell recorded in the multiport memory 208 by performing an operation such as resetting, starting, stopping, and returning the counter value by a designated value for the respective 0-system and 1-system counters in response to the instruction of Generates the address of. In this case, when the 0-system is the active system, the active-system read address generation unit 209 gives the counter value of the 0-system of the two counters to the multiport memory 208 as an address, and the standby system read-address generation unit 210 uses the two counters. Among them, the counter value for 1 system is given to the multiport memory 208 as an address. When the 1-system is the active system, conversely, the active-system read address generation unit 209 changes the value of the 1-system counter to
The standby system read address generation unit 210 gives the value of the 0 system counter as an address to the multiport memory 208.

The cell buffers 212 and 221 latch the output of the active system and the standby system of the multiport memory 208 in the same order according to the mode instruction from the switching control unit 213 and output the same, as in the above-described embodiment. One cell of the outputs from 208 is latched and repeatedly output, or the mode is set, and each cell is output to the cell coincidence comparison unit 211. That is, the operation differs depending on the mode instructed by the switching control unit 113, and in the synchronous search process, if it is assumed that the backup system is first in progress, the cell buffer 22
Of the signals output from the backup system output port P4 of the multi-port memory 208 at 1, the first output cell is recorded, and while the search is performed assuming that the backup system is in progress, The recorded cells are continuously output to the cell coincidence comparison unit 211, and other cells are not recorded. At this time, the cell buffer 21
2 allows the cells output from the active output port P3 of the multiport memory 208 to pass through without change, and the empty cell insertion unit 215
The same signal as the signal given to
Give to 211. Next, when the synchronous search is started on the assumption that the active system is in progress, the above procedure may be reversed. That is, the cell buffer 212 has a multiport memory.
Of the signals output from the active output port P3 of 208,
While the first passed cell is recorded and the search is performed on the assumption that the active system is advanced, the first recorded cell is continuously output to the cell coincidence comparison unit 211, and other cells are not recorded. At this time, the cell buffer 221 is a multiport memory.
The cell output from the backup system output port P4 of 208 is passed through as it is and given to the cell coincidence comparison unit 211. Then, in the phase locked state, the cell buffers 212 and 221 pass the output signals of the multi-port memory 208 as they are and give them to the cell coincidence comparison unit 211. Therefore, the difference of this embodiment from the above-mentioned embodiment is that the cell buffers 212 and 221 are
A constant input according to the 0 system input and the 1 system input is not given, and the active system output and the standby system output at that time are respectively latched regardless of the 0 system and the 1 system.

The cell coincidence comparison unit 211 compares the outputs of the cell buffers 212 and 221, that is, the data of the active system and the data of the standby system, as in the above embodiment, and the comparison result is the switching control unit.
Give to 213. The empty cell inserting unit 215 inserts an empty cell when there is an instruction from the empty cell counter 214 as in the above embodiment, and outputs the active output signal of the multiport memory 208 to the output terminal 216 when there is no instruction. To do.

As in the above embodiment, the switching control unit 213 determines the forced switching signal supplied from the forced switching signal input terminal 201 and the empty cell detection results of the 0-system and 1-system input signals in the empty cell detection units 204 and 205. And the comparison result of the cells of the active system and the spare system in the cell coincidence comparison unit 211, and based on these information, the 0 system write address generation unit 206, the 1 system write address generation unit
207 write address generation control, active read address generation unit 209, standby read address generation control of read address generation unit 210, and cell buffers 212, 22
The mode control of 1 and the instruction of the number of empty cells inserted into the empty cell counter 214 are performed. Switching control unit in the present embodiment
In 213, the empty cell control and the control for establishing phase synchronization are performed as shown in FIGS. 2 to 4 as in the above embodiment, and the switching control is performed as follows.

In the phase synchronization establishing method of FIG. 2, when the synchronization state is always maintained, that is, when the cell coincidence comparison section 211 gives the cell coincidence signal, the compulsory switching signal input terminal 201 inputs the signal. The system select signal is output to the active system and standby system address generators 209 and 210 according to the switching signal, and the output addresses of the multi port memory 208 are switched, so that the outputs of the output ports P3 and P4 of the multiport memory 208 are switched instantaneously, and the active system output terminals are output. Switch the system output to 216 without interruption.

Before the synchronization is established by the phase synchronization establishing method, the cell non-match signal is given from the cell matching comparison unit 211 to the switching control unit 113, and switching cannot be performed during this period. Therefore, at this time, terminal 201
If a switching signal is input to, record that there was a switching request, and after synchronization is established, that is, the cell match comparison unit
After the cell coincidence signal is given from 211, a system selection signal is given to each of the read address generation units 209 and 210 to perform switching.

As described above, according to this embodiment, the same effect as that of the above embodiment can be obtained, and since the selector is not used, the miniaturization of the device and the improvement of reliability can be expected.

In each of the above-mentioned embodiments, the inputs are two systems, that is, the 0 system and the 1 system, but in the present invention, there may be a plurality of systems, one of which is the active system and the other is the standby system. The configuration may be as follows.

Further, the present invention can be applied to the switching of the transmission path between the devices and also to the switching of the redundant components in the device. Further, it is applicable not only to the physical switching of the transmission path but also to the logical switching of the bus.

Further, in each of the above-described embodiments, the synchronous search is started on the assumption that the standby system is advanced first, but it may be started on the assumption that the active system is advanced first.

Further, although the cell buffer 221 is provided on the output side of the spare system in the second embodiment, this is omitted in the present invention, and the spare system read address generator 210 controls the multi-port memory 208 to save the spare system. Read out the cell
It may be directly supplied to the cell coincidence comparison unit 211.

Further, although each of the above embodiments has been described as a method using cells of the ATM transmission system, the present invention can be similarly applied to packet communication using fixed-length packets.

Furthermore, although each of the above embodiments has been described as a transmission device, the present invention is also applicable to a switching device having a redundant configuration due to duplication or the like, other communication devices, or an information processing device.

[0083]

As described above, according to the hitless switching method and the hitless switching device in the transmission system of the present invention, an empty cell is detected on the input side of the working system and the standby system, and the empty cell is removed. When signals are accumulated and the accumulated signals are sequentially read out, a synchronization search is performed without inserting a delay in the system in progress, and an empty cell detected at the input side and synchronization is established when the system is selected and output. Since it was configured to insert empty cells for the delay at the time of, the synchronous search can be performed assuming that one of the systems is advanced, and even if the assumption is redone, the reverse synchronous search can be performed immediately. It is possible, and at that time, the output of the working system is not affected. Therefore, the synchronization of both systems can be established in a short time. Also,
Even if a phase fluctuation occurs after the synchronization is established, an empty cell is inserted on the output side, which brings about an excellent effect that the synchronization state can be maintained regardless of the phase fluctuation.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a system switching device in a duplicated transmission device to which a method of switching without interruption according to the present invention is applied.

FIG. 2 is a flowchart showing a phase synchronization establishing method applied to the hitless switching method according to the embodiment of FIG.

FIG. 3 is a table showing signal states of respective parts when the hitless switching method according to the embodiment of FIG. 1 is applied, and is a diagram showing an example when the phase of the standby system is advanced.

FIG. 4 is a table showing a signal state of each part when the hitless switching method according to the embodiment of FIG. 1 is applied, and is a diagram showing an example when the phase of the active system is advanced.

FIG. 5 is a block diagram showing another embodiment of the system switching device in the duplicated transmission device to which the hitless switching method according to the present invention is applied.

FIG. 6 is a flowchart showing a continuation of the flowchart showing the phase synchronization establishing method of FIG. 2;

[Explanation of symbols]

 104,105,204,205 Empty cell detection unit 106,107,206,207 Write address generation unit 108,120,200 Memory 109,110,209,210 Read address generation unit 112,121,212,221 Cell buffer 111,211 Cell match comparison unit 113,213 Switching control unit 122 Selector 114,214 Empty cell counter 115,215 Empty cell insertion unit

Claims (8)

[Claims] 1. A non-instantaneous switching method in a duplexed transmission system in which, when at least two or more transmission systems of an active system and a standby system are selected and switched according to the situation, the switching is switched to a non-disruptive system. The method includes an empty cell detection step of detecting an empty cell that does not contain information among signals transmitted in each system, and a signal excluding the empty cell detected in the empty cell detection step for each system. A signal accumulating step of accumulating in the above, a signal reading step of sequentially reading out the signals accumulated in the accumulating step in each system, and latching either of the read signals and A synchronization establishing step for synchronizing the active system and the standby system while detecting a system signal; a synchronization maintaining step for maintaining the synchronization after signal synchronization is established in the synchronization establishing step; and a synchronization maintaining step. Stay in sync A signal switching step of executing a system switching in accordance with a system switching instruction by a system switching signal while holding, and a signal output during the synchronization maintaining step and the signal switching step is detected in the empty cell detecting step. And an empty cell inserting step of inserting an empty cell having a delay corresponding to the system proceeding in the synchronization establishing step, and a non-interruption switching method in a duplex transmission system. 2. The non-interruption switching method in the duplex transmission system according to claim 1, wherein the synchronization establishing step latches a signal of the working system while the working system is progressing, and the signal and the standby system. Match signal is detected by comparing with the signal from, and when the backup system is advancing, the signal of the standby system is latched, and the signal from the active system is compared and the signal is detected. A method for continuously switching without interruption in a duplex transmission system, characterized in that both processes are repeatedly executed assuming that one of the systems is in progress in the synchronization establishment process. 3. The non-interruption switching method in the duplexed transmission system according to claim 1, wherein the empty cell inserting step is used as an output when the signal coincidence detection is executed in the synchronization establishing step. An empty cell from the empty cell detection step in the system is inserted, and when a signal match is detected in the synchronization establishing step, an empty cell corresponding to the difference in the signal accumulation amount at that time is inserted into the output. A method for switching without interruption in a redundant transmission system. 4. A system having at least two transmission systems including a working system and a standby system, and switching between the systems without interruption when selecting and outputting a signal of any system according to the situation. In the non-instantaneous-interruption switching device for switching to, the device includes an empty cell detection unit that detects an empty cell that does not contain information in the signals transmitted in each system, and an empty cell detection unit that detects the empty cell. Signal accumulating means for accumulating signals other than cells for each system, signal reading means for sequentially reading the signals accumulated by the accumulating means in each system, and latching either of the read signals And a synchronization establishing means for synchronizing the working system and the standby system while detecting the signal of the other system that matches the signal, a synchronization maintaining means for maintaining the synchronization after the signal synchronization is established, and the synchronization maintaining means. In the state of maintaining synchronization by means Signal switching means for performing system switching according to a system switching instruction by a system switching signal, and an empty cell detected by the empty cell detecting means in the signal output between the synchronization maintaining means and the signal switching means, or A non-instantaneous-interruption switching device, comprising: an empty cell inserting means for inserting an empty cell having a delay corresponding to the amount of the system in progress in the synchronization establishing means. 5. The hitless switching device according to claim 4, wherein the synchronization establishing means latches a standby system signal and a second latching means latches a current system signal. And a non-instantaneous-interruption switching device having a comparing means for comparing these signals. 6. The non-interruption switching apparatus according to claim 4, wherein the empty cell inserting means outputs an empty cell in an active system to the output when the synchronization establishment means is performing signal coincidence detection. The empty cells from the cell detection means are counted, and when the synchronization establishment means detects a signal match, the empty cells corresponding to the difference in the signal accumulation amount at that time are further counted to set the empty cell insertion amount. A non-instantaneous-interruption switching device having a counting unit for 7. The hitless switching device according to claim 4, wherein the signal accumulating means is a dual port memory capable of simultaneously writing and reading a signal, and is individually provided in accordance with a synchronization establishment process and after synchronization establishment. A non-instantaneous-interruption switching device having write address generation means and read address generation means controlled by the above. 8. The hitless switching device according to claim 4, wherein the signal storage means is a multiport memory having at least two inputs and outputs, respectively.
A non-instantaneous switching device characterized in that signals of two or more systems are accumulated at the same time, one of them is read out as an active system, and the other is read out as a standby system.