JP3045144B2 - ATM switch - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an ATM switch.

[0002]

2. Description of the Related Art In an ATM exchange accommodating various traffics such as voice, image, data, etc., in order to satisfy different service qualities (delay, discard rate, etc.) required from various traffics, an upstream or downstream of a switch body. A buffer memory group for temporarily storing cell data is provided for each port of the switch.

This buffer memory group is prepared independently for each of a plurality of traffic types (hereinafter referred to as "service class"), and cells input to the buffer memory group are stored in a buffer memory corresponding to the service class. You.

The cells stored in the buffer memory for each of the plurality of service classes are stored in the buffer memory in such a manner that, for example, the service class that requires the least influence of delay is selected with absolute priority. Is output. Such scheduling control for adjusting the output cells from the buffer memory includes not only one that satisfies the service quality related to the delay as described above, but also various other controls.

[0005] On the other hand, in the above-described ATM exchange, in order to improve its reliability, the apparatus is often provided in duplicate. The active system that currently runs the service (hereinafter “active
An e-system) and a standby system (hereinafter, referred to as a "stand-by system") in which the current active system is replaced with the active system and service can be continued.

[0006] When some failure occurs in the active system and the service becomes unavailable, or when there is an instruction from the exchange control terminal, the current active system becomes a new stand-by system and the current stand-by system. Becomes a new active system is called system switching.

FIG. 9 is a diagram for explaining a conventional communication system switching method for a duplex switching device.

[0008] The input selection device 90 distributes a cell input from the line side to a currently active communication channel,
At the same time that the system of the communication path is switched, a new active
Switch so that cells are transmitted to the system channel.

The storage memory device 91 has a plurality of cell buffers for each service class, temporarily stores input cells from the input selection device 90, and preferentially reads out cells of a service class having a high delay priority. .

The cell multiplexing device 92 multiplexes cells from the storage memory devices 91 of both systems and outputs the multiplexed cells to the line side.

On the side that becomes the old active system at the time of system switching, the system switching control device 93 monitors the cell accumulation state of the old active storage memory device 91 and indicates an empty signal indicating that all cells have been output. Is notified to the new active system switching control device,
Cell output from the new active storage memory device is permitted. Also, on the side that becomes the new active system at the time of system switching, at the start of system switching, it instructs the storage memory device of the new active system to stop reading all cells, and thereafter receives an empty signal from the old active system. Then, cell reading is permitted.

[0012]

However, such a conventional technique has the following problems.

[0013] The first problem is that the service class delay quality is degraded at the time of switching the communication path system.

The reason is that at the start of the switching of the communication channel system, a plurality of cells of different service classes are stored in the storage memory device of the old active system, and the plurality of services are continuously transferred to the new active system thereafter. When cells of the class are flowing in, the new active memory is output until all cells in the old active storage memory device are output.
Only cells are stored in the ve storage memory device.
This is because they cannot be output.

A second problem is that the switching of the communication channel system cannot be reliably completed within a certain period of time.

The reason for this is that, in order to prevent cell loss at the time of switching of the communication channel system, system switching is not completed until all cells staying in the old active system are output. The time spent for system switching is based on the old acti
It becomes longer in proportion to the accumulated amount of cells staying in the ve system.

The present invention provides a method and a method for switching a communication path which do not degrade the delay quality of a service class at the time of switching the communication path and can surely complete the switching of the communication path within a predetermined time. A using a system switching device
It is intended to provide a TM exchange.

[0018]

SUMMARY OF THE INVENTION A communication path switching method and a communication path switching circuit according to the present invention guarantee the delay quality of real-time traffic by switching links for each service class when switching a communication path. It is.

Further, the communication path switching method and the communication path switching circuit according to the present invention measure the time by a timer, and when the first time elapses before the completion of the system switching, a service for guaranteeing a low discard rate thereafter. By completing the system switching operation when only the class has completed the link switching, a delay in the system switching operation due to traffic that does not need to guarantee a low discard rate is prevented. When the second time has elapsed before the completion of the system switching, the system switching operation is forcibly completed, so that the system switching time can be completed within a predetermined time.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic block diagram of an embodiment of an ATM switch according to the present invention.

Referring to FIG. 1, an ATM according to the present embodiment is shown.
The exchange includes an input selection device 10 for outputting input cells from the line to the active system, a storage memory device 11 for temporarily storing input cells from the input selection device 10 and outputting the stored cells, and system switching. Occasionally, the system switching control device 12 that monitors the residual cell amount of the storage memory devices 11 of the own system and the other system, outputs a system switching completion signal, and the cells from the storage memory device 12 are multiplexed and transmitted to the line side. The system includes a cell multiplexing device 13 and a system determining device 14 having a master function of a control bus for determining the current system and instructing each device to the system, and performing initial setting of each device.

The input select device 10 transmits the input cell data from the line side to the one indicated as 'active' among the system instruction signals 110 output from the system determination devices 14 of both systems.

Hereinafter, a system that has been a stand-by system and has become a new active system will be referred to as a “new active system”.
System, and it is an active system until now
The system that has become an and-by system is referred to as "old active system".

In FIG. 1, when a system switchover occurs, cells are output from the old active storage memory device 11 in the order of delay high priority, and when a cell of a certain service class becomes empty, it passes through the system switchover control device 12. Then, output is permitted to cells of the same service class in the storage memory device 11 of the new active system.

The system switching control device 12 of the old active system
Detects that all cells in its own storage memory device 11 have been output within a predetermined first timer value, and notifies completion of system switching.

If the first timer value is exceeded during the system switching operation, the system switching control device 12 switches the system switching at the time when all cells of a specific service class are output according to a predetermined discard priority bit. The completion is notified, and output permission is given to all service classes in the storage memory device of the new active system.

If the first timer value is exceeded and the second timer value is reached during the system switching operation, the system switching control device 12 immediately notifies the completion of system switching and issues a new acti.
Output permission is given to all service classes in the ve system storage memory device.

FIG. 2 shows the storage memory device 11 shown in FIG.
FIG. 3 is a block diagram illustrating a configuration example of FIG.

In FIG. 2, reference numeral 20 denotes a write selection unit;
10-21n are cell buffers for each service class, 2
Reference numeral 2 denotes a read selection unit, 120 to 12n are empty signals indicating whether each cell buffer is 'empty' or 'not empty', 130 to 13n are stop signals indicating 'transmission stop' or 'transmission enabled', 160 Is 'receivable'
Or a receive not ready signal (hereinafter referred to as an “RNR signal”) indicating whether or not “reception is impossible”, and 230 to 23n are output permission signals indicating whether or not “output permission”.

The write selection unit 20 receives an input cell (ATM)
Referring to the identifier 31 added to the cell 30) (FIG. 3)
), Select which of the cell buffers 210 to 21n independently provided for each service class to write to, and write the input cells to the desired cell buffer.

Each cell buffer 210-21n has one cell.
In the state where more than one is written, the empty signals 120-1
2n as 'not empty'
And the system switching control device 12 is notified. If the cell is 1
Empty signal 1 when no data is written
20 to 12n are notified as 'empty'.

The read selection unit 22 is provided for the cell multiplexer 13.
Only when the RNR signal 160 from the system switch indicates “receivable”, the stop signals 130 to 1 from the system switching control device 12
Among the cell buffers of the service class in which one or more cells are stored among the cell buffers of the service class in which 3n indicates "transmittable", the output permission signals 230 to 23n are sent to the cell buffer of the service class having the highest delay priority. 'Output allowed'
Give as.

The cell buffer that has received the output permission signals 230 to 23n outputs the cell that has been written to the cell buffer the earliest. If the RNR signal 160 indicates “unreceivable”, no output permission is given to any cell buffer. Even when the RNR signal 160 indicates "receivable", output permission is not given to the cell buffer in which the stop signals 130 to 13n indicate "transmission stop".

FIG. 4 shows the system switching control device 1 shown in FIG.
2 is a block diagram illustrating an example of the internal configuration of FIG.

In FIG. 4, reference numeral 40 denotes a timer circuit;
Is a system switching control circuit, and 42 is a discard priority register.

Reference numeral 110 denotes a system instruction signal indicating 'active' or 'stand-by';
n is another system empty signal for notifying the other system switching control device, 150 is a system switching completion signal for notifying system switching completion, and 170 is a control bus used as a means for receiving initial setting from the system determination device 14. is there.

In the timer circuit 40, two timer values can be set at the time of initial setting. Further, the timer circuit 40
Has a counter which is set to '0' at the time of initial setting, and the system instruction signal 110 is changed from 'active' to 'st'.
and-by '. That is, when the system switching starts, the counting operation is started, and thereafter, when the system switching completion signal 150 indicates the completion of the system switching, the counter is returned to '0' and the counting operation is stopped. During the counting operation, when the counter value exceeds the first timer value set at the time of the initial setting, the first timeout signal 430 is output. Similarly, when the second timer value is exceeded, a second timeout signal 440 is transmitted.

The system switching control circuit 41 is connected to the system instruction signal 11
When “0” changes from “active” to “stand-by”, the empty signal 12 from the storage memory device 11 is output.
0-12n, referring to the first timeout signal 430, the second timeout signal 440 from the timer circuit 40, and the discard priority bit of the discard priority register 42 to generate the other system empty signals 140-14n and the system switching completion signal 150, Output.

When the system instruction signal 110 is set to 'stand-
When "by" changes to "active", the other system empty signals 140 to 14n received from the other system change to the stop signal 13 corresponding to the service class indicating "empty".
0 to 13n are output as "sendable", and the stop signals 130 to 13n of the classes in which the other system empty signals 140 to 14n indicate "not empty" are output as "sending stop".

The discard priority register 42 is a register as shown in FIG. 5, and has one discard priority bit 50 to 5n for each service class. The discard priority bits 50 to 5n are set by the system determination device 14 through the control bus 170 at the time of initialization.

FIG. 6 is a block diagram showing an example of the internal configuration of the cell multiplexer 13 shown in FIG.

In FIG. 6, reference numeral 60 denotes First in
A first out memory (hereinafter, referred to as “FIFO memory”), 61 is a FIFO control unit, 62 is a multiplexing unit, 63 is a write enable signal, and 64 is a read enable signal.

The FIFO memory 60 includes a FIFO controller 6
According to the instruction 1, the writing and reading of the received cell from the storage memory device 11 are performed. When the number of write cells exceeds a certain amount, an RNR signal 160 is output.

The FIFO control unit 61 receives the system instruction signals 110 and the system switching completion signal 150 of both systems, and usually, the FIFO of the system in which the system instruction signal 110 indicates “active”.
Write permission and read permission are given only to the FO memory 60. F in which the system instruction signal indicates 'stand-by'
Since no write permission is given to the IFO memory, the received cell is discarded. Also, one of the system instruction signals 110
Is changed from 'active' to 'stand-by' and until the system switching completion signal 150 is received, write permission and read permission are given to the FIFO memories 60 of both systems. However, when cells are written in the FIFO memories 60 of both systems, read permission is given only to the new active system.

The multiplexing section 62 multiplexes the output cells from the FIFO memories 60 of both systems and outputs the multiplexed cells to the line section.

The system determination device 14 shown in FIG. 1 shows a system instruction signal 110 indicating the current system and indicating a trigger for system switching.
Is output. In the present embodiment, for simplicity of description, two system instruction signals 110 are simultaneously set to “active”.
Or “stand-by” is not indicated, and one of the system instruction signals 110 is changed from “active” to “sta-by”.
nd-by ', the other system instruction signal 11
It is assumed that 0 changes from 'stand-by' to 'active'. Further, the system determination device 14 controls the control bus 1
It has 70 master functions and can perform initial setting of each device.

Next, the operation of this embodiment will be described in detail.

First, as a prerequisite for simplifying the explanation, the priority of service classes 0 to n is assumed to be highest for service class 0 and lowest for n.
At the time of the initial setting, the timer circuit 40 supplies the first timer value for the first timeout signal 430 and the second timer value for the second timeout signal 440 (the first timer value < (Second timer value), and set “1” to the discard priority bits 50 to 5n in FIG. 5 only for the service class n, and set “0” to all others.

In FIG. 1, an input cell from the line side is:
The input instruction device 10 transmits the system instruction signal 110 to the system indicating “active” (upper side in FIG. 1),
The data is output from the cell multiplexing device 13 to the line side via the storage memory device 11.

All the cell buffers 2 for each service class in the storage memory device 11 which is currently active
In a state where one or more cells are stored in 10 to 21n, the active system instruction signal 110 is set to 'active'.
When the input cell changes from “e” to “stand-by”, the input selecting device 10 immediately replaces the subsequent input cell with ac.
The transmission to the system that has become the active system, that is, the new active system (the lower system in FIG. 1) is started.

At this time, the system switching control device 1 on the system newly changed to the stand-by system, that is, the old active system side
2 activates the counter of the timer circuit 40. In addition, another system empty signal 14 for the new active system.
0 to 14n are all output as 'not empty'.

This is because the other system empty signals 140 to 14
This is because n is generated based on empty signals 120 to 12n from the storage memory device 11 as shown in FIG. Cell buffer 210
To 21n, the empty signal 1
This is because 20 to 12n are 'not empty'.

FIG. 7 shows the system switching control device 1 shown in FIG.
FIG. 14 is a block diagram of an example of a configuration related to generation of the other-system empty signals 140 to 14n in FIG.

In FIG. 7, a is an AND circuit, and b is
Is an OR circuit. The system switching completion signal 150 is "1" to indicate system switching completion, and the empty signals 120 to
The 12n and other system empty signals 140 to 14n are '1' indicating 'empty'.

FIG. 7 shows that if the empty signal of a certain class among the empty signals 120 to 12n of each service class is “empty” and all the classes having higher priorities than that class are “empty”, The other system empty signals 140 to 14n of the class are set to 'empty'.
And can be done.

When the system switching completion signal 150 is notified, all other system empty signals 140 to
14n is also shown as 'empty'.

System switching control device 12 for new active system
Receives all the empty signals 140 to 14 n of all classes from the old active system are “not empty”, and sends all the stop signals 130 to 13 n to the storage memory device 11 of the own system as “stop sending”. Notify as.

The above is the operation immediately after the start of the system switching.

Thereafter, the cell buffer 2 having the highest service class is transmitted from the old active storage memory device 11.
The cells sequentially read from the line 10 and newly input from the line side are stored in the storage memory device 11 of the new active system.

When all cells have been read, the cell buffer 210 in the old active storage memory device 11 outputs the empty signal 120 of the corresponding service class as 'empty'. Upon receiving this, the system switching control device 12 outputs the other system empty signal 140 of the service class as 'empty'. Upon receiving this, the new active system switching control device 12 sets the stop signal 130 of the corresponding service class to “transmittable”.

New active storage memory device 11
Is the service class 0 for which the stop signal has become 'transmittable'
From the cell buffer 210 is started.

By this operation, it is possible to sequentially output cells from the service class that became empty in the old active storage memory device 11 from the new active storage memory device 11.

According to FIG. 7, regardless of the state of cell storage in the old active storage memory device 11 at the start of the system switchover, the new active system always transmits from the class having the higher delay priority. Is allowed.

On the other hand, the cell multiplexer 13 can write the input cells from both the systems into the FIFO memory 60 after the system switching is started.

As described above, the storage memory devices 11 of both systems
When a cell output is generated from the memory and the cell is written into the FIFO memories 60 of both systems, the FIFO of the new active system is used.
The cell is read from the O memory 60. The old active type FIFO memory 60 cannot read data due to the inflow of cells from the new active type and may stay in the FIFO memory 60. When the cells accumulate to a certain amount, the RNR signal 160 is transmitted. Storage memory device 1
It is possible to stop reading cells from one.

By this operation, the traffic of the service class with a high priority output from the new active system is
The transmission can be performed without being disturbed by the traffic of the low priority service class from the old active system.

In the old active system, all cells in the storage memory device 11 are output before the first timeout signal 430 is output from the timer circuit 40, and the empty signals 120 to 12 for each service class are output.
When all of n have become 'empty', the system switching completion signal 150 is output. In response, the timer circuit 4
0 stops the counting operation, and the cell multiplexer 13 sets the new a
Only the cells from the active system are written into the FIFO memory 60. This completes a series of system switching operations without losing data.

In the old active system, when the first timeout signal 430 is output from the timer circuit 40 in a state where cells are accumulated in the storage memory device 11, the discard priority shown in FIG. Bits 50-5
When all of the empty signals 120 to 12n of the service class for which n is set to '0' become 'empty', the system switching completion signal 150 is output. In response to this, the timer circuit 40 stops the counting operation, all the other system empty signals 140 to 14n for each service class become “empty”, and from the new active system, all the cell buffers 210 to 21 for each service class are transmitted.
n, the cell multiplexing device 13 reads the new a
Only the cells from the active system are written into the FIFO memory 60. This completes a series of system switching operations.

At this time, if the cells are stored in the cell buffers 210 to 21 n in the old active storage memory device 11 in which the discard priority bits 50 to 5 n are set to “1”, those cells are stored. After the cell is read from the storage memory device 11, the FIFO of the cell multiplexer 13 is read.
It is discarded by the receiving unit of the memory 60.

Further, after the first timeout signal 430 is output from the timer circuit 40, the discard priority bit 50
5n is an empty signal 12 of a service class of '0'
If the second timeout signal 440 is output before all of 0 to 12n become “empty”, the system switching completion signal 150 is output immediately. At this time, the old acti
All the cells stored in the ve system are discarded by the receiving unit of the FIFO memory 60 as described above.

FIG. 8 shows the system switching control device 1 shown in FIG.
2 is a block diagram of an example of a configuration related to generation of a system switching completion signal 150 in FIG.

In FIG. 8, a is an AND circuit and b
Is an OR circuit. The system switching completion signal 150 is "1" to indicate system switching completion, and the empty signals 120 to
12n is '1' indicating 'empty', and the first timeout signal 430 and the second timeout signal 440 are '1' indicating timeout (timer value exceeded).

[0074]

A first effect of the present invention is that the delay quality of the service class whose delay is to be reduced can be maintained even during the switching operation of the communication path.

The reason is that at the time of the system switching operation, the communication path is sequentially switched for each class from the service class having the highest delay priority.

A second effect is that the communication path switching operation can be completed within a fixed time.

The third effect is that the new ac
That is, it is possible to prevent overflow of the buffer memory of the active system.

The second and third effects are produced by using a timer and a discard priority register at the time of system switching, so that after the time of the first timer is exceeded, the request for the discard quality is low. The system switching can be completed even if the cell of the service class is discarded. Further, when the second timer expires, the cell of any service class can be discarded immediately. This is because system switching can be completed.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of an embodiment of an ATM switch according to the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a storage memory device illustrated in FIG. 1;

FIG. 3 is a diagram showing an identifier added to an ATM cell.

FIG. 4 is a block diagram illustrating an example of an internal configuration of the system switching control device illustrated in FIG. 1;

FIG. 5 is a diagram illustrating a configuration of a discard priority register.

FIG. 6 is a block diagram illustrating an example of an internal configuration of the cell multiplexer illustrated in FIG. 1;

FIG. 7 is a block diagram of an example of a configuration related to generation of another system empty signal in the system switching control device shown in FIG. 1;

8 is a block diagram illustrating an example of a configuration related to generation of a system switching completion signal in the system switching control device illustrated in FIG. 1;

FIG. 9 is a diagram for explaining a conventional method of switching a communication channel of a duplex switching device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Input selection device 11 Storage memory device 12 System switching control device 13 Cell multiplexing device 14 System determination device 20 Write selection part 210-21n Cell buffer 22 Read selection part 40 Timer circuit 41 System switching control circuit 42 Discard priority register 60 FIFO 61 FIFO Control unit 62 Multiplexing unit

Continuation of front page (56) References JP-A-10-190683 (JP, A) JP-A-11-261598 (JP, A) JP-A-6-315033 (JP, A) JP-A-11-27280 (JP, A) , A) JP-A-4-222141 (JP, A) JP-A-10-65686 (JP, A) 1997 IEICE General Conference B-7-120 IEICE Technical Report IN89-70 (58) Fields surveyed (Int .Cl. ⁷ , DB name) H04L 12/56 H04L 12/28

Claims (7)

(57) [Claims] 1. An ATM exchange having a multiplexed communication path system, wherein a link is switched for each service class when the communication path system is switched. 2. A communication path switching method for switching a multiplexed communication path, wherein a link is switched for each service class when the communication path is switched. 3. A communication path switching apparatus for switching a communication path system having a multiplex configuration, wherein a link is switched for each service class when the communication path is switched. 4. In an ATM switch having a dual communication path system, a low discard rate is guaranteed if a first predetermined time elapses before the completion of system switching when the communication path system is switched. A is characterized in that the system switching operation is completed when only the service class has completed the link switching, and cells of traffic for which a low drop rate does not need to be guaranteed are discarded.
TM exchange. 5. In an ATM switch having a dual communication path system, when a second predetermined time elapses before completion of system switching when the communication path system is switched, the system switching operation is forcibly performed. Wherein the cell which has not been switched at this time is discarded. 6. A method according to claim 1, further comprising the steps of: switching a communication path system having a dual configuration; when switching the communication path system, if a first predetermined time elapses before completion of system switching, a low discard rate; A communication path switching method characterized in that the system switching operation is completed when only the service class that guarantees the switching has completed the link switching, and the traffic cells for which a low drop rate does not need to be guaranteed are discarded. 7. A communication path switching method for switching a dual communication path system, wherein when the communication path system is switched, if a second predetermined time elapses before the completion of the system switching, the communication is forcibly performed. A communication path switching method, wherein the system switching operation is completed, and cells for which link switching has not been completed at this time are discarded.