JPH09331105A - Semiconductor light emitting device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a semiconductor light emitting device which is high in reliability and capable of operating on a low voltage even if a light emitting layer is formed of semiconductor possessed of a wide band gap by a method wherein an element which serves as the parent material of a first semiconductor layer and an element which serves as the parent materials of a second and a third semiconductor layers are set to belong to different groups in the periodic table of elements respectively. SOLUTION: A buffer layer 12, an N-type band carrier relaxtion layer 34, and an N-type interface stabilizing layer 16 are grown on a first N-GaAs substrate 11. Then, an N-ZnSe layer 17, an N-ZNSSe layer 18, an N-type clad layer 19, a light confinement layer 20, a quantum well active layer 36, a light confinement layer 24, a P-type clad layer 25, a P-ZnSSe layer 26, and a P-ZnSe layer 27 are formed on the substrate 11. A buffer layer 39, an etching stop layer 38, a contact layer 32, and an interface stabilizing layer 28 are grown on a P-GaAs substrate 40 the same as above, and then a P-ZnSe layer 27 is formed on the second substrate 40. An Se stabilizing plane 42 and a Zn stabilizing plane 43 of the P-ZnZe layer 27 are directly bonded 41 mechanically.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light emitting device and a method for manufacturing the same, and more particularly to a semiconductor light emitting device having a high reliability and a low voltage operation, which has a novel structure and manufacturing method.

[0002]

2. Description of the Related Art In recent years, optical discs have been suddenly highlighted as recording and storage media for video information and data. A semiconductor laser is used for reading information from an optical disk and writing information to the optical disk. Since the storage capacity of the optical disk increases in inverse proportion to the square of the wavelength of the laser light, shortening the wavelength of the semiconductor laser is extremely significant in improving the storage capacity of the optical disk. From this point of view, there is a strong demand for a laser in the green range and further in the blue range rather than the conventional red range.

If semiconductor lasers of three primary colors of red, green and blue are prepared, various optical devices such as display devices and full color printers will be developed and their performances will be improved. Under such a background, research and development of a next-generation blue-green light emitting device using a II-VI group compound semiconductor and a nitride-based III-V group compound semiconductor has been actively conducted.

[0004] As an example thereof, Japanese-made
Null of Applied Physics, Volume 33, 9
Page 38 "ZnCdSe with GaAs buffer layer.
/ ZnSSe / ZnMgSSe SCH laser diode ", group II-VI semiconductor laser diode (L
There is a report of room temperature laser oscillation of D). The oscillation wavelength of this LD is 509 nm. FIG. 9 shows the layer structure of the LD. This is an example in which the efficiency of confining electrons and holes in the active layer is increased by using a wide gear gab material containing Mg for the cladding layer, and the characteristics of the II-VI semiconductor LD are improved.

However, the conventional II-VI group semiconductor L
D has some problems. Among them, the problem of ohmic contact is important. In general III-V group compound semiconductors, methods for realizing ohmic contact such as alloying of metal alloy electrodes, alloying by high heat treatment, and high-concentration doping of semiconductor contact layers have been established. However, the II-VI compound semiconductor is
Due to the characteristics such as weakness to high heat of 300 ° C. or higher, high concentration doping is difficult, and large band gap, the current green-blue light emitting device using the II-VI group semiconductor is
It is not easy to realize the ohmic contact of the p-electrode. If the ohmic contact cannot be obtained, the Schottky barrier at the metal / semiconductor interface may cause no current to flow in the element in contact with the element, or the element may deteriorate due to an increase in the driving voltage of the element.

In the conventional LD, in order to solve these problems, a ZnTe layer and a ZnSe / ZnTe superlattice layer are used as a contact layer of the LD. Zn
Since the Te layer is a material capable of high-concentration p-doping, ohmic contact can be realized by using the p-type ZnTe layer as the contact layer. Further, the ZnSe / ZnTe superlattice layer has an effect of eliminating energy discontinuity (about 0.8 eV) in a large valence band between the ZnTe layer and the ZnSe layer. As a result, the operating voltage is reduced to about 5V, and M
Blue LD associated with the development of wide-gap materials containing g
Room temperature oscillation was realized.

However, the contact layer ZnT
The lattice constant difference between the e-layer and the GaAs substrate is about 8% of the lattice constant of the GaAs substrate, and ZnTe is basically GaA.
ZnTe because it is difficult to grow lattice-matched to the substrate
There is a problem with crystal quality. Further, since the ZnSe / ZnTe superlattice layer has a voltage drop of at least 1 eV or more, the ZnSe / ZnTe superlattice layer deteriorates during the room temperature continuous oscillation operation of the LD, and the operating voltage increases, which further accelerates the deterioration. There is a problem. Further, in order to form the p-side electrode on the ZnTe contact layer, it is necessary to vapor-deposit an electrode material on the wafer and heat-alloy it. However, such an electrode forming process is performed by sublimation of group VI elements or growth of dislocations due to high temperature. There is a problem of causing deterioration of the superlattice layer.

In order to realize the low voltage operation of the LD, in addition to reducing the contact resistance of the metal electrode, a large band discontinuity between the valence band of the GaAs substrate and the II-VI semiconductor layer is created. Need to be relaxed. For this problem, there is a proposal to insert a band barrier buffer layer such as GaInP or AlInP. However, it is difficult to grow a III-V semiconductor on ZnSe due to the difference in growth temperature between the two. For example, on page 272 of Proceedings of the 56th Annual Meeting of the Society of Applied Physics, Autumn 1995, “ZnS
There is a report entitled "Gas source MBE growth of p-type InAlP of barrier relaxation layer using e / GaAs".

In that report, it is attempted to insert a GaAs layer between the ZnSe layer and the InAlP layer to prevent facet growth of InAlP. Although the carrier concentration of Be-doped p-type InAlP grown on ZnSe is slightly improved, it is still in the order of 10 ¹⁴ cm ⁻³ ,
It does not reach the level that can be used for the contact layer of LD.

That is, a semiconductor light emitting device having a structure in which a II-VI group semiconductor layer is used as a light emitting layer and this layer is sandwiched between III-V group semiconductor layers has never been known.

On the other hand, regarding a light emitting device using a nitride-based III-V group compound semiconductor, the L-volume of 35 volumes of Japan Journal of Applied Physics.
In the article entitled "InGaN-based multi-quantum well laser diode" on page 74, an oscillation wavelength of 41
Room temperature pulse oscillation of 7nm LD has been reported.
LD operating voltage is 40V when outputting optical output of 00mW
It is as high as (current is 2 A), which is a problem in practical use. This is because the electrodes are directly formed on GaN. As a method of solving this, GaA having a smaller band gap is formed on the nitride-based III-V group compound semiconductor layer.
It is conceivable to grow a III-V group compound semiconductor layer such as s, but it is difficult due to the lattice mismatch between GaAs and GaN, and even if it is obtained, the element is caused by defects due to the lattice mismatch. Is not reliable enough. That is,
A semiconductor light-emitting device having a structure in which a nitride-based III-V group compound semiconductor layer is used as a light-emitting layer and this layer is sandwiched between non-nitride-based III-V group compound semiconductor layers has never been known.

[0012]

DISCLOSURE OF THE INVENTION The present invention solves the above problems and provides a novel II-VI group compound semiconductor light emission which is highly reliable and operates at a low voltage even when a semiconductor having a wide band gap is used for a light emitting layer. Element or nitride system III-
An object of the present invention is to provide a group V compound semiconductor light emitting device and a method for manufacturing the same.

[0013]

According to the present invention, a first semiconductor layer including one or more layers including a light emitting layer has a second semiconductor layer and a third semiconductor layer each including one or more layers. A semiconductor light-emitting element sandwiched between two elements, the group of the periodic table to which the element forming the matrix of the first semiconductor layer belongs, and the element forming the matrix of the second and third semiconductor layers. The present invention relates to a semiconductor light emitting device characterized by being different from the group of the periodic table to which is belongs.

The semiconductor light emitting device having this structure is a semiconductor light emitting device having a novel structure obtained for the first time by the manufacturing method described later, and enables free design beyond the group of elements constituting the matrix. . Here, the elements forming the matrix of the first to third semiconductor layers can be appropriately selected according to the required characteristics.

In this semiconductor light emitting device, the first
It is particularly preferable that the semiconductor layer of is a II-VI group compound semiconductor layer, and the second semiconductor layer and the third semiconductor layer are a III-V group compound semiconductor layer. The II-VI group compound semiconductor has a wide band gap and it is extremely difficult to make ohmic contact with the electrode material. With such a structure, ohmic contact with the electrode can be obtained. .

Further, the portions of the second semiconductor layer and the third semiconductor layer adjacent to the first semiconductor layer are 2-5.
It is preferably composed of a III-V group arsenic compound semiconductor layer having a molecular layer thickness. That is, in the III-V group arsenic compound semiconductor layer, the group V element escape from the surface of the layer during growth interruption is III.
Since it is less likely to occur as compared with the group V phosphorus compound semiconductor, it has an effect of keeping the surface of the epitaxial growth layer a mirror surface. Therefore,
When a III-V group arsenic compound semiconductor layer having a thickness of 2 to 5 molecular layers is provided, II-VI is formed on the III-V group compound semiconductor layer.
This facilitates epitaxial growth of the group compound semiconductor layer. Hereinafter, this layer is referred to as an interface stabilizing layer.

Further, according to the present invention, the first semiconductor layer including one or more layers including the light emitting layer is sandwiched between the second semiconductor layer and the third semiconductor layer each including one or more layers. A semiconductor light-emitting device configured, wherein the first semiconductor layer comprises one or more III-V group nitrogen compound semiconductor layers,
The nitrogen composition of the second semiconductor layer and the third semiconductor layer is 1%.
The present invention relates to a semiconductor light emitting device comprising one or more layers having the following one or more III-V group compound semiconductor layers. According to this configuration, the contact with the electrode is
It is possible to use a III-V group compound semiconductor layer such as GaAs having a smaller band gap. The semiconductor light emitting device having this structure is also manufactured by the below-described manufacturing method, which has been difficult to achieve with a nitride-based III-V group compound semiconductor layer and GaA.
It is possible to stack III-V group compound semiconductor layers such as s.

In this light emitting device, a portion of the second semiconductor layer and the third semiconductor layer adjacent to the first semiconductor layer is used as a stabilizing layer to form a group III-V phosphorus compound having a thickness of 2 to 5 molecular layers. It is preferably composed of a semiconductor layer.

Furthermore, in any of the above semiconductor light emitting devices, it is preferable that the second semiconductor layer and / or the third semiconductor layer have a band barrier relaxation layer. The band barrier relaxation layer is composed of semiconductor multilayers that are sequentially stacked, and the bandgap of each layer becomes smaller as the distance from the first semiconductor layer increases, and the layer adjacent to the first layer in the multilayer has the first layer. The outermost layer of the semiconductor layers (second and / or third)
Is smaller than the band gap of the portion adjacent to the semiconductor layer).

In the present invention, the conductivity types of the second semiconductor layer and the third semiconductor layer are usually different from each other.

In the present invention, each of the second semiconductor layer and the third semiconductor layer comprises one or more layers laminated on the first substrate and the second substrate, respectively.
The second semiconductor layer, the first semiconductor layer, the third semiconductor layer, and the second substrate may be layered in this order (or vice versa). This substrate is selected as a semiconductor substrate that is suitable for epitaxial growth of the second semiconductor layer or the third semiconductor layer and does not generate an energy barrier at the interface. It is preferable that at least one of the substrates is as thin as possible in order to improve heat dissipation, but one substrate is preferably 10 to 100 μm from a practical viewpoint. The semiconductor light emitting device having such a structure has an advantage that the metal electrode can be formed on the back surface of the substrate simultaneously with the formation of the epitaxial layer in the manufacturing process.

Further, according to the present invention, the second semiconductor layer is laminated on a first substrate, and a layer which is a part of the first semiconductor layer and includes at least a light emitting layer is laminated on the second semiconductor layer. 1
And a step of stacking the third semiconductor layer on the second substrate, and stacking the remaining layers of the first semiconductor layer not stacked in the first stacking step on the second semiconductor layer. Manufacture of a semiconductor light emitting device including a laminating step, and a step of directly laminating and bonding a first substrate and a second substrate on which respective layers are formed by the laminating step so that the first semiconductor layers face each other. Regarding the method.

In the present invention, at least one of the first and second substrates is made of a metal having a melting point lower than the growth temperature of the semiconductor epitaxial growth layer grown on those substrates and higher than the growth temperature. It is also possible to form a metal electrode by fusing to a support having a melting point and epitaxially growing a semiconductor layer on a substrate at a predetermined growth temperature in a growth apparatus, and at the same time reducing the contact resistance at the interface between the metal and the semiconductor substrate.

In this case, instead of fusing with a metal having a low melting point, the side surface (rear surface) opposite to the surface on which each of the above layers is formed on at least one of the first and second substrates.
Alternatively, at least one kind of metal electrode material may be vapor-deposited in advance to form the metal electrode.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION II- on the GaAs substrate of the present invention
The Group VI semiconductor light-emitting element is, for example, as shown in FIG.
Between the electrode side and the p-ZnSe layer 27, the p ⁺ -GaAs contact layer 32, the p-type band barrier relaxation layer 35, and the p-Ga are formed.
The As interface stabilizing layer 28 has a III-1V semiconductor layer. The action of these III-V semiconductor layers is shown in FIG.
This will be described with reference to FIG. 8A, 8B, and 8C are used for the contact interface between the Au electrode and the p-ZnSe contact layer, the hetero interface between the p-GaAs layer and the p-ZnSe layer, and the semiconductor LD of the present invention, respectively. Band barrier relaxation layer and p-
It is a band schematic diagram at 0 bias of the hetero interface of a ZnSe layer.

As shown in (a), the Au electrode and p-Z
A band barrier in the valence band of 1.6 eV exists at the hetero interface of the nSe contact layer.

Further, as shown in (b), p-GaAs
A band barrier in the valence band of 1.4 eV also exists at the hetero interface between the layer and the p-ZnSe layer. However, as shown in (c), the band barrier of the valence band at the hetero interface between the p-AlInP layer and the p-ZnSe layer is only 0.43 eV. If the potential barrier of the valence band between the p-type contact layer and the LD element becomes small, the injection of holes becomes easy. Therefore, between the p-GaAs layer and the p-ZnSe layer, p-
By inserting the AlInP layer, the operating voltage of the ZnSe based semiconductor LD can be reduced. That is, p-
The AlInP layer functions as a band barrier relaxation layer.

Further, GaInP, GaAs, and InGaAs, which are semiconductors having a smaller band gap than AlInP, are used.
By further combining, as shown in (c),
The band barrier can be gradually relaxed. In addition, since a semiconductor layer having a small band gap enables high p-doping, there is an effect that ohmic contact with a metal electrode is easily obtained.

Such AlGaI is usually formed on ZnSe.
It is difficult to grow an nP-based band barrier relaxation layer due to the difference in the growth temperature of these crystals. However, in the manufacturing method of the present invention, since the band barrier relaxation layer is grown and formed not on ZnSe but on the GaAs substrate, a high quality one can be easily obtained. Moreover, since these band barrier relaxation layers are lattice-matched with the GaAs substrate, there is no dislocation due to strain, and high quality and high p concentration doping can be performed.

That is, according to the present invention, there is no deterioration due to dislocation multiplication of the strongly strained contact layer as seen in the conventional LD, and the II-VI semiconductor light emitting device of the present invention has high reliability.

In the process of manufacturing the semiconductor LD wafer shown in FIG. 1, the p-GaAs substrate is removed by etching, and p ⁺ -
400 to form a p-electrode on the GaAs contact layer
Even if the wafer is heated to about C, the wafer has a structure in which the p-ZnSe layer is capped with the AlGaInP-based band barrier relaxation layer, so that Se escape from the ZnSe layer can be prevented. Therefore, the semiconductor light emitting device manufacturing method of the present invention can avoid thermal deterioration of the LD during the electrode formation process.

In the method of manufacturing a II-VI semiconductor light emitting device shown in FIG. 2 of the present invention, a low melting point metal such as In or another metal electrode material is fused or vapor-deposited on the back surfaces of the p substrate and the n substrate before growth. Then, the metal and the interface of the semiconductor substrate are alloyed with each other to form the metal electrode while growing the respective semiconductor layers on the substrates. Then, the semiconductor layer grown on the p substrate and the semiconductor layer including the semiconductor light emitting layer grown on the n substrate are directly bonded to each other, and the p substrate and the n substrate after bonding are left without being removed by etching or the like. Therefore, the electrode process after the growth of the LD element wafer becomes unnecessary, and the thermal deterioration of the wafer and the growth of dislocations due to the electrode process can be avoided.

In the method for manufacturing a semiconductor light emitting device according to the present invention, the semiconductor layers on the surfaces of the two wafers to be bonded are made to have the same composition, that is, the semiconductor layers of the same type and the same conductivity type, and the bonding surfaces are directly bonded. When manufactured, a distortion-free joint surface can be easily formed. Further, since the distance between the bonding surface and the light emitting layer can be set sufficiently, the influence of the bonding on the light emitting layer can be sufficiently reduced.

Further, in the method for manufacturing a semiconductor light emitting device of the present invention, since it is not necessary to perform thermal annealing after bonding at a high temperature higher than the growth temperature and under pressure, deterioration due to pressure and heat of the lattice mismatched layer included in the epi-wafer can be prevented. And the doping concentration of the p-clad layer does not decrease. As a result, the bonding layer formed by the compound semiconductor bonding method of the present invention can maintain the same quality as the epitaxial layer.

The same applies to the III-V group nitrogen compound semiconductor LD of the present invention.

[0036]

EXAMPLES The present invention will be described in more detail with reference to the following examples.

[Embodiment 1] FIG. 1 is a sectional structural view of this embodiment. The LD of this embodiment has an n-electrode 10 and a thickness 10
0 μm n-type GaAs substrate 11, 300 nm thick n-type
GaAs buffer layer 12, n-type band barrier relaxation layer 34,
Bilayer n-GaAs interface stabilizing layer 16, layer thickness 30
nm n-ZnSe layer 17, 150 nm thick n-ZnSe layer
SSe layer _{18, n-Mg 0.1 Zn 0.9} S 0.14 of thickness 1μm
Se _0.86 clad layer 19, n-ZnS having a layer thickness of 100 nm
Se light confinement layer 20, Zn _0.8 Cd _0.2 S with a layer thickness of 7 nm
e-well layer 21, ZnSSe barrier layer 2 having a layer thickness of 10 nm
2. Zn _0.8 Cd _0.2 Se well layer 23 having a layer thickness of 7 nm, p-ZnSSe optical confinement layer 24 having a layer thickness of 100 nm, p-Mg _0.1 Zn _0.9 S _0.14 Se _0.86 clad layer 25 having a layer thickness of 0.8 μm, layer thickness of 300 nm P-ZnSSe layer 26, a p-ZnSe layer 27 having a layer thickness of 40 nm, and a bilayer p-G layer
aAs interface stabilization layer 28, P-type band barrier relaxation layer 35,
It comprises a p ⁺ -GaAs contact layer 32 and a p electrode 33. The n-type band barrier relaxation layer 34 has a layer thickness of 50 nm.
GaInP layer 13, n- (Al _0.5 Ga with a layer thickness of 50 nm
_0.5 ) _0.5 In _0.5 P layer 14, n-AlI having a layer thickness of 50 nm
The p-type band barrier relaxation layer 35 is composed of the nP layer 15, and the p-type band barrier relaxation layer 35 includes a p-AlInP layer 29 having a layer thickness of 50 nm and a p-AlInP layer having a layer thickness of 50 nm.
-(Al _0.5 Ga _0.5 ) _0.5 In _0.5 P layer 30, layer thickness 50 n
m of p-GaInP layer 31.

The LD of Example 1 is an LD element in which a II-VI group compound semiconductor layer is provided as a light emitting layer on a GaAs substrate. That is, in this LD, the first semiconductor layer including the light emitting layer is a II-VI group compound semiconductor layer, the second semiconductor layer and the third semiconductor layer are III-V group compound semiconductor layers, and the first semiconductor A layer is sandwiched between a second semiconductor layer and a third semiconductor layer. Further, the two semiconductor layers sandwiching the first semiconductor layer are III-V group compound semiconductor layers having different conductivity types, and two molecular layers are provided at the boundary between the II-VI group compound semiconductor layer and the III-V group compound semiconductor layer. Thick II
N-type and p-type G that is an IV group arsenic compound semiconductor layer
It has an aAs interface stabilizing layer. Also, n-type and p
Type band barrier relaxation layer.

MBE,
A vapor phase growth method such as MOCVD, MOMBE and gas source MBE is used. As the III-V group semiconductor raw material, A
Solid raw materials such as 1, Ga, In, As or P, Al, G
Organometallic raw material containing a, In, As or P, or A
A hydrogen compound containing s or P is used. As the II-VI group semiconductor raw material, simple substances such as Cd, Zn, Mg and S and compounds such as CdS, ZnS and ZnCl ₂ are used. The hydrogen compound raw material or the organometallic raw material may be cracked at a high temperature to supply the raw material element.

Be, Mg, Zn or the like is used as the p-dopant of the III-V semiconductor layer, and Si or S is used as the n-dopant.
n or the like is used. The p-dopant of the II-VI group semiconductor layer is nitrogen plasma of excited nitrogen or neutral radicals supplied by an ECR plasma gun or a thermal decomposition cell, and the n-dopant is Cl of ZnCl ₂ or metal Ga. To use.

The n-type doping concentration is about 8 in all layers.
× 10 ¹⁷ cm ^-3 , p-type doping concentration is p
-MgZnSSe cladding layer 25 is 5 × 10 ¹⁷ cm ^-3 ,
p-ZnSSe layer 26, p-ZnSe layer 27, p-Ga
The As interface stabilization layer 28 is 8 × 10 ¹⁷ cm ⁻³ , the p-type band barrier relaxation layer 35 is 1 × 10 ¹⁸ cm ⁻³ , and the p ⁺ -GaAs contact layer 32 is about 1 × 10 ¹⁹ cm ⁻³ . Further, the Zn _0.8 Cd _0.2 Se well layer 21 and Z which are the light emitting layer
The nSSe barrier layer 22 layer is an undoped layer. However,
The doping concentration, the composition of the ternary mixed crystal and the composition of the quaternary mixed crystal, and the layer thickness are not limited to those in this embodiment, and can be adjusted so that the LD gain is maximized.

The method of manufacturing the LD of this embodiment will be described below with reference to FIG. First, in the MBE growth chamber dedicated to the III-V group, the first substrate n-GaAs substrate 11
Then, the substrate temperature is set to 630 ° C. under As beam irradiation and G
After evaporating the oxide film of the aAs substrate, the n-GaAs buffer layer 12 is grown. The growth temperature is lowered to 540 ° C. while growing the n-GaAs buffer layer 12, and AlGa
After growing the InP-based n-type band barrier relaxation layer 34 and the n-GaAs interface stabilizing layer 16, the substrate temperature is lowered to 150 ° C. The n-GaAs interface stabilizing layer 16 has an effect of facilitating the growth of n-ZnSe grown thereon.

Next, the wafer is used as a MB for II-VI group only.
E Transfer to the growth chamber while maintaining a high vacuum, and grow at a growth temperature of 30
The n-ZnSe layer 17 and the n-ZnSSe layer 1 were formed at around 0 ° C.
8, n-MgZnSSe cladding layer 19, ZnSSe optical confinement layer 20, ZnCdSe / ZnSSe quantum well active layer 36, ZnSSe optical confinement layer 24, p-MgZn
SSe cladding layer 25, p-ZnSSe layer 26, layer thickness 2
0 nm p-ZnSe layer 27 is sequentially grown by MBE,
Each layer is formed on the first substrate.

Similarly, 350 μm thick p-GaA is formed.
p-GaAs buffer layer 39, p-Ga on s substrate 40
The InP etching stop layer 38, the p ⁺ -GaAs contact layer 32, and the p-GaAs interface stabilizing layer 28 are formed as III.
-After growing in the MBE growth chamber dedicated to group V, layer thickness 20n
The p-ZnSe layer 27 of m is grown in the MBE growth chamber dedicated to the II-VI group, and each layer is formed on the second substrate.

In this way, the surface layers of the first substrate and the second substrate were both p-ZnSe layers having the same composition (having the same constituent elements and the same conductivity type). However, in this embodiment, Se is exposed on the surface of the first substrate (Se stabilizing surface 42) and Zn is exposed on the surface of the second substrate (Zn stabilizing surface 43). These two wafers are kept at the same temperature of, for example, about 280 ° C. in a high vacuum, and p-Zn
By mechanically directly bonding 41 the Se stabilizing surface 42 and the Zn stabilizing surface 43 of the Se layer 27, a bonded and integrated wafer is obtained.

Next, the p-GaAs substrate 40 and p-GaA
The s buffer layer 39 and the p-GaInP etching stop layer 38 are removed by etching 44. Specifically, this is performed as follows. First, the integrated wafer is taken out from the MBE apparatus, and the In adhering to the substrate surfaces on the n-side and the p-side used for fixing the substrate is immersed in hydrochloric acid to be removed.

The surface of the n-GaAs substrate is covered with wax,
For the p-GaAs substrate 40 and the p-GaAs buffer layer 39, a phosphoric acid-based etching solution (phosphoric acid (85% aqueous solution):
Remove with hydrogen peroxide (30% aqueous solution): water = 1: 1: 10). p-GaInP etching stove layer 3
At 8, the phosphoric acid type etching is automatically stopped. p-Ga
The InP etching stop layer 38 is removed using hydrochloric acid to expose the p ⁺ -GaAs contact layer 32 on the surface.

In the following steps, the wax is peeled off by organic cleaning and n-GaA is used as in the normal LD electrode forming process.
The s substrate is polished, a stripe is formed on the p side using quartz glass or a resist, and then a p electrode and an n electrode are formed.

[Embodiment 2] FIG. 2 shows L of Embodiment 2 of the present invention.
It is a section construction drawing of D. The semiconductor light emitting device of this example has I
an n-electrode 53, an n-GaAs substrate 11 having a thickness of 350 μm,
The n-GaAs buffer layer 12 having a layer thickness of 300 nm, the n-type band barrier relaxing layer 34, the n-GaAs interface stabilizing layer 16 having a two-layer thickness, the n-ZnSe layer 17 having a layer thickness of 30 nm, and the n-ZnSSe layer having a layer thickness of 150 nm. Layer 18, n-MgZnSSe cladding layer 19 with a Mg composition of 0.1 and a layer thickness of 1 μm, n-ZnSSe optical confinement layer 20 with a layer thickness of 100 nm, layer thickness 7
nm Zn _0.8 Cd _0.2 Se well layer 21, layer thickness 10 nm
ZnSSe barrier layer 22, Zn _0.8 Cd with a layer thickness of 7 nm
_0.2 Se well layer 23, p-ZnSS having a layer thickness of 100 nm
e Light confinement layer 24, Mg composition 0.1 and layer thickness 0.8 μm
P-MgZnSSe cladding layer 25, layer thickness 300 nm
P-ZnSSe layer 26, p-ZnSe having a layer thickness of 40 nm
A layer 27, a bilayer thick p-GaAs interface stabilizing layer 28,
p-type band barrier relaxation layer 35, p-Ga having a layer thickness of 0.1 μm
As layer 50, p-GaAs substrate 51 having a thickness of 50 μm, I
It consists of an n-electrode 52. The n-type and p-type band barrier relaxation layers 34 and 35 have the same layer structure as that of the first embodiment.

The LD of this embodiment has a structure in which a semiconductor layer including a light emitting layer made of an element of a group different from the group of elements constituting the substrate is sandwiched between two substrates, and p-GaA is used.
s layer 50, p-GaAs substrate 51, In electrodes 52, 53
Other than that, the structure is the same as that of the LD of Example 1.

The LD manufacturing method of the second embodiment is a method of directly bonding wafers similar to the LD manufacturing method of the first embodiment, in which the semiconductor substrate is fused with a low melting point metal such as In to a high melting point support. Then, the metal electrode is formed by making an ohmic contact at the interface between the metal and the semiconductor substrate while epitaxially growing on the substrate at a predetermined growth temperature in the growth apparatus.

According to the structure and the manufacturing method of the second embodiment, since the p-GaAs substrate removal and the n-side and p-side electrode forming processes required for manufacturing the LD of the first embodiment are not required, the electrode is not formed. There is an advantage that a high-quality LD can be obtained in a very short time without the heat deterioration and the trouble and failure of the electrode forming process.

[Embodiment 3] FIG. 3 shows L of Embodiment 3 of the present invention.
It is a section construction drawing of D. The LD of this embodiment is AuGe.
Ni-n electrode 60, n-InP substrate 6 having a thickness of 350 μm
1, n-InP buffer layer 62 having a layer thickness of 0.1 μm, 2 minutes
N-InGaAs interface stabilizing layer 63 having a child layer thickness, layer thickness 15
0 nm n-Zn_0.48Cd_0.52Se layer 64, layer thickness 1 μm
N-Mg _0.2Zn_0.4Cd_0.4Se clad layer 65, layer
100 nm thick n-Mg_0.05Zn_{0.4 6}Cd_0.49Se light closed
Containment layer 66, Zn with a layer thickness of 10 nm_0.4Cd_0.6Se Hue
Layer 67, Mg having a layer thickness of 15 nm_0.05Zn_0.46Cd_0.49S
e barrier layer 68, n-Zn having a layer thickness of 10 nm_0.4Cd_0.6S
e-well layer 69, p-Mg having a layer thickness of 100 nm_0.05Zn
_0.46Cd_0.49Se light confinement layer 70, with a layer thickness of 0.7 μm
n-Mg_0.2Zn_0.4Cd _0.4Se clad layer 71, layer thickness
300 nm p-Zn_0.48Cd_0.52Se layer 72, 2 molecules
P-InGaAs interface stabilizing layer 73 having a layer thickness of 200
nm p-InP layer 74, p⁺-InGaAs contact
And a p-electrode 76.

The LD of Example 3 is the same as the LD of Example 1 except that the II-VI group semiconductor layer having an active layer is III-V.
It is an example of a semiconductor LD having a structure sandwiched between group semiconductor layers.
The difference between the LD of Example 3 and the LD of Example 1 is that
It is an LD in which a II-VI group compound semiconductor layer is provided as a light emitting layer on an InP substrate, and has n-type and p-type InGaAs layers as an interface stabilizing layer, but has a III-V group band barrier relaxing layer. The point is not doing.

The method of manufacturing the LD of Example 3 uses a method of directly bonding the wafers, and Au / Ge / Ni, which is a metal electrode material, is vapor-deposited on the back surface of the n-type InP semiconductor substrate to form a metal electrode. After being formed, the n-type InP
It is characterized by performing epitaxial growth on the surface of a semiconductor substrate.

A method of manufacturing the LD of Example 3 will be described below with reference to FIG. First, the n-InP substrate 6
Au / Ge / N on the back surface of 1 (the surface opposite to the semiconductor growth surface)
i was vapor-deposited to form a metal electrode. Next, in the MBE growth chamber dedicated to the III-V group, the substrate temperature was set to 530 ° C. and the natural oxide film of the InP substrate was evaporated on the n-InP substrate 61, and then the substrate temperature was set to 520 ° C. N-In
P buffer layer 62, n-InGaAs interface stabilization layer 63
Are grown and the substrate temperature is lowered to 150 ° C. n-InG
The aAs interface stabilizing layer is grown on it with n-Zn _0.48.
It has the effect of facilitating the growth of the Cd _0.52 Se layer.

Next, the wafer is treated with an MB dedicated to II-VI group.
E Transfer to the growth chamber while maintaining a high vacuum, and grow at a growth temperature of 30
At around 0 ° C., n-Mg _0.2 Zn _0.4 Cd _0.4 Se cladding layer 65, n-Mg _0.05 Zn _0.46 Cd _0.49 Se optical confinement layer 66, n-Zn _0.4 Cd _0.6 Se / n-Mg _0.05 Zn
_0.46 Cd _0.49 Se quantum well active layer 83, p-Mg _0.05
Zn _0.46 Cd _0.49 Se optical confinement layer 70, n-Mg _0.2
A Zn _0.4 Cd _0.4 Se clad layer 71 and a p-Zn _0.48 Cd _0.52 Se layer 72 having a layer thickness of 150 nm are sequentially MBE-grown to form each layer on the first substrate.

Similarly, p-on the p-InP substrate 81.
After growing the InP buffer layer 80, the p ⁺ -InGaAs contact layer 75, the p-InP layer 74, and the p-InGaAs interface stabilizing layer 73 in the MBE growth chamber dedicated to the III-V group, the p-Zn layer having a layer thickness of 150 nm is grown. _0.48 Cd _0.52 Se layer 7
2 in the MBE growth chamber dedicated to the II-VI group,
Each layer is formed on the substrate.

In this way, the surface layers of the first substrate and the second substrate were both layers having the same composition (having the same constituent element and the same conductivity type). However, in this embodiment, Se is exposed on the surface of the first substrate (Se stabilizing surface 86),
ZnCd was exposed on the surface of the substrate (Zn
Cd stabilization surface 87). The two wafers are kept at the same temperature of, for example, about 280 ° C. in a high vacuum, and p-Zn _0.48
By mechanically directly bonding with the Cd _0.52 Se layer 72, a bonded and integrated wafer is obtained.

Next, the p-InP substrate 81 and the p-InP buffer layer 80 are removed by etching 85. First, the integrated wafer is taken out from the MBE apparatus, and the In adhering to the substrate surface on the n-side and the p-side for fixing the substrate is immersed in nitric acid to be removed.

Next, the surface of the n-InP substrate is covered with wax, and the p-InP substrate 81 and the p-InP buffer layer 80 are etched with a hydrobromic acid-based etching solution (HBr (47% aqueous solution): hydrogen peroxide (30% aqueous solution). ): Water = 4: 1: 1
0) to remove. Since the etching automatically stops on the surface of the p ⁺ -InGaAs contact layer 75, p
^{The +} -GaAs contact layer 75 is exposed.

In the following steps, the wax is removed by organic cleaning and n-InP is used as in the normal LD electrode forming process.
The substrate is polished and a strap is formed on the p side using quartz glass or a resist to form a p electrode. As shown in this embodiment, the present invention is also applicable when using an InP substrate. Further, by performing the n-side electrode forming process before the growth, it is possible to halve the heat deterioration at the time of forming the electrode of the growth layer and the labor and failure of the electrode forming process.

[Fourth Embodiment] FIG. 4 is a sectional view of an LD according to a fourth embodiment.
It is a structural drawing. The LD of Example 4 has an n-electrode 100, a thickness of
350 μm n-GaAs substrate 101, layer thickness 300 nm
N-GaAs buffer layer 102, n-type band barrier relaxation
Layer 124, bilayer thick n-GaInP interface stabilizing layer 1
06, 50 nm thick n-GaN / InN superlattice layer 10
7, n-Ga with a layer thickness of 800 nm_0.8In_0.2N buffer layer
108, n-Al having a layer thickness of 200 nm _0.12Ga_0.68In
_0.2N-clad layer 109, n-Ga having a layer thickness of 100 nm_0.8
In_{0. 2}N optical confinement layer 110, Ga having a layer thickness of 7 nm_0.6I
n_0.4N well layer 111, Ga having a layer thickness of 10 nm_0.8In
_0.2N barrier layer 112, Ga having a layer thickness of 7 nm_0.6In_0.4N
Well layer 111, p-Ga having a layer thickness of 100 nm_0.8In_0.2
N optical confinement layer 113, p-Al having a layer thickness of 200 nm_0.12
Ga_0.68In_0.2N-clad layer 114, layer thickness 400 nm
P-Ga_0.8In_0.2N layer 115, p with a layer thickness of 400 nm
-Ga_0.8In_0.2N buffer layer 116, with a layer thickness of 50 nm
p-GaN / InN superlattice layer 117, bilayer thickness p-
GaInP interface stabilization layer 118, p-type band barrier relaxation layer
125, p⁺-GaAs contact layer 122, p electrode 1
It consists of 23. The n-type band barrier relaxation layer 124 has a layer thickness of 5
0 nm n-GaInP layer 103, layer thickness 50 nm n-
(Al _0.5Ga_0.5)_0.5In_0.5P layer 104, layer thickness 50n
m-type n-AlInP layer 105, p-type band barrier
The relaxation layer 125 is the p-AlInP layer 11 having a layer thickness of 50 nm.
9, p- (Al with a layer thickness of 50 nm_0.5Ga_0.5)_0.5In_0.5
P layer 120, p-GaInP layer 121 with a layer thickness of 50 nm
Consists of

The LD of Example 4 is a semiconductor light emitting device in which a III-V group nitrogen compound semiconductor layer is provided as a light emitting layer on a GaAs substrate. The first semiconductor layer including the light emitting layer is II
I-V group nitrogen compound semiconductor layer, the second and third semiconductor layers are III-V group compound semiconductor layers containing no nitrogen as a group V element, and the first semiconductor layer is the second and third semiconductor layers. It is a structure sandwiched between. The second and third semiconductor layers are III-V group compound semiconductor layers having different conductivity types, and are located at the boundary between the III-V group nitrogen compound semiconductor layer and the III-V group compound semiconductor layer containing no nitrogen as a V group element. Two
It has n-type and p-type GaInP interface stabilizing layers which are III-V group compound semiconductor layers having a molecular layer thickness. Further, it has n-type and p-type band barrier relaxation layers.

MBE,
A vapor phase growth method such as MOCVD, MOMBE and gas source MBE is used. As the III-V group semiconductor raw material, A
Solid raw materials such as 1, Ga, In, As or P, Al, G
Organometallic raw material containing a, In, As or P, or A
A hydrogen compound containing s or P is used. As the III-V group nitrogen compound semiconductor raw material, Al, Ga or In
A solid raw material such as Al, Ga, In or N is used as an organic metal raw material, or a hydrogen compound including N such as ammonia is used. The hydrogen compound raw material is cracked at a high temperature to supply the raw material element. An Mg compound such as CP ₂ Mg is used as the p-dopant raw material of the III-V semiconductor layer, and Si or the like is used as the n-dopant.

The method of manufacturing the LD of Example 4 will be described below. The manufacturing method of the LD of this embodiment is basically the same as that of the LD of the first embodiment. However, the semiconductor including the light emitting layer is I
Since it is not a group I-VI compound semiconductor but a group III-V nitrogen compound semiconductor, a manufacturing method suitable for it is used.

As shown in FIG. 4, the n-GaAs substrate 10
After growing the n-GaA buffer layer 102 on the substrate 1, the growth temperature is kept at about 540 ° C. and the AlGaInP-based n-type band barrier relaxation layer 124 and the bilayer n-GaInP interface stabilizing layer 106 are grown. . Next, after changing the supplied V group element from P to N and nitriding the surface, the temperature is about 550 ° C.
The n-GaN / InN superlattice layer 107 having a layer thickness of 50 nm and the n-Ga _0.8 In _0.2 N buffer layer 108 having a layer thickness of 150 nm are grown at the growth temperature of 1.

Then, under a sufficient N pressure, the growth temperature was raised to about 1000 ° C., and n-Ga _0.8 I with a layer thickness of 650 nm was formed.
n _0.2 N p-G with a layer thickness of 400 nm from the N buffer layer 108
The a _0.8 In _0.2 N layer 115 is sequentially grown to form each layer on the first substrate.

On the other hand, on the p-GaAs substrate 101, p-
GaAs buffer layer, p-GaInP etching stop layer, p ⁺ -GaAs contact layer 122, p-type band barrier relaxation layer 125, p-GaInP interface stabilizing layer 118.
And then p-GaN / InN in the same manner.
P-Ga _0.8 In ₀ superlattice layer 117 and the layer thickness 400 nm _.2
The N buffer layer 116 is grown to form each layer on the second substrate.

The two wafers thus obtained were treated with about 10
The substrate temperature is kept at 00 ° C., and the surfaces are directly bonded and bonded. Finally, while maintaining the N pressure, the integrated wafer is thermally annealed at 600 ° C. or higher for about 1 hour. As a result, Mg doped into the nitrogen compound semiconductor is activated, and a high concentration p-type nitrogen compound semiconductor is obtained.

N has a high vapor pressure and is easily sublimated from the crystal, but in this method, the two wafers act as cap layers for the other wafers, and it is possible to prevent N escape during thermal annealing.

The integrated wafer was taken out from the MBE crystal growth apparatus, and p-GaAs was formed in the same manner as in the first embodiment.
Substrate 101, p-GaAs buffer layer, p-GaInP
Etching stop layer is removed by etching, and p ⁺ -G
The aAs contact layer 122 is exposed on the surface, and the p-electrode 12
3 is formed.

[Embodiment 5] FIG. 5 is a sectional structural view of an LD of Embodiment 5. The LD of the fifth embodiment has a thickness of 300 μm.
Sapphire substrate 130, AlN buffer layer 131 having a layer thickness of 50 nm, GaN buffer layer 132, n-GaN layer 1
33, n electrode 134, n-AlGaN cladding layer 13
5, GaInN active layer 136, p-AlGaN cladding layer 137, pGaN layer 138, p-GaN layer 139, p-GaN / InN superlattice layer 140 having a layer thickness of 50 nm, p-GaInP interface stabilizing layer having a two-layer thickness 141, p-type band barrier relaxation layer 148, p ⁺ -GaAs contact layer 14
5 and the p electrode 147. p-type band barrier relaxation layer 14
8 is a p-AlInP layer 142 having a layer thickness of 50 nm and a layer thickness of 5
0 nm p- (Al _0.5 Ga _0.5 ) _0.5 In _0.5 P layer 14
3 and a p-GaInP layer 144 having a layer thickness of 50 nm.

The LD of Example 5 is a semiconductor light emitting device in which a III-V group nitrogen compound semiconductor layer is provided as a light emitting layer on a sapphire substrate. This LD is an LD element having a structure in which a light emitting layer is sandwiched between two substrates and has a bilayer thickness of III.
It has a p-type GaInP interface stabilizing layer that is a -V group neighboring compound semiconductor layer, and a p-type band barrier relaxation layer.

The manufacturing method of the LD of the fifth embodiment is similar to that of the LD of the fourth embodiment, in which the wafer is directly bonded. The position of bonding is the position indicated by the bonding interface 149 in FIG. However, the AlN buffer layer 131 and the GaN buffer layer 132 are 5
Grow at a low temperature of 50 ° C. In addition, the method for growing the III-V group nitrogen compound layer is the same as that in the fourth embodiment.

[0076]

INDUSTRIAL APPLICABILITY The structure of the present invention can be applied to various kinds of semiconductor light emitting devices, the semiconductor layer including the light emitting layer can have an arbitrary structure, and the kind of substrate can be a specific type. Not limited. That is, according to the present invention, it is possible to provide a semiconductor light emitting device having a novel structure, which has high versatility and enables free design beyond the group of elements constituting the matrix.

Further, according to the present invention, since the contact layer of the III-V group compound semiconductor of high quality and high doping concentration which is lattice-matched can be provided, the ohmic contact between the n-electrode and the p-side electrode can be easily obtained.

Further, since the contact layer and the band barrier relaxation layer are lattice matching layers, there is no deterioration due to dislocation multiplication of the strongly strained contact layer as seen in the conventional LD, and the semiconductor light emitting device can operate with high reliability. is there.

Since the semiconductor light emitting device of the present invention can be provided with a band relaxation barrier layer of high quality and high doping concentration lattice-matched with the substrate, for example, a GaAs substrate and a II-VI group in the conduction band and the valence band. The band barrier between the semiconductor layers is gradually relaxed, and it is easy to inject electrons and holes into the semiconductor layer including the light emitting layer. That is, the semiconductor light emitting device of the present invention can operate at a low voltage.

That is, according to the present invention, a II-VI group compound semiconductor light emitting device or III having high reliability and low voltage operation.
A -V group nitrogen compound semiconductor light emitting device can be realized.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor light emitting device of Example 1.

FIG. 2 is a sectional view of a semiconductor light emitting device of Example 2.

FIG. 3 is a sectional view of a semiconductor light emitting device of Example 3.

FIG. 4 is a sectional view of a semiconductor light emitting device of Example 4.

FIG. 5 is a sectional view of a semiconductor light emitting device of Example 5.

FIG. 6 is an explanatory view of the method for manufacturing the semiconductor light emitting device of the first embodiment.

FIG. 7 is an explanatory view of the method for manufacturing the semiconductor light emitting device of the third embodiment.

FIG. 8 is a diagram illustrating the operation of each layer of the present invention. (A) Schematic band diagram of the contact interface between the Au electrode and the p-ZnSe contact layer at 0 bias (b) Schematic band diagram of the hetero interface of the p-GaAs layer and p-ZnSe layer at 0 bias (c) Band Schematic band diagram of the hetero interface between the barrier relaxation layer and the p-ZnSe layer at 0 bias

FIG. 9 is a cross-sectional view of a conventional II-VI group compound semiconductor light emitting device.

[Explanation of symbols]

10 n Electrode 11 n-GaAs Substrate 12 n-GaAs Buffer Layer 13 n-GaInP Layer 14 n- (Al _0.5 Ga _0.5 ) _0.5 In _0.5 P Layer 15 n-AlInP Layer 16 n-GaAs Interface Stabilization Layer 17 n-ZnSe Layer 18 n-ZnSSe layer 19 n-Mg _0.1 Zn _0.9 S _0.14 Se _0.86 Cladding layer 20 n-ZnSSe optical confinement layer 21 Zn _0.8 Cd _0.2 Se well layer 22 ZnSSe barrier layer 23 Zn _0.8 Cd _0.2 Se well layer 24 p-ZnSSe Optical confinement layer 25 p-Mg _0.1 Zn _0.9 S _0.14 Se _0.86 clad layer 26 p-ZnSSe layer 27 p-ZnSe layer 28 p-GaAs interface stabilizing layer 29 p-AlInP layer 30 p- (Al _0.5 Ga _0.5 ) _0.5 In _0.5 P layer 31 p-GaInP layer 32 p ⁺ -GaAs contact layer 33 p electrode 34 n-type Band barrier relaxation layer 35 p-type band barrier relaxation layer 36 quantum well active layer 37 junction interface 38 p-GaInP etching stop layer 39 p-GaAs buffer layer 40 p-GaAs substrate 44 etching removal 45 In metal 50 p-GaAs layer 51 p -GaAs substrate 52, 53 In electrode 60 AuGeNi-n electrode 61 n-InP substrate 62 n-InP buffer layer 63 n-InGaAs interface stabilizing layer 64 n-Zn _0.48 Cd _0.52 Se layer 65 n-Mg _0.2 Zn _0.4 Cd _0.4 Se clad layer 66 n-Mg _0.05 Zn _0.46 Cd _0.49 Se optical confinement layer 67 Zn _0.4 Cd _0.6 Se well layer 68 Mg _0.05 Zn _0.46 Cd _0.49 Se barrier layer 69 n-Zn _0.4 Cd _0.6 Se well layer 70 p-Mg _0.05 Zn _0.46 Cd _0.49 Se Light confinement layer 71 n-Mg _0.2 Zn _0.4 Cd _0.4 Se clad layer 72 p-Zn _0.48 Cd _0.52 Se layer 73 p-InGaAs interface stabilization layer 74 p-InP layer 75 p ⁺ -InGaAs contact layer 76 p electrode 77 junction interface 80 p-InP buffer layer 81 p-InP Substrate 82 In metal layer 83 Quantum well active layer 85 Etching removal 100 n electrode 101 n-GaAs substrate 102 n-GaAs buffer layer 103 n-GaInP layer 104 n- (Al _0.5 Ga _0.5 ) _0.5 In _0.5 P layer 105 n-AlInP Layer 106 n-GaInP interface stabilization layer 107 n-GaN / InN superlattice layer 108 n-Ga _0.8 In _0.2 N buffer layer 109 n-Al _0.12 Ga _0.68 In _0.2 N cladding layer 110 n-Ga _0.8 In _0.2 N optical confinement layer 111 Ga _0.6 In _0.4 N well layer 112 Ga0.8In0 2N barrier layer 113 p-Ga _0.8 In _0.2 N light confining layer _{114 p-Al 0.12 Ga 0.68 In} 0.2 N cladding layer 115 p-Ga _0.8 In _0.2 N layer 116 p-Ga _0.8 In _0.2 N buffer layer 117 p-GaN / InN superlattice layer 118 p-GaInP interface stabilization layer 119 p-AlInP layer 120 p- (Al _0.5 Ga _0.5 ) _0.5 In _0.5 P layer 121 p-GaInP layer 122 p ⁺ -GaAs contact layer 123 p electrode 124 n-type band Barrier relaxation layer 125 p-type band barrier relaxation layer 126 Junction interface 130 Sapphire substrate 131 AlN buffer layer 132 GaN buffer layer 133 n-GaN layer 134 n electrode 135 n-AlGaN cladding layer 136 GaInN active layer 137 p-AlGaN cladding layer 138 p -GaN layer 139 p-GaN 140 p-GaN / InN superlattice layer 141 p-GaInP interfacial stability layer 142 p-AlInP layer _{143 p- (Al 0.5 Ga 0.5)} 0.5 In 0.5 P layer 144 p-GaInP layer 145 p ⁺ -GaAs contact layer 147 p Electrode 148 p-type band barrier relaxation layer 149 Junction interface 300 In electrode 301 n-GaAs substrate 302 n-GaAs buffer layer 303 n-ZnSe layer 304 n-ZnSSe layer 305 n-MgZnSSe cladding layer 306 n-ZnSSe optical confinement layer 307 ZnCdSe Active layer 308 p-ZnSSe optical confinement layer 309 p-Mg
ZnSSe clad layer 310 p-ZnSSe layer 311 p-ZnSe layer 312 p-ZnSe / ZnTe multiple quantum well layer 313 p-ZnTe contact layer 314 Insulating layer 315 Pd / Pt / Au electrode

Claims (13)

[Claims] 1. A first layer comprising one or more layers including a light emitting layer
Is a semiconductor light-emitting device configured by being sandwiched between a second semiconductor layer and a third semiconductor layer, each of which is composed of one or more layers, and an element constituting a matrix of the first semiconductor layer. A semiconductor light-emitting element characterized in that the group of the periodic table to which the element belongs is different from the group of the periodic table to which the elements constituting the bases of the second and third semiconductor layers belong. 2. The first semiconductor layer is a II-VI group compound semiconductor layer, and the second semiconductor layer and the third semiconductor layer are III-V group compound semiconductor layers. Item 2. The semiconductor light emitting device according to item 1. 3. A portion of the second semiconductor layer and the third semiconductor layer adjacent to the first semiconductor layer is formed of a III-V group arsenic compound semiconductor layer having a thickness of 2 to 5 molecular layers. The semiconductor light emitting device according to claim 2, wherein 4. A first layer comprising one or more layers including a light emitting layer
Is a semiconductor light emitting device configured by being sandwiched between a second semiconductor layer and a third semiconductor layer, each of which is composed of one or more layers, wherein the first semiconductor layer has one or more layers. It is composed of a group V nitrogen compound semiconductor layer, and the second semiconductor layer and the third semiconductor layer have a nitrogen composition of 1%.
A semiconductor light emitting device comprising one or more layers having the following one or more III-V group compound semiconductor layers. 5. The portions of the second semiconductor layer and the third semiconductor layer adjacent to the first semiconductor layer are composed of a III-V phosphorus compound semiconductor layer having a thickness of 2 to 5 molecular layers. The semiconductor light emitting device according to claim 4, wherein 6. The second semiconductor layer and / or the third semiconductor layer.
6. The semiconductor light emitting device according to claim 1, wherein the semiconductor layer has a band barrier relaxation layer. 7. The semiconductor light emitting device according to claim 1, wherein the second semiconductor layer and the third semiconductor layer have different conductivity types. 8. The second semiconductor layer and the third semiconductor layer are formed of one or more layers laminated on the first substrate and the second substrate, respectively. 2. The semiconductor layer, the first semiconductor layer, the third semiconductor layer, and the second substrate are layered in this order.
7. The semiconductor light emitting device according to any one of to 7. 9. A first stack in which the second semiconductor layer is stacked on a first substrate, and a layer which is a part of the first semiconductor layer and includes at least a light emitting layer is stacked on the second semiconductor layer. And a second laminating step of laminating the third semiconductor layer on a second substrate and laminating the remaining layer of the first semiconductor layer not laminated in the first laminating step on the third substrate. And a first substrate and a second substrate on which each layer is formed by the stacking step.
The substrate of claim 1 and the step of directly laminating and bonding the first semiconductor layers so that the first semiconductor layers face each other.
9. The method for manufacturing a semiconductor light emitting device according to any one of 8. 10. A first stack in which the second semiconductor layer is stacked on a first substrate, and a layer which is a part of the first semiconductor layer and includes at least a light emitting layer is stacked on the second semiconductor layer. And a second laminating step of laminating the third semiconductor layer on a second substrate and laminating the remaining layer of the first semiconductor layer not laminated in the first laminating step on the third substrate. And a first substrate and a second substrate on which each layer is formed by the stacking step.
And the first semiconductor layer, the first semiconductor layer, the first semiconductor layer, the third semiconductor layer, and the third semiconductor layer, which are manufactured by the bonding step. Removing at least a part of either the first substrate or the second substrate in the bonded substrate consisting of the semiconductor layer and the second substrate, The method for manufacturing a semiconductor light emitting device according to claim 1, further comprising a step of forming an electrode or a stripe structure and an electrode on the removed surface. 11. The layer according to claim 9, wherein the layer forming the bonding surface in the bonding step has the same composition on both the first substrate and the second substrate. Method for manufacturing semiconductor light emitting device. 12. A metal having a melting point lower than a growth temperature of a semiconductor epitaxial growth layer grown on the at least one of the first and second substrates is used, and a melting point higher than the growth temperature is used. And a semiconductor layer is epitaxially grown on the substrate at a predetermined growth temperature in a growth apparatus at the same time, and the contact resistance at the interface between the metal and the semiconductor substrate is lowered to form a metal electrode. The method for manufacturing a semiconductor light emitting device according to claim 9. 13. A metal electrode is formed by pre-depositing at least one kind of metal electrode material on a side surface of at least one of the first and second substrates opposite to a surface on which the layers are formed, 12. A method of manufacturing a semiconductor light emitting device according to claim 9, further comprising epitaxially growing a semiconductor layer on the surface of the substrate.