JP2002124738A - Semiconductor optical device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor optical device which is small in loss of optical output and is reliable in a high-output operation. SOLUTION: The semiconductor optical device comprises a substrate, a first conductivity type clad layer formed on the substrate, an active layer formed on the first conductivity type clad layer, and a second conductivity type clad layer formed on the active layer. The active layer includes an optical waveguide region,which is formed at the center in the longitudinal direction of the active layer, and optical confinement regions, which are formed on both sides of the optical waveguide region, are larger in band gap than the optical waveguide region,and are small in refractive index. The light confinement regions are lower in concentration of impurity than a region A of the second conductivity type clad layer that is positioned above the light confinement region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor optical device useful as a semiconductor laser or the like and a method for manufacturing the same, and more particularly to a semiconductor optical device having high reliability in high-power operation and a method for manufacturing the same.

[0002]

2. Description of the Related Art Semiconductor optical device devices are semi-rugged,
Because of their excellent characteristics such as high efficiency, wide wavelength selection range, and durability, they are widely used as light emitting elements such as semiconductor lasers and amplifiers. Conventional semiconductor optical device devices include a ridge buried inner stripe structure (hereinafter referred to as a “ridge buried type”) and a self-aligned waveguide type inner stripe structure (hereinafter referred to as a “self-aligned type”).
Are widely known.

[0003] The structure of a conventional semiconductor optical device and its manufacturing process will be described by taking a self-aligned semiconductor optical device as an example. FIG. 2 is a vertical perspective view of a conventionally known typical self-aligned semiconductor laser. First conductive type clad layer 3 on substrate 30
1. The active layer 32, the second conductivity type first cladding layer 33, and the oxidation preventing layer 34 are epitaxially grown in this order. Next, in order to form a light confinement region in the active layer 32,
Impurities are ion-implanted from above the oxidation preventing layer 34 and heat-treated at a predetermined temperature to diffuse the impurities. Then, the opening 3
6 is epitaxially grown, and a second-conductivity-type second cladding layer 37 and a contact layer 38 are formed on the opening 36 and the current blocking layer 35. Electrodes 39 and 40 are formed on the contact layer 38 and the substrate 30 as needed. As described above, in the semiconductor optical device device, impurities are generally added (doped) and heat treatment (annealing) is performed in the manufacturing process so that a wafer serving as a substrate for device formation has a desired electric resistivity.

[0004]

However, in the conventional semiconductor optical device, some disadvantages associated with the above-described impurity addition and heat treatment have been pointed out. For example, Japanese Patent Application Laid-Open No. Hei 10-233556 discloses a ridge-embedded semiconductor laser diode and a method of manufacturing the same. This ridge-embedded semiconductor laser diode has a disorder in the active layer by implanting Si ions into the cladding layer on both sides of the ridge waveguide and in the vicinity of the active layer and then performing a heat treatment to diffuse the Si atoms into the crystal. Has been caused. However, in this semiconductor laser diode, since a high concentration of impurities (Si) exists on both sides (first high refractive index region) of the active layer, light absorption loss is large and a leak current is liable to occur. Therefore, in this semiconductor laser diode, the threshold current increases, so that the current-to-light conversion efficiency is reduced, and the reliability of the semiconductor laser diode is deteriorated. Further, in this semiconductor laser diode, since Si ions are implanted into the vicinity of the active layer, dislocations due to ion implantation occur, and further, propagation of dislocations may occur. For this reason, a reduction in luminous efficiency, a carrier lifetime, a laser failure, and the like are induced, and the reliability as a laser diode cannot be maintained.
Particularly at high output, light damage (hereinafter “COD” (Catas
trophic optical damage)), making laser oscillation impossible.

On the other hand, Japanese Patent Application Laid-Open No. 10-150239 discloses a ridge stripe embedded semiconductor laser device. This semiconductor laser device has a p-type
In this case, Zn is contained as a type dopant, and mixed crystal is formed by a subsequent heat treatment. However, when the p-type impurity is added from the second p-type cladding layer and the heat treatment is performed, the p-type impurity in the first p-type cladding layer above the mixed crystal region is increased.
The type impurity concentration is higher than the impurity concentration in the first p-type cladding layer above the non-mixed crystal region. For this reason, the current at the time of energization tends to leak in the width direction (outside) of the first p-type cladding layer above the mixed crystal region, and current confinement cannot be performed effectively. In addition, since a high concentration of impurities (Zn) exists in the mixed crystal regions on both sides of the active layer, light absorption loss is large and a leak current is easily generated. Therefore, such a semiconductor laser device has a problem that the threshold current increases and the current-to-light conversion efficiency decreases, so that the reliability of the semiconductor laser deteriorates. Furthermore, the presence of a high concentration of p-type impurity (Zn) causes diffusion even during energization, so that the reliability during use, particularly the reliability during high output, has been a problem.

[0006] Under such circumstances, even a semiconductor optical device device which has been subjected to impurity addition and heat treatment, has a reliable semiconductor optical device device which does not cause the above-described problems, and in particular, has a small light absorption loss and a high level. It has been desired to develop a semiconductor optical device having high reliability during output operation. Thus, the present invention has been made in view of the above-mentioned conventional problems, and even in a semiconductor optical device device which has been subjected to impurity addition and heat treatment, current confinement can be effectively performed, and light absorption loss is reduced. It is another object of the present invention to provide a semiconductor optical device having high reliability at the time of high output.

[0007]

Means for Solving the Problems In order to solve the above-mentioned problems, the present inventors diligently study the impurity concentration and the diffusion of the impurities in the active layer and the cladding layer formed thereon due to the impurity addition and heat treatment. Stacked. It is generally said that the impurity addition and the heat treatment are performed after the impurity added by ion implantation or the like is diffused to the active layer to form a desired mixed crystal region. Regarding this point, the description of the heat treatment (annealing) in the above-mentioned Japanese Patent Application Laid-Open No. Hei 10-233556 states that "Since the ion implantation alone does not cause disordering of the active layer of the quantum well structure, Si atoms are introduced into the crystal by the heat treatment. This is because the active layer is disordered only after the diffusion.
(JP-A-10-233556, page 5, [0025])
It is clear from.

The present inventor has studied the change in the impurity concentration in the active layer and the clad layer formed thereon during the addition of impurities and the heat treatment, and as a result, has found a fact different from the conventional recognition. That is, when comparing the impurity concentrations in the active layer and the cladding layer when the mixed crystal region is formed in the active layer, surprisingly, even if there is a peak of the impurity concentration in the cladding layer, the active layer It was found that mixed crystal formation occurred. In addition, when the state of the active layer in the case where the clad layer has an impurity concentration peak was examined, it was found that an excellent mixed crystal region with few crystal lattice defects was obtained, and the present invention was completed.

That is, the present invention provides a substrate, a first conductivity type clad layer formed on the substrate, an active layer formed on the first conductivity type clad layer, and a second layer formed on the active layer.
A semiconductor optical device having a conductive clad layer, wherein the active layer is an optical waveguide region formed in a vertical direction,
A light confinement region formed on both sides of the light guide region and having a band gap larger than that of the light guide region and a smaller refractive index; and the impurity concentration of the light confinement region is just above the light confinement region. Wherein the impurity concentration is lower than the impurity concentration in the cladding layer region of the second conductivity type.

In a preferred embodiment of the semiconductor optical device according to the present invention, the impurity concentration of the light confinement region of the active layer is 5 × 10 ¹⁸ cm ⁻³ or less; The second conductive type clad layer region A has a higher resistance or a different conductive type than the second conductive type clad layer region B located directly above the optical waveguide region of the active layer. An aspect in which the active layer has a quantum well layer; an aspect in which the quantum well layer is subjected to compressive strain; an aspect in which In is included as a constituent element of the quantum well layer; the quantum well layer in which at least GaAs, AlGaAs,
InGaAs, AlGaInAs, GaInP, AlG
aInP, GaInAsP, AlGaInAsP, Ga
An embodiment comprising N or InGaN; an embodiment in which the active layer has a barrier layer and / or an optical guide layer sandwiching the quantum well layer, and the thickness of the barrier layer and / or the guide layer is larger than that of the quantum well layer; An embodiment containing Al as a constituent element of a barrier layer and / or a light guide layer sandwiching a well layer; an embodiment in which a quantum well layer in a light confinement region of an active layer is mixed crystal; An embodiment in which a window region in which the band gap of the quantum well layer is larger than the center of the optical waveguide region is formed near the end face; an embodiment in which the quantum well layer is mixed crystal in the window region; An aspect in which a current blocking layer is formed on the region A of the second conductivity type cladding layer; an aspect in which the current blocking layer is composed of at least a semiconductor layer of the first conductivity type or a high resistance. ; Half Aspect body optical device apparatus is a semiconductor laser; and the embodiment used as an optical fiber amplifier pumping source; semiconductor optical device apparatus aspect is a semiconductor optical amplifier.

Further, the present invention provides a step (a) of forming a substrate, a first conductive type clad layer, an active layer, and a second conductive type clad layer in this order, and a heat treatment after ion-implanting impurities. Forming a confinement region, and a method for manufacturing a semiconductor optical device.

In a preferred embodiment of the method for manufacturing a semiconductor optical device according to the present invention, the impurity concentration of the light confinement region of the active layer is lower than that of the region A of the second conductivity type clad layer located immediately above the light confinement region. A mode in which the impurity is ion-implanted so as to have a lower impurity concentration; a mode in which the ion implantation energy is 5 to 1000 keV when the thickness of the second conductivity type cladding layer is 0.01 to 1 μm;
The amount of ion implantation for impurity ion implantation is 0.5 ×
^{Embodiment in which} 10 ^-13 cm ^{-2 to} 20 × 10 ^-13 cm ^-2 is used; Embodiment in which the ion-implanted element is not substantially diffused into the active layer by heat treatment; An embodiment including a step of forming a surface protective film on the surface and removing the surface protective film after ion implantation; an embodiment in which the surface protective film is SiNx; and in step b, the surface of the second conductivity type cladding layer before heat treatment. An embodiment in which a coating layer is formed and heat treatment is performed and then the coating layer is removed; and an embodiment in which the coating layer is made of a Si-based amorphous.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor optical device and a method of manufacturing the same according to the present invention will be described in detail. The semiconductor optical device of the present invention comprises a substrate, a first conductivity type clad layer formed on the substrate, an active layer formed on the first conductivity type clad layer, and a second layer formed on the active layer. The active layer has a conductive type cladding layer, the active layer has an optical waveguide region formed at the center in the longitudinal direction of the active layer, and a band gap formed on both sides of the optical waveguide region. A light confinement region having a large refractive index and a small refractive index, wherein the impurity concentration in the light confinement region is lower than the impurity concentration in the region A of the second conductivity type clad layer located immediately above the light confinement region. It is characterized by. The semiconductor optical device of the present invention may appropriately have a layer formed by a normal semiconductor optical device in addition to these layers.

In this specification, the expression “Y layer formed on the X layer” refers to the case where the Y layer is formed such that the bottom surface of the Y layer is in contact with the upper surface of the X layer, and the case where the Y layer is formed on the upper surface of the X layer. In which one or more layers are formed and a Y layer is further formed on that layer. The above expression also includes a case where the top surface of the X layer and the bottom surface of the Y layer are partially in contact with each other and one or more layers exist between the X layer and the Y layer in other portions. The expression “region A of the second conductivity type cladding layer” is a region of the second conductivity type cladding layer located directly above the light confinement region of the active layer and in which the ion-implanted impurity exists. Say. Further, the expression “region B of the second conductivity type cladding layer” refers to a region of the second conductivity type cladding layer that is located directly above the optical waveguide region of the active layer and in which impurity ion implantation is not performed. Say. These specific aspects are apparent from the following description of each layer and specific examples of the examples.

FIG. 1A is a perspective view of an example of a self-aligned semiconductor optical device according to the present invention.
(B) is a perspective view of an example of a ridge buried type of the semiconductor optical device device of the present invention. The structure of an example of the self-aligned type shown in FIG. 1A is schematically obtained by laminating a first conductive type clad layer 2, an active layer 3, and a second conductive type clad layer 4 on a substrate 1 made of a compound semiconductor. A current blocking layer 6 and a surface protection layer 7 which are opened in a stripe shape via an antioxidant layer 5 are laminated thereon. Further, the current blocking layer 6
A second conductivity type cladding layer 9 is formed so as to be laminated on the opening 8 having the opening and the current blocking layer 6 on both sides of the opening 8, and the contact layer 1 is formed on the second conductivity type cladding layer 9.
0 is formed.

On the other hand, the structure of an example of the ridge buried type shown in FIG. 1B is schematically shown on a substrate 15 made of a compound semiconductor.
A first conductive type clad layer 16, an active layer 17, and a second conductive type first clad layer 18 are laminated, and an oxidation preventing layer 1 is formed thereon.
9, the surface protection layer 20 is laminated. Furthermore, the second conductive type second cladding layer 21 and the contact layer 22
Are laminated.

In FIGS. 1A and 1B, the substrates 1 and 15 constituting the semiconductor optical device of the present invention are those on which a crystal having a double hetero structure can be grown. There is no particular limitation on the conductivity or the material. Preferred is a conductive substrate. Specifically, GaAs suitable for growing a crystal thin film on a substrate,
InP, GaP, GaN, ZnSe, ZnO, Si, A
It is preferable to use a crystal substrate such as l ₂ O ₃ , particularly a crystal substrate having a zinc blende structure. In that case, the substrate crystal growth surface is preferably a low-order surface or a surface crystallographically equivalent thereto,
The (100) plane is most preferred. In this specification, the (100) plane is not necessarily strictly a (100) just plane, but includes a case having an off-angle of about 30 ° at the maximum. The upper limit of the off-angle is preferably 30 ° or less, more preferably 16 ° or less. The lower limit is preferably 0.5 ° or more, more preferably 2 ° or more, still more preferably 6 ° or more, and most preferably 10 ° or more.

The substrates 1 and 15 may be hexagonal substrates, for example, substrates made of Al ₂ O ₃ , 6H—SiC, or the like.

On the substrates 1 and 15, a thickness of 0.2 mm is usually used in order to prevent defects of the substrate from being introduced into the epitaxial growth layer.
It is preferable to form a buffer layer having a thickness of about 2 μm. In this specification, “to” means a range that includes numerical values described before and after it as a minimum value and a maximum value, respectively.

On the substrates 1 and 15, a compound semiconductor layer including the active layers 3 and 17 is formed. The compound semiconductor layer includes a layer having a lower refractive index than the active layer above and below the active layer,
Among them, the layers on the substrates 1 and 15 side are the first conductivity type cladding layer,
The other layer on the epitaxial side functions as a second conductivity type cladding layer. The magnitude relationship between the refractive indices can be adjusted by appropriately selecting the material composition of each layer by a method known to those skilled in the art. For example, Al _x Ga _1-x As,
(Al _x Ga _{1 -x} ) _0.5 In _0.5 P, (Al _x Ga _{1 -x} ) _0.5
The refractive index can be adjusted by changing the Al composition such as In _0.5 As and Al _x Ga ₁ -xN.

The first conductivity type cladding layers 2 and 16 are formed of a material having a lower refractive index than the active layers 1 and 15. Further, it is preferable that the refractive index of the first conductive type clad layers 2 and 16 is larger than the refractive index of the second conductive type clad layer.
For example, first conductivity type InP, GaInP, AlGaI
nP, AlInP, AlGaAs, AlGaAsP, A
lGaInAs, GaInAsP, GaN, AlGa
N, AlGaInN, BeMgZnSe, MgZnSS
e, CdZnSeTe, ZnO, MgZnO, and general III-V and II-VI semiconductors such as MgO can be used. The lower limit of the carrier concentration of the first conductivity type cladding layers 2 and 16 is preferably 1 × 10 ¹⁷ cm ⁻³ or more, and 3 × 10 ¹⁷ cm ⁻³ or more.
More preferably ¹⁷ cm ^-3 or more, and most preferably 5 × 10 ¹⁷ cm ^-3 or more. The upper limit is preferably 2 × 10 ²⁰ cm ^-3 or less, more preferably 2 × 10 ¹⁹ cm ^-3 or less, and 5 × 10 ¹⁸
cm ^-3 or less is most preferred.

The first conductivity type cladding layers 2 and 16 may be formed of a single layer or may be formed of two or more layers. When composed of a single layer, the lower limit of the thickness is 0.4
μm or more is preferable, and 0.6 μm or more is more preferable.
0.7 μm or more is more preferable. The upper limit of the thickness is 5
μm or less, preferably 4 μm or less, more preferably 3 μm
m or less is more preferable.

The first conductivity type cladding layers 2 and 16 may be composed of a plurality of layers.
A cladding layer made of P, AlGaInP or AlInP, and a cladding layer made of AlGaAs or AlGaAsP of the first conductivity type formed on the substrate side of the layer can be exemplified. At this time, the thickness of the layer on the active layer side is preferably thin, and the lower limit of the thickness is preferably 0.01 μm or more, and more preferably 0.05 μm or more. The upper limit is preferably 0.5 μm or less,
0.3 μm or less is more preferable. The carrier concentration of the layers on the substrates 1 and 15 side is 2 × 10 ¹⁷ cm ⁻³ as the lower limit.
^Or more, and more preferably 5 × 10 ¹⁷ cm ⁻³ or more. The upper limit is preferably 2 × 10 ²⁰ cm ⁻³ or less,
It is more preferably 5 × 10 ¹⁹ cm ⁻³ or less.

The structure of the active layers 3 and 17 constituting the semiconductor optical device of this embodiment is not particularly limited. FIG.
One example of (a) shows an embodiment having a double quantum well (DQW) structure. Specifically, the double quantum well (DQW) structure has a light guide layer (non-doped) 51, a quantum well layer (non-doped) 52, a barrier layer (non-doped) 53, a quantum well layer (non-doped) 54, and a light guide layer (non-doped). (Non-doped) 55 are sequentially laminated. In addition to the double quantum well (DQW) structure, for example, a single quantum well structure (SQW) composed of a quantum well layer and a light confinement layer sandwiching the quantum well layer from above and below, and three or more quantum well layers and A multi-quantum well structure having a barrier layer sandwiched therebetween and an optical guide layer stacked above the uppermost quantum well layer and below the lowermost quantum well layer may be used. By making the active layers 3 and 17 have a quantum well structure, a shorter wavelength (630 nm to 660 nm) and a lower threshold can be achieved as compared with a single bulk active layer.

As the material of the active layers 3 and 17, other elements can be appropriately selected as long as they contain an In element which is a group V element. For example, the material of the quantum well layer is GaAs, AlGaAs, InGaAs.
s, AlGaInAs, GaInP, AlGaInP,
GaInAsP, AlGaInAsP, GaN, InG
aN, AlGaN, AlGaInN, GaInAsN, and the like. In the case of a material containing Ga and In as constituent elements, a natural superlattice is easily formed, so that the effect of controlling the natural superlattice by using an off-substrate can be increased.

The active layers 3 and 17 are formed in the optical waveguide region 6 formed at the center in the vertical direction by ion implantation and heat treatment described later.
0 and light confinement regions 61 formed on both sides of the optical waveguide region. The optical waveguide region 60 includes the light confinement region 6.
This is a region formed of a layer having a refractive index slightly higher than that of 1, and is free from impurities due to ion implantation and heat treatment. The optical waveguide region can efficiently confine the light and effectively confine the oscillation light emitted from the active layer. Further, the optical waveguide region 60 can be formed so that the lateral width is different between the central portion and the vicinity of the end face. In order to obtain stable light oscillation (stabilization of the horizontal and transverse modes), the upper limit of the lateral length of the optical waveguide region is preferably 7 μm or less, more preferably 6 μm or less, and most preferably 5 μm or less. The lower limit is preferably 0.5 μm or more,
1 μm or more is more preferable, and 1.5 μm or more is most preferable. The light confinement regions 61 are formed on both sides of the light guide region 60 so that light can be confined in the light guide region 60. The optical confinement region 61 has a band gap larger than that of the optical waveguide region 60 and a refractive index smaller than that of the optical waveguide region 60 so that the oscillation light can be efficiently confined in the optical waveguide region 60. The size of the band gap is not particularly limited, and can be appropriately determined according to the length of the wavelength of the oscillation light. The refractive index is not particularly limited as long as light can be confined in the optical waveguide region. The optical confinement region 61 has a second conductivity type clad layer 4 (described later) formed by ion implantation of impurities and heat treatment.
The impurity concentration is set lower than that of the region A of No. 18. Considering the easiness of light absorption due to the increase of the impurity concentration and the easiness of current leakage during energization, the upper limit of the impurity concentration of the light confinement region 61 is preferably 5 × 10 ¹⁸ cm ⁻³ or less. The upper limit is more preferably 4 × 10 ¹⁸ cm ⁻³ or less, and even more preferably 3 × 10 ¹⁸ cm ⁻³ or less.

When the active layers 3 and 17 have a quantum well structure, it is preferable to have the following structure from the viewpoint of facilitating the mixed crystal formation of the quantum well structure. (1) The active layers 3 and 17 have a single well layer (single quantum well) because the amount of change in composition can be increased before and after mixed crystal formation. (2) When the active layers 3 and 17 have a plurality of well layers (multiple quantum wells), the active layers 3 and 17 are sandwiched between the mixed crystal composition well layers in order to suppress the reduction of the band gap near the center of the mixed crystal region. The thickness of the formed barrier layer 53 is larger than that of the well layers 52 and 54. (3) Compressive strain is applied to the well layer in order to increase the band gap change before and after mixed crystal formation. (4) I that easily diffuses at a relatively low temperature into the constituent elements of the well layer
n must be included. (5) The light guide layers 51 and 55 formed above and / or below the barrier layer 53 or the active layers 3 and 17 sandwiching the well layer do not include In for reducing the band gap. (6) The barrier layer 53 or the light guide layer 51 sandwiching the well layer,
The constituent elements 55 contain Al for increasing the band gap.

In the semiconductor optical device of the present invention, FIG.
As shown in (c), the window region 25 in which the band gap of the quantum well layer is larger than the central portion of the optical waveguide region near at least one end face of the optical waveguide region of the active layer 3 can be formed. The window region 25 is a disordered region, and the end face of the optical waveguide region of the active layer 3 is formed of a mixed crystal region. The mixed crystal region is formed by ion implantation and heat treatment or impurity diffusion. It is preferable to use ion implantation and heat treatment for forming the light confinement region 61.
In FIG. 1, a region indicated by oblique lines is a region where ion implantation has been performed. Usually, the active layer 3 has a double quantum well (D
QB), it has a band gap as shown in FIG. 4B, but has disordered structure.
As shown in (a), the band gap is larger than that of a normal active layer 3 (shown by a dotted line). Therefore, in the active layer 3, the light confinement region 61 is
Band gap is larger and the refractive index is smaller. Further, by forming the window region, absorption of light waves at the light output end face can be suppressed, and COD can be prevented beforehand.

As shown in FIGS. 1A to 1C, the second conductivity type cladding layers 4 and 18 are formed on the active layers 3 and 17. In the semiconductor optical device of the present invention, at least one second conductive type clad layer is formed. The second conductivity type cladding layer has two regions, that is, a region A (62) and a region B (63), and the region A (62) has a region B (6).
It is preferable that the resistance is higher than 3) or that the region A (62) and the region B (63) have different conductivity types. If the region A (62) has a higher resistance or a different conductivity type than the region B (63), the light distribution (particularly, the light distribution in the lateral direction) can be controlled, and the current at the time of energization can be reduced.
(63) can easily flow, and the current blocking function can be improved.

In the present invention, the second conductivity type cladding layer comprises:
Two or more layers may be formed. A case where two second conductive type cladding layers are formed will be described with reference to FIG. In FIG. 1, the second conductive type first clad layers 4 and 18 and the second conductive type second clad layers 9 and 21 are arranged in this order from the closest to the active layers 3 and 17.
A preferred embodiment having two layers is shown.

The second conductive type first cladding layers 4 and 18 are formed of a material having a lower refractive index than the active layers 3 and 17.
For example, second conductivity type InP, GaInP, AlGaI
nP, AlInP, AlGaAs, AlGaAsP, A
lGaInAs, GaInAsP, GaN, AlGa
N, AlGaInN, BeMgZnSe, MgZnSS
e, CdZnSeTe, ZnO, MgZnO, and general III-V and II-VI semiconductors such as MgO can be used. When the second conductivity type first cladding layers 4 and 18 are made of a III-V compound semiconductor containing Al, substantially the entire surface on which growth is possible is made of GaAs, GaAsP or Ga.
Does not contain Al such as InAs, GaInP, and GaInN
Covering with a III-V compound semiconductor is preferable because surface oxidation can be prevented.

The second conductive type first cladding layers 4, 18
Rear concentration, lower limit is 1 × 10¹⁷cm ^-3More preferably,
3 × 10¹⁷cm^-3More preferably, 5 × 10¹⁷cm
^-3The above is most preferred. The upper limit is 5 × 10¹⁸cm^-3The following
Preferably 3 × 10¹⁸cm^-3The following is more preferable, and 2 ×
10¹⁸cm^-3The following are most preferred. As the lower limit of thickness
0.01 μm or more is preferable, and 0.05 μm or more is more preferable.
Preferably, it is at least 0.07 μm. Upper limit
Is preferably 0.5 μm or less, more preferably 0.4 μm or less.
More preferably, it is most preferably 0.2 μm or less.

The second conductive type first cladding layers 4 and 18 are formed on the active layers 3 and 17. In a preferred embodiment of the present invention, the refractive index of the second conductive type first cladding layers 4 and 18 is smaller than the refractive index of the first conductive type cladding layers 2 and 16. By adopting such an embodiment, the light distribution (near-field image) can be controlled so that light effectively seeps from the active layer to the light guide layer side. Further, since the optical waveguide loss from the active region (the portion where the active layer is present) to the impurity diffusion region can be reduced, it is possible to achieve improvement in laser characteristics and reliability in high-power operation.

By forming the antioxidant layers 5 and 19 on the second conductive type first cladding layers 4 and 18, when the second conductive type second cladding layers 9 and 21 are regrown, the regrowth interface is formed. As a result, it is possible to easily prevent the generation of a high-resistance layer that increases the passage resistance. In addition, the antioxidant layer 5,
19 may function as an etching stop layer.

The material of the antioxidant layers 5 and 19 is not particularly limited as long as it is hardly oxidized or easily oxidized and cleaned. The material of the antioxidant layers 5 and 19 is generally selected from materials having a larger band gap than the material of the active layer. However, even if the material has a smaller band gap than the material of the active layer, the thickness is 50 nm.
Or less, more preferably 30 nm or less, most preferably 1 nm or less.
If it is 0 nm or less, it can be used because light absorption can be substantially ignored. Specifically, a group III-V compound semiconductor layer having a low content of an easily oxidizable element such as Al (about 0.3 or less) may be mentioned, and GaAs may be selected. Further, it is preferable that the antioxidant layers 5 and 19 are made so as not to absorb light from the active layers 3 and 17 by selecting a material and a thickness. An embodiment in which it is transparent is mentioned.

In the semiconductor optical device having the structure of the present invention, ion implantation and heat treatment (annealing) are performed from above the second conductive type cladding layers 4 and 18 so that the region A of the second conductive cladding layers 4 and 18 is formed. (62) and the active layer 3,
Seventeen light confinement regions 61 can be created. Further, the window region 25 in the present invention can be formed by ion implantation and thermal diffusion. The impurity (ion source) diffused by ion implantation is not particularly limited as long as it functions as a dopant. For example, Si, F, Al,
B, C, N, P, S, As, and Ga can be mentioned. More preferred are Si, F, B, C, N, P, As.
And more preferred are Si, F, B and N;
Most preferred is Si.

If the ion implantation amount (dose amount) in ion implantation is too small, it becomes difficult for the active layer to form a mixed crystal. On the other hand, if the amount is too large, the impurity concentration in the active layer becomes too high, and the active layer is easily affected by quality deterioration due to the regrowth interface, leading to a decrease in controllability of the front position and an increase in leak current at the end. Problem. In particular, if impurities diffuse to a layer having a relatively small band gap below the second conductivity type cladding layers 4 and 18, the increase in leakage current increases and the performance as a light emitting element is greatly impaired.

In consideration of these, the ion implantation amount (dose amount) in the case of ion implantation is 0.1 × 1 as the lower limit.
0 ¹³ cm ⁻² or more is preferable, 0.5 × 10 ¹³ cm ⁻² or more is more preferable, and 0.7 × 10 ¹³ cm ⁻² or more is most preferable. The upper limit is preferably 20 × 10 ¹³ cm ⁻² or less, more preferably 15 × 10 ¹³ cm ⁻² or less, and 10 × 1 cm ² or less.
0 ¹³ cm ^-2 or less is most preferred.

In general, the profile of ion implantation into a solid very closely matches the Gaussian distribution, especially near the peak. According to the study results of the present inventors, when the dose amount is constant, if the peak position of the concentration distribution is injected into the vicinity of the light confinement region 61 of the active layer or into the light confinement region 61, the mixed crystal hardly occurs. Rather, rather than the light confinement region 61 of the active layer, the second conductivity type cladding layers 4, 1
It was found that setting the injection profile so that the concentration peak position was within the region A (62) of No. 8 promoted the mixed crystal formation at the same dose. It has also been found that in the heat treatment after implantation, mixed crystals occur inside the active layer even though the implanted atoms do not diffuse to the active layer side. From this, it is possible to form a mixed crystal even if impurities do not diffuse during heat treatment after ion implantation. In the conventional diffusion of impurities into the active layer, light absorption (internal loss is greatly increased) due to impurities particularly in the end window region and p
Although a problem such as an increase in leakage current at the end due to the shift of the n-junction position has occurred, the present invention solves the conventional problem because it does not require substantial impurity diffusion into the active layer. can do.

From the above, from the viewpoint of easiness of mixed crystal formation and reduction of damage to the active layer, the concentration peak position of the injection profile is more second than the light confinement region 61 of the active layer.
It is preferably in the region A (62) of the conductive type cladding layers 4, 18. The concentration peak position of the injection profile is
It can be controlled by adjusting the energy to be implanted according to the distance from the epitaxial surface to be implanted to the active layer. Specifically, when the distance from the implantation surface to the active layer is 0.01 to 1 μm, the ion implantation energy for ion implantation is 5
It is preferable to set it to 1000 keV. More preferably, the distance from the injection surface to the active layer is 0.02-0.5.
In the case of μm, the ion implantation energy for ion implantation is 10 to 500 keV, and most preferably, the distance from the implantation surface to the active layer is 0.0
When the thickness is 5 to 0.3 μm, the ion implantation energy for ion implantation is set to 20 to 300 keV.

According to the present invention, before ion implantation of an impurity, a surface protective film can be formed on a portion where the impurity is not doped by ion implantation. When the surface protective film is formed, the material of the surface protective film is not particularly limited as long as it satisfies the condition that the dopant does not pass during ion implantation. Specifically, a dielectric, a photoresist, or the like can be used as the surface protective film. In the case of a dielectric, for example, SiN
x film, SiO ₂ film, SiON film, Al ₂ O ₃ film, ZnO
A group consisting of a film, a SiC film, and amorphous Si. Preferably, SiNx film, SiO ₂ film, S
iON film, most preferably SiNx.
When a surface protective film is formed, the surface protective film is removed before heat treatment. The method for removing the surface protective film is not particularly limited as long as the surface protective film can be completely removed. Therefore, a commonly used etching method can be used, and examples thereof include dry etching, wet etching, reactive ion etching, and plasma etching.

The ion implantation front at the end of the opening needs to be lower than the quantum well layer in the active layer 23 when the mixed crystal is formed, and has a larger band gap than the active layers 3 and 17. It is preferable to form it in the first conductivity type cladding layers 2 and 16 from the viewpoint of suppressing current leakage.

In the semiconductor optical device having the structure of the present invention, in addition to the above-described ion implantation from the upper part of the second conductivity type clad layer, the ion implantation after forming the block layer 6 and the surface protection layer 7 which will be described later. An injection can also be performed. For example, in the example shown in FIG. 1, impurities can be diffused by ion implantation from the antioxidant layers 5 and 19 at both ends of the optical waveguide region and from the surface protection layers 7 and 20 at both ends of the light confinement region. it can. At both ends of the optical waveguide region, the impurities can reach the active layers 3 and 17 through the relatively thin antioxidant layers 5 and 19 and the second conductive type first cladding layers 4 and 18. Therefore, it is possible to easily improve the position controllability of the ion implantation front and reduce the leak current at the end. In addition, at both ends of the light confinement region, the light can pass through the surface protection layers 7 and 20 and into the below-described current blocking layer 6 below.

The heat treatment (annealing) method in the present invention is not particularly limited as long as the window structure region can be formed after ion implantation. Therefore, a method used for normal annealing can be used, for example, hydrogen annealing, rapid thermal annealing (Rapid Thermal Annealing).
Anneal) and a rapid thermal process.

In the heat treatment after the ion implantation, the window region can be formed by adjusting the temperature and time of the heat treatment. The upper limit of the annealing temperature of the present invention is 1000.
° C or lower, more preferably 950 ° C or lower, and even more preferably 900 ° C or lower. The lower limit is preferably at least 600 ° C, more preferably at least 650 ° C,
More preferably, it is 0 ° C. or higher. The upper limit of the annealing time is preferably 60 minutes or less.
The time is more preferably 0 minutes or less, and even more preferably 15 minutes or less. The lower limit of the annealing time is preferably 5 seconds or more, more preferably 10 seconds or more, and even more preferably 30 seconds or more.

Prior to the formation of the window region by the heat treatment of the present invention, the surfaces of the antioxidant layers 5 and 19 may be covered with a coating layer in advance. When annealing is performed, defects of group V elements (such as As and P) usually occur on the surfaces of the epitaxial growth layers such as the oxidation prevention layers 5 and 19.
Such defects may degrade the surface state and have a significant effect on subsequent epitaxial growth. Therefore, in order to prevent such a deficiency of the group V element, annealing is performed in an atmosphere of a group V element (As, P, or the like), or annealing is performed after a coating layer is further formed on the surface of the epitaxial growth layer. It is preferred to do so. When forming a coating layer, the material of the coating layer is not particularly limited as long as it has heat resistance, stability, and the like. It is also possible to use amorphous from the viewpoint of easy formation and processing of a thin film. Specifically, SiNx, SiO ₂ ,
SiON, Al ₂ O ₃ , ZnO, SiC and the like can be mentioned.

When the coating layer is formed, the coating layer is removed before forming the second-conductivity-type second cladding layers 9 and 21 described later. The method for removing the coating layer is not particularly limited as long as the coating layer can be completely removed. Therefore, a commonly used etching method can be used, and examples thereof include dry etching, wet etching, reactive ion etching, and plasma etching.

In the semiconductor optical device of the present invention, the current blocking layer 6 can be further formed on the second conductivity type cladding layer. The relationship between the second conductive cladding layer and the current blocking layer will be described using an example of a self-aligned type shown in FIG. The current block layer 6 is preferably formed on the region A (62) of the second conductivity type clad layer 4 from the viewpoint of preventing current constriction and generation of leak current.
The current blocking layer 6 has an opening 8, and a current is injected into the active layer 3 from the opening 8.

The material of the current blocking layer 6 is not particularly limited as long as it has a current blocking function. When a semiconductor is used as the material of the current blocking layer 6, the heat conductivity is higher than that of the dielectric film, so that the heat dissipation is good, the cleavage is good, and the flattening is easy, and the junction is easy to assemble. Since the contact layer can be easily formed on the entire surface, there is an advantage that the contact resistance can be easily reduced.

The refractive index of the current blocking layer 6 is preferably lower than the refractive index of the second conductivity type second cladding layer 9 made of AlGaAs or AlGaAsP sandwiched between the current blocking layers 6 (real refractive index guide structure). ). By controlling such a refractive index, it becomes possible to reduce the operating current as compared with the conventional loss guide structure. When the current blocking layer is a compound semiconductor, the lower limit of the refractive index difference between the current blocking layer 6 and the second conductive type second cladding layer 9 is preferably 0.001 or more, more preferably 0.003 or more, and 0.007 or more. The above is most preferred. The upper limit is 1.0
Is preferably 0.5 or less, more preferably 0.5 or less, and most preferably 0.1 or less. When the current blocking layer 6 is a dielectric,
The lower limit is preferably 0.1 or more, more preferably 0.3 or more, and most preferably 0.7 or more. The upper limit is preferably 3.0 or less, more preferably 2.5 or less, and most preferably 1.8 or less.

The material of the current blocking layer 6 may have a lower refractive index than that of the second cladding layer 9 of the second conductivity type, or may be made of GaAs.
Considering lattice matching with the substrate, AlGa
As or Al _y Ga _1-y As (0.35 ≦ y ≦ 1) can also be used. However, when the Al composition is too close to AlAs, deliquescentness is exhibited, and since it is necessary to make the refractive index lower than that of the second cladding layer 9 of the second conductivity type, Al
The y value as the lower limit of the composition is 0.35 or more, preferably 0.37 or more, and more preferably 0.40 or more. Further, the y value as the upper limit is 1 or less, preferably 0.9 or less, and more preferably 0.8 or less.

The current blocking layer 6 is formed from two or more layers having different refractive indices, carrier concentrations or conductivity types in order to control the light distribution (particularly the light distribution in the lateral direction) and to improve the current blocking function. May be. By forming the surface protective layer 7 on the current blocking layer 6, it is possible to suppress surface oxidation or to protect the surface in the process. Although the conductivity type of the surface protective layer 7 is not particularly limited, the current blocking function can be improved by using the second conductivity type.

The conductivity type of the current blocking layer 6 is any of the first conductivity type or high resistance (undoped or doped with impurities (O, Cr, Fe, etc.) that form a deep order), or a combination of the two. Or a plurality of layers having different conductivity types or different compositions.
For example, a current blocking layer formed in the order of the second conductivity type or high resistance semiconductor layer and the first conductivity type semiconductor layer from the side close to the active layer 3 can be preferably used. Further, if the thickness is too small, it may cause a problem in blocking the current. Therefore, the thickness is preferably 0.1 μm or more, and more preferably 0.3 μm or more. On the other hand, if the thickness is too large, the passage resistance increases, so the upper limit is preferably 2 μm or less, more preferably 1 μm or less. In consideration of the size of the element, it is preferable to select from a range of about 0.3 to 1 μm.

The method for forming the current blocking layer 6 is as follows.
Is not particularly limited as long as it can be formed. When the current block layer 6 is formed by selective growth, the source gas, the growth temperature,
If you choose the atmosphere, you can form a thin film in a self-aligned manner,
It is particularly preferable because it has advantages such as easy adaptation to element miniaturization.

As the upper layer of the current blocking layer 6, the current blocking layer 6 inside the opening 8 and at least on both sides of the opening 8
The second conductivity type second cladding layer 9 is formed so as to reach the upper part. The second conductivity type second cladding layer 9 is formed so as to cover the entire upper surface of the opening 8 and extend at least partially on the current blocking layer 6 on both sides of the opening 8. In the case of the ridge buried type, the oxidation preventing layer 19 is used.
And a second conductive second cladding layer 21 on the surface protection layer 20.
Is formed.

The second conductive type second clad layers 9 and 21 have a capacitor.
Rear concentration, lower limit is 3 × 10¹⁷cm ^-3More preferably,
5 × 10¹⁷cm^-3More preferably, 7 × 10¹⁷cm
^-3The above is most preferred. The upper limit is 1 × 10¹⁹cm^-3Less than
Lower is preferred, 5 × 10¹⁸cm^-3The following is more preferable,
3 × 10¹⁸cm^-3The following are most preferred.

When the thickness of the second conductive type second cladding layers 9 and 21 is too small, the light confinement becomes insufficient, and when the thickness is too large, the passing resistance increases. For this reason, the lower limit of the thickness of the second conductive type second cladding layers 9 and 21 is set to 0.1 mm.
5 μm or more is preferable, and 1.0 μm or more is more preferable. The upper limit is preferably 3.0 μm or less, more preferably 2.0 μm or less.

When an electrode is further formed after forming the second cladding layers 9 and 21 of the second conductivity type, a low resistance (high carrier concentration) is used in order to reduce the contact resistance with the electrode material.
It is preferable to form the contact layers 10 and 22 of FIG.
In particular, it is preferable to form the electrodes after forming the contact layers 10 and 22 on the entire surface of the uppermost layer on which the electrodes are to be formed.

At this time, the material of the contact layers 10 and 22 is usually selected from materials having a smaller band gap than that of the cladding layer, and has a low resistance and an appropriate carrier density in order to obtain ohmic contact with the metal electrode. Is preferred. For example, GaAs, GaInAs, GaInP, GaIn
AsP, GaN, GaInN, GaNAs, GaNP,
ZnSe, ZnSSe, CdZnSeTe, ZnO, C
A general III-V or II-VI semiconductor such as dZnO can be used. The lower limit of the carrier density is 1 × 10 ¹⁸
cm ^-3 or more, more preferably 3 × 10 ¹⁸ cm ^-3 or more, and most preferably 5 × 10 ¹⁸ cm ^-3 or more. The upper limit is preferably 2 × 10 ²⁰ cm ^-3 or less, and 5 × 10 ¹⁹ cm
^-3 or less, more preferably 3 × 10 ¹⁹ cm ^-3 or less. The lower limit of the thickness of the contact layer 29 is 0.1 μm.
It is preferably at least 0.3 μm, more preferably at least 0.5 μm. The upper limit of the thickness is preferably 10 μm or less, more preferably 6 μm or less, and particularly preferably 4 μm or less.

Next, an opening 8 formed in the current block layer 6 in the self-aligned type semiconductor optical device.
Will be described.

When the opening 8 of the current blocking layer 6 is smaller on the lower side (on the active layer 3 side) than on the upper side (on the side of the contact layer 10), the passage resistance is reduced (operating voltage and heat generation). Is preferred from the viewpoint of reduction of Current block layer 6
Is formed on the end window structure region, leakage current in the end window structure region can be eliminated. Further, by forming the current block layer 6 further inside the end window structure region, current injection to the end of the active layer 23 can be suppressed. Thereby, deterioration in the end region (particularly, end surface deterioration) can be reduced.

The opening 8 of the current block layer 6 may be a stripe-shaped opening extending to both ends, or extending to one end but extending to the other end. The opening may not be provided. When the opening is a stripe-shaped opening extending to both ends, light control in the end window structure region becomes easier, and the spread of light in the lateral direction on the end face can be reduced. On the other hand, if the opening is formed in a portion that is somewhat inside from the end face, current can be made non-injected near the end face, preventing recombination of current at the end face and preventing the cladding layer etc. Can be minimized. It is preferable that the structure of the opening is appropriately determined according to the purpose of use while taking such advantages into consideration.

The direction of the off angle depends on the current blocking layer 6.
A direction within ± 30 ° from a direction perpendicular to a direction (longitudinal direction) in which the opening 8 formed in the substrate extends is ± 7 °.
Direction is more preferable, and a direction within ± 2 ° is most preferable. When the plane orientation of the substrate 1 is (100), the direction of the opening 8 is [0-11] or a direction equivalent thereto, and the off-angle direction is ± 30 degrees from the [011] direction or a direction equivalent thereto. Is preferably within ± 7 °, more preferably ± 7 °, and most preferably ± 2 °. In this specification, the term “[011] direction” refers to a plane existing between the (100) plane and the (011) plane in general III-V and II-VI semiconductors. The [011] direction is defined as a surface on which a group III or group II element appears.

In the embodiment of the present invention, the above-mentioned opening is [01].
-1] direction. For example, when the opening extends in the [011] direction or a direction crystallographically equivalent thereto, for example, the growth rate can be made anisotropic depending on the growth conditions. 1
11) Almost no growth can occur on the B-plane. By forming the stripe-shaped protective film in the [011] direction, a current block layer having the (111) B plane as a side surface can be formed.

For the same reason, when a wurtzite type substrate is used, the direction in which the opening extends is, for example, (0
On the (001) plane, [11-20] or [1-100] is preferable. HVPE (Hydride Vapor Phase Epitaxy)
May be in either direction, but in MOVPE [11-
20] direction is more preferable.

In designing the semiconductor optical device of the present invention, first, the thickness of the active layer and the composition of the cladding layer are determined in order to obtain a desired vertical divergence angle. Usually, when the vertical divergence angle is reduced, light seepage from the active layer to the cladding layer is promoted, the light density at the end face is reduced, and the optical damage (COD) level at the output end face can be improved. When high-output operation is required, it is set relatively narrow, but the lower limit is to suppress an increase in oscillation threshold current due to a reduction in light confinement in the active layer and a decrease in temperature characteristics due to carrier overflow. There is a limit, and the lower limit is preferably 15 ° or more, more preferably 17 ° or more, and most preferably 19 ° or more. Upper limit is 33 °
Or less, more preferably 31 ° or less, and most preferably 30 ° or less.

Next, when the vertical divergence angle is determined, the structural parameters that largely govern the high output characteristics are the distance dp between the active layer and the current blocking layer and the width at the bottom of the opening (hereinafter referred to as “opening width”) W Becomes When only the second conductivity type first cladding layer exists between the active layer and the current blocking layer, dp is the thickness of the second conductivity type first cladding layer. When the active layer has a quantum well structure, the distance between the active layer closest to the current block layer and the current block layer is dp.

The upper limit of dp is preferably 0.50 μm or less, more preferably 0.40 μm or less, and 0.3
0 μm or less is most preferable. The lower limit is preferably 0.03 μm or more, more preferably 0.05 μm or more.
It is most preferably at least 07 μm. However, if the purpose of use (where the spread angle is set, etc.), material system (refractive index, resistivity, etc.) is different, the above-mentioned optimum range is slightly shifted. It should also be noted that this optimum range affects each of the above structural parameters.

The upper limit of the opening width W at the opening bottom is 1
It is preferably not more than 000 μm, more preferably not more than 500 μm. The lower limit is preferably 1 μm or more, more preferably 1.5 μm or more, and most preferably 2 μm or more. Further, in order to make the transverse mode a single mode (transverse light intensity distribution of a single peak), W cannot be made too large from the viewpoint of cutoff of a higher-order mode and prevention of spatial hole burning. The upper limit of W is preferably 7 μm or less,
5 μm or less is more preferable, and 3 μm or less is particularly preferable.

In order to realize a high output operation with an optical output of 300 mW or more, it is effective to widen the opening width W at the bottom of the opening from the viewpoint of reducing the light density at the end face. It is preferable to reduce the width of the opening from the viewpoint of reducing the waveguide loss. Therefore, by making the opening width W2 near the center, which is the gain region, relatively small, and making the opening width W1 near the ends relatively wide, it is possible to simultaneously achieve low operation current and high output operation. In addition, high reliability can be ensured (FIG. 4A). That is, the upper limit of the end (cleavage plane) width W1 is 1000.
μm or less, and more preferably 500 μm or less. The lower limit is preferably 2 μm or more, more preferably 3 μm or more. Center width W
As for 2, the upper limit is preferably 100 μm or less, more preferably 50 μm or less. The lower limit is preferably 1 μm or more, more preferably 1.5 μm or more, and most preferably 2 μm or more. The upper limit of the difference between the end width W1 and the center width W2 is preferably 1000 μm or less, more preferably 500 μm or less. The lower limit is preferably 0.2 μm or more, more preferably 0.5 μm or more.

Further, in order to make the transverse mode a single mode, the upper limit of the end width W1 is preferably 10 μm or less, more preferably 7 μm or less. The upper limit of the center width W2 is preferably 7 μm or less, more preferably 5 μm or less. The upper limit of the difference between the end width W1 and the center width W2 is preferably 5 μm or less, more preferably 3 μm or less, and 2 μm or less.
μm or less is most preferred. 0.2 μm for lower limit
Or more, more preferably 0.5 μm or more.

To achieve a laser whose beam is close to circular (aspect value 2 or less) while maintaining high reliability,
It is necessary to control the above dp and W within an appropriate range with good controllability.

It is effective to reduce the aperture width in order to realize a nearly circular beam. However, when the aperture width is reduced, the injection current density is not preferable from the viewpoint of suppressing bulk deterioration. Therefore, by reducing the width of the central portion W2, which is the gain region, to a relatively large value and the portion near the end portion to a relatively small value, the beam spot can be reduced and the low operating current can be realized at the same time. (Fig. 4
(B)).

That is, the upper limit of the edge (cleavage plane) width W1 is preferably 10 μm or less, and preferably 5 μm.
Or less, more preferably 3 μm or less. The lower limit is preferably 0.5 μm or more, more preferably 1 μm or more. The upper limit of the center width W2 is preferably 100 μm or less, and more preferably 50 μm or less. The lower limit is preferably 1 μm or more, more preferably 1.5 μm or more, and most preferably 2 μm or more. The upper limit of the difference between the end width W1 and the center width W2 is preferably 100 μm or less, more preferably 50 μm or less. The lower limit is preferably 0.2 μm or more, more preferably 0.5 μm or more.

The length of the above-mentioned gradually increasing portion, gradually decreasing portion, and end portion may be designed according to desired characteristics, but the length of the gradually decreasing portion is 5 to 5 from the viewpoint of reducing the waveguide loss.
10 μm is preferable, and 10 to 50 μm is more preferable.
The length of the end portion is preferably from 5 to 30 μm, more preferably from 10 to 20 μm, from the viewpoint of cleavage accuracy. However, if necessary, the window may be manufactured as follows. (1) The opening width or length of the end portion, the gradually increasing portion or the gradually decreasing portion is asymmetric on both sides of the chip. (2) An area in which the width of the end is constant is not set, but is gradually increased or decreased to the end. (3) One side of the end face (normally, high-output light extraction (front end face)
Side), the opening width of which gradually increases or decreases. (4) The width of the end opening differs between the front end face and the rear end face. (5) A combination of some of the above (1) to (4).

In addition, it is not necessary to provide an electrode near the end face to suppress bulk degradation due to current injection into the opening near the end face and to reduce recombination current at the end face. This is effective from the viewpoint of producing a laser having a spot diameter.

If the length of the window structure region in the direction of the resonator at the end is too short, it will be difficult to cleave with good reproducibility, while if it is too long, the loss in the window region 40 will increase. Laser characteristics such as an increase in current and a decrease in slope efficiency are deteriorated. Therefore, the lower limit of the length of the window region 40 is preferably 1 μm or more, more preferably 5 μm or more. As a maximum, 50 micrometers or less are preferred and 30 micrometers or less are more preferred.

The window region 25 is preferably formed at both ends, but may be formed only on one side surface. When formed only on one side, it is preferable to form it on the end face side from which higher-power laser light is emitted.

If the lower limit of the light output of the semiconductor optical device of the present invention is 30 mW or more, the features of the present invention can be used more effectively. At least 50 light output
If a long life can be confirmed at mW or more, the reliability of the semiconductor optical device at the time of high-output operation will be high. The optical output of the semiconductor optical device of the present invention is 100
mW or more, and even 200 mW or more, can be used for a long time.

The method of manufacturing a semiconductor optical device of the present invention is not particularly limited as long as a double heterostructure or the like can be crystal-grown, and is within the scope of the present invention as long as it satisfies the requirements of claim 1 above. It is. The method for growing the current blocking layer and the surface protective layer is not particularly limited as long as selective growth is possible, and the metal organic chemical vapor deposition (MO)
A known growth method such as a CVD method), a molecular beam epitaxy method (MBE method), a hydride or halide vapor phase growth method (VPE method), and a liquid phase growth method (LPE method) can be appropriately selected and used.

In the method of manufacturing a semiconductor optical device according to the present invention, first, a first conductive type clad layer 2 and an active layer 3 are formed on a substrate 1.
And a step b of forming a light-confinement region in the active layer 3 by performing a heat treatment after ion-implanting impurities and forming a light confinement region in the active layer 3. Can be exemplified. Details of this manufacturing method and other manufacturing methods can be understood from the following examples and related technical documents.

The method for growing crystals of each layer in the method for manufacturing a semiconductor optical device of the present invention is not particularly limited. Therefore, a conventional method can be used. For example, a metal organic chemical vapor deposition (MOCV) method is used for the crystal growth of the double hetero structure and the selective growth of the current blocking layer.
A known growth method such as D method), molecular beam epitaxy method (MBE method), hydride or halide vapor phase growth method (VPE method), and liquid phase growth method (LPE method) can be appropriately selected and used.

The specific growth conditions and the like of each layer vary depending on the composition of the layer, the growth method, the shape of the device, and the like. When the III-V compound semiconductor layer is grown by the MOCVD method, a double heterostructure is used. Is a growth temperature of about 600 to 750 ° C., and V
/ III ratio 50 to 150 (in the case of GaAs and InGaAs) about 20 to 60 (in the case of AlGaAs) or 3
The block layer has a growth temperature of 600 to 700 ° C. and a V / V
III ratio about 40 to 60 (in the case of AlGaAs) or about 350 to 550 (InGaAsP, AlGaInP
Is preferred).

As a semiconductor laser device utilizing the semiconductor optical device of the present invention, a light source for information processing (usually AlG
aAs system (wavelength around 780 nm), AlGaInP system (wavelength 600 nm band), InGaN system (wavelength 400 nm)
(In the vicinity)), communication signal light source (normally 1.3 μm band, 1.5 μm in which InGaAsP or InGaAs is used as an active layer)
communication semiconductor laser devices such as an m-band) laser, a fiber excitation light source (in the vicinity of 980 nm using an InGaAs strained quantum well active layer / GaAs substrate, or near 1480 nm using an InGaAsP strained quantum well active layer / InP substrate); Various devices that require high output operation can be given. In addition, even for communication lasers,
A laser having a circular shape is effective in increasing the coupling efficiency with the fiber. A laser having a single peak in the far-field image can be used as a laser suitable for a wide range of uses such as information processing and optical communication.

Further, the semiconductor optical device of the present invention can be applied not only to a semiconductor laser but also to optical elements such as a semiconductor optical amplifier, a photodetector, an optical modulator, an optical switch, and an integrated device thereof. Further, the present invention is not limited to a semiconductor laser, and may be a light emitting diode (LED) such as an edge emitting type.
It is also applicable as.

[0086]

The present invention will be described in more detail with reference to specific examples. Materials, reagents, ratios, operations, and the like shown in the following examples can be appropriately changed without departing from the spirit of the present invention. Therefore, the scope of the present invention is not limited to the following specific examples. (Example) In this example, a semiconductor light emitting element, which is one of the semiconductor optical device devices, was manufactured by forming each layer in the order shown in FIG. 3A to 3F, FIG.
Some parts are intentionally changed in size to make it easier to grasp the structure, but the actual dimensions are as described in the following text.

On a n-type GaAs (n = 1 × 10 ¹⁸ cm ⁻³ ) substrate 301 having a thickness of 350 μm and a (100) plane, a 2.0 μm-thick n-type Al is formed by MOCVD.
_0.4 Ga _0.6 As (Si doped: n = 1 × 10 ¹⁸ cm ⁻³ )
N-type cladding layer 302 of GaAs having a thickness of 30 nm
s optical confinement layer (non-doped), a thickness of 6 nm an In _{0. 2}
Ga _0.8 As well layer (non-doped), Ga having a thickness of 8 nm
As barrier layer (non-doped), 6 nm thick In _0.2 G
a _0.8 As well layer (non-doped) and 30 nm thick G
Double quantum well (DQW) active layer 303 formed by sequentially laminating aAs light confinement layer (non-doped), thickness 0.1 μm
P _0.4 Al _0.6 As (Zn doped: p = 1 × 10
¹⁸ cm ⁻³ ) p-type first cladding layer 304, thickness 1
0 nm p-type GaAs (Zn doped: p = 1 × 10 ¹⁸ c
m- ³ ) A double hetero structure was formed by sequentially laminating the antioxidant layers 305 (FIG. 3A).

Next, a protective film made of SiNx having a thickness of 0.3 μm was formed on the surface of the double hetero substrate by plasma CVD.
And [01] by photolithography.
1) A stripe-shaped surface protective film 306 having a longitudinal direction in the A direction was formed. Striped SiNx protective film 30
6 was 2 μm, and the horizontal space interval between the stripe-shaped SiNx protective films 306 was about 350 μm (FIG. 3B). Si was ion-implanted around the SiNx protective film 306 as a mask. The injection condition is 60 ke
V, 5 × 10 ¹³ cm ⁻² . After this, a film thickness of 4
A coating layer 307 made of 0 nm SiNx was deposited by plasma CVD (FIG. 3C), and heat treatment (annealing) was performed. Annealing conditions were 810 ° C. and 10 minutes. Thereafter, a striped SiNx protective film 306 is formed.
The coating layer 307 was removed by etching so as to remain. At this time, the impurity concentration in the light confinement region of the active layer was 2 × 10 ¹⁸ cm ⁻³ or less.

The above-mentioned striped SiNx protective film 30
6 on both sides by selective growth using MOCVD, a 0.6 μm thick n-type Al _0.45 Ga _0.55 As (Si-doped:
n = 1 × 10 ¹⁸ cm ⁻³ )
Then, an n-type GaAs surface protective layer (Si-doped: n = 1 × 10 ¹⁸ cm ⁻³ ) 309 having a thickness of 10 nm was formed (FIG. 3).
(D)). At this time, side surfaces of the opening made of the (111) B surface (B surface means As surface) were formed on both sides of the SiNx protective film 306. By selecting the stripe direction of the SiNx protective film 306 in the [011] A direction, the lateral growth on the protective film could be suppressed and the facets on the side surfaces of the opening could be made very flat.

Next, the rectangular SiNx protective film 306 was removed by etching. At this time, the SiNx protective film 3
For removing 06, wet etching using a buffered hydrofluoric acid solution or the like or dry etching using a gas such as SF ₆ or CF ₄ was used. Thereafter, a 2.0 μm-thick p-type Al _0.4 Ga _0.6 As (Zn-doped:
= 1 × 10 ¹⁸ cm ⁻³ ) p-type second cladding layer 31
0 and a 3.0 μm thick p-type GaAs (Zn-doped: p
= 2 × 10 ¹⁹ cm ⁻³ ) was grown (FIG. 3E).

In the above MOCVD method, trimethyl gallium (TMG), trimethyl indium (TMI) and trimethyl aluminum (T
MA), arsine and phosphine as group V raw materials,
Hydrogen was used as a carrier gas. Dimethyl zinc (DEZ) was used as the p-type dopant, and disilane was used as the n-type dopant. Furthermore, n-type Al
_When growing the _0.45 Ga _0.55 As current blocking layer, the SiN
HCl gas was used to suppress the deposition of poly on the x protective film.

Thereafter, the p-side electrode 312 was deposited and the substrate was thinned to 100 μm, and then the n-side electrode 313 was deposited and alloyed (FIG. 3 (f)). The wafer thus fabricated was cleaved and cut into chip bars to produce an embedded laser. After coating the end face, it was separated into chips by secondary cleavage. After assembling the chip by junction down, current-light output and current-voltage characteristics were measured at 25 ° C. by continuous conduction (CW).

The semiconductor laser device thus manufactured oscillates at a low threshold current (10 mA or less), the optical output increases as the operating current increases, and the high output (200 m
(W or more), light output was obtained without kink. Furthermore, it was found that high reliability (stable operation for 3000 hours or more at a high temperature of 50 ° C., 200 mW and high output) was obtained. In addition, since the opening for current injection is formed by selective growth, the side surface of the opening has less undulation (2).
0 nm or less) and the uniformity of the opening width could be improved, and the above-described semiconductor laser device could be manufactured with a high yield. The side surface was formed by an atomic force microscope (AF).
M).

Comparative Example Normal ion implantation and heat treatment were performed.
Then, the concentration in the light confinement region was set to 6 × 10 ¹⁸cm^-3
The laser element was manufactured in the same manner as in Example 1 except that
A child was made. The laser device of this comparative example is different from that of the first embodiment.
The impurity concentration of the light confinement region of the active layer is the second conductivity type first.
It is higher than the impurity concentration of the cladding layer. This element
When the operating current is increased, the
COD occurs when an optical output of 200 mW is obtained,
The user element has been broken.

[0095]

According to the semiconductor optical device of the present invention, since the impurity concentration of the light confinement region of the active layer is lower than the impurity concentration of the region A of the second conductivity type cladding layer, light absorption loss can be reduced. In addition, generation of a leak current can be suppressed. In addition, since the region A of the second conductivity type cladding layer has a higher resistance or a different conductivity type than the region B, current diffusion in the direction of the region A of the second conductivity type cladding layer can be suppressed. The current confinement is improved, and the current loss to the active layer can be reduced. Furthermore, the second
If a current blocking layer is formed on the region A of the conductive type cladding layer, and the current blocking layer is made to have a higher resistance or a different conductive type than the second conductive type cladding layer, diffusion of current in the lateral direction is further suppressed. Current can be effectively passed to the active layer. Therefore, the semiconductor optical device of the present invention is:
Since the threshold current can be reduced, the current-light conversion efficiency can be improved. Also, the semiconductor optical device of the present invention has improved luminous efficiency,
Since D can be effectively suppressed, a highly reliable semiconductor optical device can be provided.

[Brief description of the drawings]

FIG. 1 is a perspective view of an embodiment of a semiconductor optical device according to the present invention.

FIG. 2 is a perspective view showing a conventional general self-aligned waveguide type stripe structure.

FIG. 3 is a process diagram illustrating an example of a manufacturing process of the semiconductor optical device device of the present invention.

4A and 4B are diagrams illustrating a band gap of an active layer of an embodiment of the semiconductor optical device according to the present invention, wherein FIG. 4A is a diagram illustrating a band gap of a window region, and FIG. FIG. 7 is a diagram showing a band gap when the band gap is not performed.

FIG. 5 is a top view of one embodiment of the semiconductor light emitting device of the present invention.

[Explanation of symbols]

 1: substrate 2: first conductivity type clad layer 3: active layer 4: second conductivity type first clad layer 5: antioxidant layer 6: current blocking layer 7: surface protection layer 8: opening 9: second conductivity type Second clad layer 10: Contact layer 15: Substrate 16: First conductive type clad layer 17: Active layer 18: Second conductive first clad layer 19: Antioxidant layer 20: Surface protective layer 21: Second conductive type second Cladding layer 22: Contact layer 25: Window region 26: Mixed crystal region 51, 55: Light guide layer 52, 54: Quantum well layer 53: Barrier layer 60: Optical waveguide region 61: Optical confinement region 62: Region A 63: Region B 301: Substrate 302: N-type cladding layer 303: Active layer 304: P-type cladding layer 305: P-type antioxidant layer 306: SiNx protective film 307: SiNx coating layer 30 : The current blocking layer 309: a surface protective layer 310: p-type second cladding layer 311: contact layer 312: p-side electrode 313: n-side electrode W1: end width W2: central width

Claims (28)

[Claims] 1. A substrate, a first conductive type clad layer formed on the substrate, an active layer formed on the first conductive type clad layer, and a second conductive type clad layer formed on the active layer A semiconductor optical device having: wherein the active layer comprises:
An optical waveguide region formed at the center in the longitudinal direction of the active layer, and a light confinement region formed on both sides of the optical waveguide region, having a larger band gap and a smaller refractive index than the optical waveguide region. The impurity concentration of the light confinement region is:
A semiconductor optical device device, wherein the impurity concentration is lower than an impurity concentration in a region A of the second conductivity type clad layer located immediately above the light confinement region. 2. The semiconductor optical device according to claim 1, wherein the impurity concentration of the light confining region of the active layer is 5 × 10 ¹⁸ cm ⁻³ or less. 3. The optical waveguide according to claim 1, wherein the width of the optical waveguide region of the active layer is different between the central portion and the vicinity of the end face.
3. The semiconductor optical device device according to item 1. 4. A region A of the second conductivity type cladding layer,
The conductive layer according to claim 1, wherein the active layer has a higher resistance or a different conductive type than a region B of the second conductive type clad layer located immediately above the optical waveguide region of the active layer. Semiconductor optical device. 5. The semiconductor optical device according to claim 1, wherein said active layer has a quantum well layer. 6. The semiconductor optical device according to claim 5, wherein a compressive strain is applied to the quantum well layer. 7. The semiconductor optical device according to claim 5, wherein the quantum well layer contains In as a constituent element. 8. The method according to claim 1, wherein the quantum well layer is at least GaAs,
AlGaAs, InGaAs, AlGaInAs, Ga
InP, AlGaInP, GaInAsP, AlGaI
The semiconductor optical device device according to claim 5, wherein the device is made of nAsP, GaN, or InGaN. 9. The method according to claim 1, wherein the active layer has a barrier layer and / or a light guide layer sandwiching the quantum well layer, and the barrier layer and / or the guide layer are thicker than the quantum well layer. 9. The semiconductor optical device according to claim 5, wherein 10. A barrier layer sandwiching the quantum well layer and / or
10. The semiconductor optical device according to claim 9, wherein Al is included as a constituent element of the light guide layer. 11. The quantum well layer in the light confinement region of the active layer is mixed crystal.
0. The semiconductor optical device according to any one of the above items. 12. A window region in which the band gap of the quantum well layer is larger than the central portion of the optical waveguide region near at least one end face of the optical waveguide region of the active layer. 12. The semiconductor optical device according to any one of items 1 to 11. 13. The semiconductor optical device according to claim 12, wherein the quantum well layer is mixed crystal in the window region. 14. The semiconductor optical device according to claim 12, wherein a protective film is formed on the window region. 15. The semiconductor optical device according to claim 1, wherein a current blocking layer is formed on the region A of the second conductivity type cladding layer. 16. The semiconductor optical device according to claim 15, wherein said current blocking layer is formed of a semiconductor layer of at least a first conductivity type or a high resistance. 17. The semiconductor optical device according to claim 1, wherein said semiconductor optical device is a semiconductor laser. 18. The semiconductor optical device according to claim 1, wherein said semiconductor optical device is a semiconductor optical amplifier. 19. The semiconductor optical device according to claim 1, which is used as a light source for exciting an optical fiber amplifier. 20. a step of forming a substrate, a first conductivity type cladding layer, an active layer, and a second conductivity type cladding layer in this order;
And a step b of forming a light confinement region in the active layer by heat treatment after ion implantation of impurities. 21. Impurity ions are implanted so that the impurity concentration of the light confinement region of the active layer is lower than the impurity concentration of the region A of the second conductivity type clad layer located immediately above the light confinement region. 21. The method of manufacturing a semiconductor optical device according to claim 20, wherein: 22. The thickness of the cladding layer of the second conductivity type is 0.0
22. The method according to claim 19, wherein the ion implantation energy is 5 to 1000 keV when the thickness is 1 to 1 [mu] m. 23. The ion implantation amount 0.5 × 10 in the case where the impurity ions are implanted ^{-1 3 cm -2 ~20 × 10 -13} cm -2
23. The method for manufacturing a semiconductor optical device according to claim 22, wherein: 24. The method according to claim 20, wherein the ion-implanted element does not substantially diffuse into the active layer by the heat treatment.
24. The method for manufacturing a semiconductor optical device device according to any one of items 23 to 23. 25. The method according to claim 20, wherein the step (b) includes a step of forming a surface protective film on a surface of a portion not to be ion-implanted before ion implantation, and removing the surface protective film after the ion implantation. 25. The method for manufacturing a semiconductor optical device device according to any one of items 24 to 24. 26. The method according to claim 25, wherein the surface protection film is SiNx. 27. The method according to claim 20, wherein, in the step (b), a coating layer is formed on the surface of the second conductivity type cladding layer before the heat treatment, and the coating layer is removed after the heat treatment. 27. A method of manufacturing a semiconductor optical device according to any one of 28. The method according to claim 27, wherein the coating layer is made of a Si-based amorphous.