JPH09320912A - Semiconductor substrate and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the quality of a semiconductor device, the yield and throughput in a semiconductor substrate with a large bore by performing a plurality of heat treatments by providing a semiconductor substrate having no propagation of a slip generated on the substrate rear side up to the substrate surface. SOLUTION: Two single crystal substrates 1, 2 having the same face azimuths are overlapped with the crystal axis azimuths shifted each other for being finished to a prescribed thickness after heat treatment so as to from a semiconductor substrate 11. In this case, a treatment such as ion implantation is performed into the surface of the side to which at least one side single crystal substrate is to be joined, or an oxide film is formed for performing joining together so as to strengthen slip prevention.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate used for a semiconductor device and a method of manufacturing the same, and more particularly to a single crystal substrate having a large diameter.

[0002]

2. Description of the Related Art Conventionally, a wafer obtained by slicing a silicon (Si) single crystal ingot has been used as a semiconductor substrate for use in this type of semiconductor device, and a plurality of heat treatment steps are added in the process of manufacturing the semiconductor device. . This heat treatment step is performed in a high-temperature processing furnace. At this time, thermal stress is generated at a contact portion between the substrate and a boat accommodating the substrate. This thermal stress is generated by the weight of the substrate at the contact point due to the difference in the coefficient of thermal expansion between the substrate and the boat. The thermal stress increases as the diameter of the semiconductor substrate increases.

[0003] Due to this thermal stress, dislocation occurs in a portion of the substrate in contact with the boat, causing crystal defects called slip and wafer warpage. Since a single substrate is a single crystal in which the crystal axis is in a fixed direction, the slip easily propagates to the substrate surface in the device formation region. Further, as the size of a semiconductor device manufactured from a semiconductor substrate is reduced, the production yield of the semiconductor device is reduced even if a slight slip occurs.

In order to improve the throughput, it is necessary to expand the device fabrication region to the outermost peripheral portion of the semiconductor substrate. However, since the outer peripheral portion tends to cause slip, the use of the outer peripheral region is difficult. Has a limit.

As a conventional method for preventing slippage, a method is adopted in which the cycle at the time of temperature rise and fall in the heat treatment step, that is, the thermal history is delayed to reduce the occurrence of thermal stress, but the throughput is reduced. There is a disadvantage of doing so.

In order to solve these problems, Japanese Patent Laid-Open Publication No.
In JP-A-62867, as shown in FIG. 8, a groove 36 is provided around one wafer 32 of the two flat wafers 32 and 33 by etching, and the two wafers 32 and 33 are vacuumed. After the bonding, the semiconductor substrate 37 is formed by heat treatment, and a vacuum space 36 is formed inside the substrate.
A method is disclosed in which the voids 36 are used to alleviate the strain generated in the wafer and reduce the stress, thereby preventing the occurrence of dislocations and crystal defects.

[0007]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the method disclosed in Japanese Patent No. 2867, a groove is provided on one surface of two substrates, the surface having the groove is bonded to another substrate, and a space is provided inside the substrate. Alleviates the strain generated on the wafer and reduces the stress,
The method to prevent the occurrence of dislocations and defects is to stop the slip generated from the back side of the substrate, but due to the void inside the substrate,
Since irregularities are generated on the surface of the superposed substrates, there is a disadvantage that it is difficult to form a minute semiconductor element.

It is an object of the present invention to provide a semiconductor substrate in which a slip generated from the back surface of a large-diameter substrate subjected to a plurality of heat treatments does not propagate to the substrate surface. An object of the present invention is to improve the quality, yield, and throughput of a device.

[0009]

According to a first semiconductor substrate of the present invention, a first single crystal substrate and a second single crystal substrate having the same plane orientation are stacked to form a first semiconductor substrate and a second semiconductor substrate. To prevent the crystal axis orientations on the main surface of the substrate from matching, the directions of the crystal axes on the main surface of the substrate are offset from each other by an angle of more than 0 ° and less than 90 °, and they are bonded to each other. It is formed by polishing.

[0010] If a semiconductor substrate is formed by laminating and bonding two single-crystal substrates so that their crystal axis directions on the main surfaces do not coincide with each other, the heat is generated from the portion of the back surface of the substrates that contacts the boat. A crystal defect called a slip stops at the surface of the upper single crystal substrate with different crystal axis orientations on the surface where the two single crystal substrates are bonded, and the upper surface of the upper single crystal substrate, which is the device active region, Propagation can be prevented.

A second semiconductor substrate of the present invention comprises a first single crystal substrate and a second single crystal substrate formed by changing the principal plane orientation with respect to the principal plane orientation of the first single crystal substrate. It is formed by superposing and joining, and grinding and polishing to a predetermined thickness.

Since the first and second single-crystal substrates having different principal plane orientations do not have the same slip dislocation plane angle, the first and second single-crystal substrates have a lower slip surface that contacts the boat during the heat treatment. Even if a dislocation plane occurs, it does not affect the upper single crystal substrate in the bonding plane.

The above-mentioned first and second semiconductor substrates of the present invention are provided as means for preventing the propagation of crystal defects on the surface of at least one of the first and second single crystal substrates which is to be joined. It is preferable to perform a treatment for creating any one of crystal defects of ion implantation, sandblast, dislocation, and strain.

Furthermore, it is preferable that the first and second single crystal substrates have an oxide film on the surface of at least one of the substrates to be joined.

By applying these treatments, the above-mentioned first and second semiconductor substrates of the present invention allow the propagation of the slip generated at the contact surface of the semiconductor substrate with the boat to occur at the joint between the two single crystal substrates. The blocking effect is further improved.

[0016]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a diagram showing a first embodiment of a semiconductor substrate of the present invention, FIG. 1 (a) is a schematic side view, FIG. 1 (b) is an exploded perspective view of two wafers,
FIG. 2 is a plan view of the wafer.

In FIG. 1A, a semiconductor substrate 11 is formed by superimposing a first wafer 1 and a second wafer 2 having the same plane orientation. When the two wafers are superposed on each other, as shown in FIG. 1B, the crystal axis orientations on the main surfaces of the two wafers, which are measured by an X-ray diffraction method, do not match, as shown in FIG. The crystal axis orientations {011} on the principal plane of are shifted by the angle θ so that they do not coincide with each other. The magnitude of θ is 0 <θ <90.

The reason for this is that in the case of a wafer whose plane orientation is the (100) plane as shown in FIG. 2, as shown in FIG.
Since the generated slip occurs along the (111) dislocation plane 10 in the cleavage plane <110> direction,
This is to prevent the cleavage planes of the wafers from matching. That is, in the case of a wafer having a plane orientation of (100), the cleavage plane is {110}, and each has an angle of 90 °.

Also in the case of bonding wafers having plane orientations of (110) and (111), they may be bonded so that the cleavage planes do not coincide with each other, as in the above. However, in any case, it is preferable that the thickness of the wafer be the same. The reason is to prevent the substrate from warping due to the heat treatment.

The step of bonding the first and second wafers will be described. The sliced silicon wafer is hydrophilized by chemical treatment as shown in FIG. 3A. Then, the two wafers are mechanically bonded in a vacuum and heated to 500 ° C. to 1000 ° C. in a vacuum in order to strengthen the adhesion of the bonded surfaces, and FIG.
Dehydration condensation is performed as shown in FIG.

After bonding the two wafers in this way, the semiconductor substrate 11 is formed by grinding and polishing to finish to a predetermined thickness used in the process of manufacturing a semiconductor device.

If the two wafers are stacked and bonded so that the crystal axis directions on the main surfaces of the two wafers do not coincide with each other to form a semiconductor substrate, the slip generated from the contact portion of the back surface of the substrate with the boat in the heat treatment process can be obtained. A crystal defect called a crystal wafer stops at a bonding surface of an upper wafer having a different crystal axis orientation on a bonding surface of two wafers and is prevented from propagating to an upper surface side of the upper wafer which is a device active region. Can be. Since the lower surface of the upper wafer is bonded to the lower wafer, the cause of slippage due to no contact with the boat is eliminated.

Next, a second embodiment of the present invention will be described. FIG. 4 is a schematic cross-sectional view showing the direction of cutting out the main surfaces of the _first wafer ₁₁ and the second wafer 21. FIG. 5 illustrates the relationship between the angle between the slip dislocation plane and the growth plane in a silicon single crystal. FIG.

In this case, the main surfaces of the first and second wafers are formed so as to be different from each other. That is, if the first main surface orientation of the single crystal substrate 1 ₁ and <100>, the second major surface orientation of the single crystal substrate 2 ₁ 4 <100>
And is formed at an angle of φ °.

The reason is as shown in the sectional view of FIG.
In the case of a silicon wafer 9 having a growth plane with a (100) plane orientation, the slip dislocation plane 10 is represented by a (111) plane and forms an angle of 54.74 ° with the (100) plane. ing. Therefore, when the first main surface orientation of the silicon wafer 1 ₁ (100) plane, by an inclination angle phi of the second silicon wafer 2 _primary face orientation 0 <phi <a range of 54.74 ° if not match slip dislocation surfaces of the two wafers, thus slip dislocation surfaces generated in the wafer 2 _1,
It does not affect the wafer 1 ₁ in the bonding surface of the wafer 1 _1.

When the wafer is bonded to a wafer having one of the (110) and (111) planes, the other wafer is cut out by inclining the plane of the other wafer by φ ° in the same manner as described above, so that the slip dislocation planes are mutually formed. It is good to stick so that they do not match.

The steps of bonding the two wafers thus formed, performing a heat treatment, and performing a polishing treatment to form a semiconductor substrate are the same as the steps described in the first embodiment.

Next, a third embodiment of the present invention will be described. In this embodiment, as shown in FIG. 6, ion implantation, as means for preventing the propagation of crystal defects, is performed on at least one of the surfaces of the first wafer 1 ₂ and the second wafer 2 ₂ to be bonded. After performing processing to create any one of crystal defects in sandblast, dislocation, and strain,
The two wafers are bonded together and the semiconductor substrate 12 is formed through the same steps as described above. If this method is applied to the wafers described in the first and second embodiments,
It is further effective in preventing the propagation of slips generated on the back surface of each semiconductor substrate at the mating surface.

Next, a fourth embodiment of the present invention will be described. In this embodiment, as shown in FIG. 7, a semiconductor substrate 13 is formed on at least one of the surfaces of the first wafer 1 ₃ and the second wafer 2 ₃ to be bonded together with an oxide film 5 interposed. Is. A suitable oxidation temperature is about 1100 ° C., and an oxidation time is about 10 minutes. The semiconductor substrate 13 is formed through the same steps as described above so that the surface on which the oxide film is formed is the bonding surface. If this method is applied to the wafers described in the first and second embodiments described above, it is further effective in preventing the propagation of slips generated on the back surface of the semiconductor substrate at the mating surface.

[0030]

As described above, the semiconductor substrate of the present invention is formed by stacking two single crystal substrates and shifting the crystal axis directions on the main surfaces of the stacked single crystal substrates from each other. Slip that occurs at the contact part with the boat on the backside of the substrate due to the heat treatment because the main surface orientation of the superposed single crystal substrate is formed so as to be different from the main surface orientation of the other single crystal substrate, and the structure is superposed. However, there is an effect that it is blocked at the bonding interface and does not propagate to the surface layer of the substrate on which the device of the front side is formed. Therefore, if a semiconductor device is manufactured using this semiconductor substrate, its quality and yield can be improved, and it is not necessary to delay the thermal history in the heat treatment step, and throughput can be improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of a semiconductor substrate of the present invention, wherein FIG. 1A is a schematic side view of the semiconductor substrate, and FIG.
(B) is a development perspective view of two wafers.

FIG. 2 is a schematic plan view showing a direction of a cleavage plane of a wafer.

FIG. 3 is a diagram illustrating the principle of bonding wafers.

FIG. 4 is a diagram showing a second embodiment of the present invention,
FIG. 3 is a schematic cross-sectional view illustrating a direction of a main surface of a wafer.

FIG. 5 is a schematic sectional view showing an angle of a slip dislocation plane in a silicon single crystal wafer.

FIG. 6 is a schematic cross-sectional view of a semiconductor substrate showing a third embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view of a semiconductor substrate showing a fourth embodiment of the present invention.

FIG. 8 is a schematic diagram of an example of a semiconductor substrate according to the prior art.

[Explanation of symbols]

1, 1 ₁ , 1 ₂ , 1 ₃ , 32 1st single crystal substrate / wafer 2, 2 ₁ , 2 ₂ , 2 ₃ , 33 2nd single crystal substrate / wafer 5 Oxide film 6 Strained layer 7 (100) Semiconductor substrate 8 Cleaved surface 9 Silicon wafer 10 Slip dislocation surface 11, 12, 13, 37 Semiconductor substrate 36 Groove / vacancy

Claims (8)

[Claims] 1. A first single crystal substrate and a second single crystal substrate having the same plane orientation are overlapped with each other so that the crystal axis orientations on the planes of the first substrate and the second substrate do not match. , A semiconductor substrate formed by being bonded to each other with an angle of more than 0 ° and less than 90 ° and being ground and polished to a predetermined thickness. 2. A semiconductor substrate formed by superimposing the first single crystal substrate and a second single crystal substrate formed by changing the principal plane orientation on the first substrate. 3. Ion implantation, sandblast, dislocation, strain, etc., as means for preventing the propagation of crystal defects on the surface of at least one of the first and second single crystal substrates on the side to be joined. The semiconductor substrate according to claim 1 or 2, which has been subjected to a treatment for producing one of the crystal defects. 4. The semiconductor substrate according to claim 1, wherein the first and second single crystal substrates have an oxide film on a surface of at least one of the substrates on the side to be bonded. 5. The main surfaces of the first single crystal substrate and the second single crystal substrate having the same plane orientation are opposed to each other, and they are bonded at positions where the crystal axis orientations of the main surfaces do not coincide with each other. A method for manufacturing a semiconductor substrate, wherein heat treatment is performed to increase the adhesive strength of the bonded surfaces, and grinding / polishing is performed to a predetermined thickness. 6. A first single crystal substrate is formed, and a second single crystal substrate having a principal plane orientation different from a principal plane orientation of the first single crystal substrate is formed. A method for manufacturing a semiconductor substrate, which comprises bonding a second single crystal substrate so as to face each other, performing heat treatment for increasing the bonding force of the bonded surface, and grinding / polishing to a predetermined thickness. 7. Ion implantation is performed on the bonding surface of at least one of the first and second single crystal substrates,
The method for manufacturing a semiconductor substrate according to claim 5, wherein the semiconductor substrate is subjected to any one treatment of sandblasting, dislocation, strain, etc., and then bonded and formed. 8. An oxide film is applied to the bonding surface of at least one of the first and second single crystal substrates, and then the first and second single crystal substrates are bonded to each other. 7. The method for manufacturing a semiconductor substrate according to claim 5 or 6.