JPH09298237A - Multilayer interconnection method of integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: Not only to lessen a time required for carrying out the multilayer interconnection of an integrated circuit but also to synchronize the integrated circuit on clock by a method wherein a wiring is provided in parallel with an X-direction wiring so as not to pass over a point O, provided that an intersection of an X-direction wiring and a Y-direction wiring in the top view of the wiring of the integrated circuit is represented by a point O. SOLUTION: Provided that an intersection of an X-direction wiring and a Y-direction wiring in the top view of the wiring of an integrated circuit is represented by a point O, a wiring is provided in parallel with the X-direction wiring so as not to pass over the point O. That is, an LSI wiring layer is composed of a zero layer 20 where gates 30 and terminals are provided, a first layer 21 where an X-direction wiring layer 31 is provided, a second layer 22 where a Y-direction wiring layer 32 is provided, a third layer 23 where a wiring layer 33 is provided in parallel with the X-direction wiring layer 31 and equipped with wirings arranged between the wirings of the X-direction wiring layer 31, and furthermore a fourth layer 24 where a wiring layer 34 is provided in parallel with the Y-direction wiring layer 32 and equipped with wirings arranged between the wirings of the X-direction wiring layer 31.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring method for an integrated circuit, and more particularly to a multilayer wiring method for a high speed LSI.

[0002]

2. Description of the Related Art Generally, in a conventional multi-layered structure of an LSI (Large Scale Integrated Circuit), a gate layer where AND, OR, NOT, etc. are located is located at the lowest layer, and a wiring layer is formed thereon. It was FIG. 10 is a schematic view showing a multilayer structure of such a conventional LSI.

As shown in this figure, AND, O of the lowermost layer
The gate layer 1 where R, NOT, etc. are located is the 0th layer 10,
The upper layers are referred to as a first layer 11, a second layer 12, ... When viewed from directly above and considering the X, Y, and Z axes as a reference, the first layer 11 is formed from the wiring region 2 in the X direction, the second layer 12 is formed in the wiring region 3 in the Y direction, and the third layer 13 is formed. The wiring regions 2 in the X direction are alternately formed. Also, the first layer 11,
The wiring regions of the third layer 13 ... All appear to overlap on the same line. Similarly, the second layer 12, the fourth layer 14,
.. also appear to overlap on the same line.

Further, each layer is connected to an intersection of the X-direction wiring 4 and the Y-direction wiring 5 by using a via (VIA) 6 which is a Z-direction wiring. Based on such a wiring layer structure, it is necessary to reduce the wiring length and form an efficient wiring capable of clock synchronization and the like, and various algorithms have been devised.

Here, one of the wiring problems that is currently receiving attention is the Zero-Skew problem. This is a problem of realizing clock synchronization by making the wiring lengths equal when wiring from a certain terminal to several terminals. 11 shows a multi-layered structure of a three-layer structure showing one example thereof, FIG. 11 (a) is a plan view of the 0th layer, FIG. 11 (b) is a plan view of the first layer, and FIG.
11C is a plan view of the second layer, FIG. 11D is a composite view of the layers, and FIG. 11E is a view showing the wiring state.

As shown in FIG. 11 (e), when wirings having the same wiring length are provided from the point A to the point B, the point C and the point D, according to the conventional algorithm, the middle of the points B and C is used. A point (referred to as point H) is taken, and wiring from point B and point C to point H is provided.
Next, the wiring length between the midpoint (point H) and the point B or the point C is calculated, the wiring having the same length is provided from the point D on an arbitrary route, and then the point I is generated. Here, a midpoint (point J) between points H and I is taken, and wiring from point A to point J is provided. As a result, the wiring as shown in FIG.

[0007]

However, in the above-described conventional wiring method, as shown in FIG. 12, the midpoint (point H) of the points B and C is in the area where wiring does not exist. In that case, a point H'close to it is obtained. next,
A wiring having the same length as the wiring length (L) between the points B and C from the middle point (point H ′) is provided from the point D to generate an extension point (point I),
Match the wiring length. However, no matter where the wiring of length L is performed and the point I is generated at any point, the middle point (point J) is a region where no wiring exists.

In such a case, it is impossible to obtain Zero-Skew by any wiring.
Retrying from the placement problem in the previous stage of the wiring problem, or giving up the strict Zero-Skew, the approximate solution was used. This is not desirable not only in terms of time but also in terms of clock synchronization. SUMMARY OF THE INVENTION It is an object of the present invention to eliminate the above-mentioned problems, reduce the wiring time, and provide a multilayer wiring method for an integrated circuit, which can perform clock synchronization.

[0009]

In order to achieve the above-mentioned object, the present invention provides [1] a multilayer wiring method for an integrated circuit, wherein the wiring of the integrated circuit is viewed from directly above and the wiring of the X-direction wiring and the Y-direction wiring is When the intersection is point O, it is parallel to the X-direction wiring and
The wiring does not pass above.

As described above, by subdividing the wiring in the X-axis direction, it is possible to reduce the wiring time and perform clock synchronization. [2] In the multilayer wiring method of the integrated circuit, when the wiring of the integrated circuit is viewed from directly above and the intersection point of the X-direction wiring and the Y-direction wiring is point O, it is parallel to the Y-direction wiring and the point O
The wiring does not pass above.

By thus subdividing the wiring in the Y-axis direction, it is possible to reduce the wiring time and to perform clock synchronization. [3] In the multilayer wiring method of an integrated circuit, when the wiring of the integrated circuit is viewed from directly above and the intersection point of the X-direction wiring and the Y-direction wiring is point O, it is parallel to the X-direction wiring and point O
A wire that does not pass above and a wire that is parallel to the Y-direction wire and does not pass above the point O are provided.

Thus, by subdividing the wiring in the X-axis and Y-axis directions, the wiring time can be reliably reduced, and
It becomes possible to obtain strict clock synchronization. Especially,
This is effective for wiring high-speed logic circuits where clock synchronization is difficult, and enables higher-speed circuit design. [4] In the multilayer wiring method of an integrated circuit, when the wiring of the integrated circuit is viewed from directly above and the intersection point of the X-direction wiring and the Y-direction wiring is point O, the X-direction wiring and the Y-direction wiring are fixed. A plurality of wirings having an angle and parallel to each other are provided so as not to pass over the point O.

As described above, by subdividing the wiring oblique to the X-axis and the Y-axis, the wiring time can be reduced and clock synchronization can be performed.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the present invention, Zero
-As a means to completely solve the Skew problem, LSI
In addition to the conventional wiring, the wiring layer which is parallel to the X-direction wiring and has a wiring whose Y coordinate position is shifted from the X-direction wiring of the other layer,
Parallel to the direction wiring, and in the Y direction wiring of another layer, and X
An LSI that has a wiring layer with wiring whose coordinates are displaced
To provide a multi-layer wiring layer configuration.

FIG. 1 shows a multi-layer structure of the five-layer structure of the present invention. FIG. 1 (a) is a plan view of the 0th layer, and FIG.
1B is a plan view of the first layer, FIG. 1C is a plan view of the second layer, and FIG. 1D is a plan view of the third layer.
FIG. 1E is a plan view of the fourth layer, and FIG. 1F is a composite view of the layers. In FIG. 1, the wiring layer configuration of the LSI is
As shown in FIG. 1A, the 0th layer 20 has a gate 30 and a terminal, and as shown in FIG.
In the X-direction wiring layer 31, the second layer 22 in the Y-direction wiring layer 32 as shown in FIG. 1C, and the third layer 23 as shown in FIG. And, and
A wiring layer 33 in which wiring is provided between the respective wirings of the X-direction wiring layer 31 of the first layer 21, and as shown in FIG. 1E, the fourth layer 24 is parallel to the Y-direction wiring layer 32, And,
A wiring layer 34 having wiring is provided between the Y-direction wirings 32 of the second layer 22. Reference numeral 25 shown in FIG. 1 (f) indicates a composite plane layer of them.

Next, the wiring method (solution) of the present invention will be described with reference to FIGS. First, in the arrangement as shown in FIG. 2, from the starting point 1 to the points 2, 3, 4, 5, 6,
When the Zero-Skew wiring is applied to No. 7, ZSP (Zero-S) of an arbitrary pair of two points (2 and 3, 5 and 6, 4 and 7)
(key point). Next, as shown in FIG. 3, the midpoint (8, 9, 10) of this pair of two points is taken and Z
Wiring from SP to the midpoint. Here the midpoint (8, 9, 1
0) is replaced with MP (Mark-Point).

Next, as shown in FIG. 4, a set consisting of points 2, 3, and 8 and a set consisting of points 4, 7, and 10 are selected, and the middle point (8) to ZSP (2) are selected. Or wiring length X up to 3)
And the wiring length Y from the midpoint (10) to ZSP (4 or 7)
Compare. The difference between X and Y is 1.0, point 2, point 3 and point 8
Since the set has a long wiring length, the wiring (10 to 11) having the wiring length of 1.0 is applied from the MP (10) by an arbitrary route,
An extension point (11) is generated and the wiring lengths are matched.

Next, as shown in FIG. 5, the MP (10) is updated, the extension point (11) is replaced with the MP, the midpoint (12) between the MPs (8 and 11) is taken, and the wiring is performed from the MP. Give.
Here, as shown in FIG. 6, the middle point (12) is replaced with MP, and then a set of point 2, point 3, point 4, point 7 and point 12,
The wiring lengths of the pairs of points 5, 6, and 9 are compared. Difference is 7.
5 and since the wiring length of the set of point 2, point 3, point 4, point 7, and point 12 is long, the wiring (9-13) having the wiring length of 7.5 is routed from MP (9) by an arbitrary route. Then, the extension point (13) is generated to match the wiring length.

Next, as shown in FIG. 7, the extension point (13)
Is replaced by MP, and the midpoint between MP (12 and 13) (1
Wire to 4). Finally, as shown in FIG. 8, the midpoint (14) is replaced with MP, and wiring is performed from the starting point (1) to complete the Zero-Skew wiring. At this time, from the starting point (1) to ZSP (2, 3 and 4, 5 and 6 and 7)
The wiring lengths up to are 19.0.

By using these wirings, the conventional Zero-Skew wiring shown in FIG. 12 can be obtained as shown in FIG. In the conventional case, as shown in FIG. 12, the midpoint cannot be taken and the wiring is impossible, but the half wiring of the present invention can be used to easily perform the wiring. Further, the wiring length of the embodiment of the present invention is 4.

As described above, according to the present invention, by adopting the half-wiring method, it is possible to reliably reduce the wiring time and to obtain strict clock synchronization. In particular, it is effective for wiring of a high-speed logic circuit in which clock synchronization is difficult, and a higher-speed circuit can be designed. FIG. 13 is a view showing a multi-layer structure of a five-layer structure showing another embodiment of the present invention, and FIG. 13 (a) is a plan view of the 0th layer thereof, and FIG.
FIG. 13B is a plan view of the first layer, and FIG.
FIG. 13D is a plan view of the third layer, and FIG.
3 (e) is a plan view of the fourth layer, and FIG. 13 (f) is a composite view of the respective layers. The same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

As shown in these figures, in this embodiment, the third layer 41 is displaced from the X-axis, the wiring layer 51 inclined by 45 ° is formed, and the fourth layer 42 is displaced from the Y-axis. The inclined wiring layer 52 is formed. The composite plane layer 43 is shown. It should be noted that although the above-mentioned embodiment describes the five-layer structure, it is needless to say that the present invention can be applied to a multi-layer wiring for forming more multi-layers.

Further, subdivision of wiring parallel to the X-axis and Y-axis,
Subdivided multilayer wiring may be performed by combining subdivisions using oblique wiring. Furthermore, the present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and these modifications are not excluded from the scope of the present invention.

[0024]

As described above, according to the present invention, the following effects can be obtained. (1) According to the first aspect of the invention, by subdividing the wiring in the X-axis direction, it is possible to reduce wiring time and perform clock synchronization.

(2) According to the second aspect of the invention, by subdividing the wiring in the Y-axis direction, it is possible to reduce the wiring time and perform clock synchronization. (3) According to the third aspect of the invention, by subdividing the wiring in the X-axis and Y-axis directions, it is possible to reliably reduce the wiring time and to obtain strict clock synchronization. In particular, it is effective for wiring a high-speed logic circuit in which clock synchronization is difficult, and a higher-speed circuit can be designed.

(4) According to the fourth aspect of the present invention, the wiring time can be reduced and clock synchronization can be performed by subdividing the wiring obliquely to the X-axis and the Y-axis.

[Brief description of drawings]

FIG. 1 is a diagram showing a multilayer structure of a five-layer structure showing an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a solution method (process 1) when wiring is provided according to the embodiment of the present invention.

FIG. 3 is a diagram showing an example of a solution method (process 2) when wiring is provided according to the embodiment of the present invention.

FIG. 4 is a diagram showing an example of a solution method (process 3) when wiring is provided according to the embodiment of the present invention.

FIG. 5 is a diagram showing an example of a solution method (process 4) in the case of providing the wiring according to the embodiment of the present invention.

FIG. 6 is a diagram showing a solution example (process 5) in the case of providing the wiring according to the embodiment of the present invention.

FIG. 7 is a diagram showing an example of a solution method (process 6) when wiring is provided according to the embodiment of the present invention.

FIG. 8 is a completed diagram of the Zero-Skew wiring according to the embodiment of the present invention.

FIG. 9 is a diagram showing an example of wiring according to the embodiment of the present invention.

FIG. 10 is a schematic diagram showing a multilayer structure of a conventional LSI.

FIG. 11 is a diagram showing a multi-layer structure of a conventional three-layer structure.

FIG. 12 is a diagram showing a problem of wiring of a conventional multilayer structure.

FIG. 13 is a diagram showing a multilayer structure of a five-layer structure showing another embodiment of the present invention.

[Explanation of symbols]

 20 0th layer 21 1st layer 22 2nd layer 23,41 3rd layer 24,42 4th layer 25,43 Composite plane layer 30 Gate 31 X direction wiring layer 32 Y direction wiring layer 33,34,51,52 Wiring layer

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Kenichi Toya 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Kenji Shimonaka 1-7-12 Toranomon, Minato-ku, Tokyo In Oki Electric Industry Co., Ltd. (72) Inventor Tatsusaku Home 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (4)

[Claims] 1. When the wiring of the integrated circuit is viewed from directly above and the point of intersection of the X-direction wiring and the Y-direction wiring is point O, wiring that is parallel to the X-direction wiring and does not pass over the point O is defined. A multi-layer wiring method for an integrated circuit, which is performed. 2. When the wiring of the integrated circuit is viewed from directly above and the point of intersection of the X-direction wiring and the Y-direction wiring is point O, a wiring that is parallel to the Y-direction wiring and does not pass over the point O is defined. A multi-layer wiring method for an integrated circuit, which is performed. 3. A wiring which is parallel to the X-direction wiring and does not pass over the point O when the intersection of the X-direction wiring and the Y-direction wiring is point O when the wiring of the integrated circuit is viewed from directly above. , Y
A multilayer wiring method for an integrated circuit, characterized in that wiring parallel to the direction wiring and not passing over the point O is provided. 4. When the wiring of the integrated circuit is viewed from directly above and the intersection of the X-direction wiring and the Y-direction wiring is point O, the wiring has a certain angle with respect to the X-direction wiring and the Y-direction wiring, and A multilayer wiring method for an integrated circuit, wherein a plurality of wirings are provided in parallel so as not to pass over the point O.