JPH09297705A - Memory control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the memory control method which can perform precise control, even if respective function blocks differ in transfer speed and can corrects data of the respective function blocks by one-error correcting circuit and is actualized at a low cost. SOLUTION: When the data A and B of the function blocks 1 and 2 are written into or read out of a memory 10, a memory controller 20 allocates the frequencies of memory access to the data A and B and the allocation rate of the access frequencies is made to correspond to the ratio '10MB/S:20MB/S =1:2' of the transfer speeds of the function blocks 1 and 2. Namely, the memory controller 20, after having accessed the memory 10 once for the data A, accesses the memory 10 twice for the data B.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control method when a plurality of functional blocks access one memory.

[0002]

2. Description of the Related Art FIG. 8 is a block diagram showing a conventional memory control method. In this memory control method, one memory 10 shared by two functional blocks 1 and 2 is
It is divided into two areas 11, 12 and two functional blocks 1,
2 alternately accessed the areas 11 and 12. That is, the memory controller 200 controls the functional block 2 to access the area 12 while the functional block 1 is accessing the area 11.
Then, next, when the functional block 1 accesses the area 12, the functional block 2 is controlled to access the area 11. In addition, DR is usually taken into consideration in terms of cost.
Although the AM is used as the memory 10, it is known that the DRAM is garbled with a certain probability due to the influence of α rays or the like. Therefore, when the DRAM is used as the memory 10, the error correction circuit 30 is added to ensure high reliability.

[0003]

However, the above-mentioned conventional memory control method has the following problems. In the conventional memory control method, the memory 10 is divided into two areas 11,
12 functional blocks 1 and 2 are divided into regions 11,
Since this is a technique of alternately accessing 12, the control lines from each functional block to the divided area are required by the number of divisions of the memory 10. For example, two functional blocks 1 and 2
In order to access the areas 11 and 12 with, two control lines are required. Therefore, as the number of functional blocks increases, a large number of control lines are required, which causes problems in wiring and cost. Further, for example, the transfer rate of the functional block 1 is 10 MB / s, and the transfer rate of the functional block 2 is 2
When the transfer rates of a plurality of functional blocks are different, such as 0 MB / s, it is difficult to control each functional block so that it can access any address. Further, when the DRAM is used for the memory 10, the number of error correction circuits 30 has to be increased corresponding to the number of divisions of the memory 10, which further increases the cost.

The present invention has been made in order to solve the above-mentioned problems. It is possible to perform accurate control even if the transfer speed of each functional block is different, and to correct the data of each functional block with one error correction circuit. It is an object of the present invention to provide a memory control method that is capable of achieving the above and can be realized at low cost.

[0005]

In order to solve the above-mentioned problems, the invention of claim 1 is such that a plurality of functional blocks share one memory, and the plurality of functional blocks and the above-mentioned one are controlled by a memory controller. In the memory control method for transferring data to and from a memory, the memory controller allocates the memory access times for the data of each of the functional blocks in a time-sharing manner, and allocates the access frequency allocation ratio to the plurality of functional blocks. It is configured to correspond to the speed ratio.

According to a second aspect of the present invention, in the memory control method according to the first aspect, the memory controller uses a ring buffer to first-in first-out data from the plurality of functional blocks and one memory. And

The inventions of claims 3 and 4 are defined by claim 1.
In the memory control method according to claim 2, a DRAM is used as the one memory, and an error correction circuit is interposed between the memory controller and the DRAM to perform data error correction.

According to the invention of claim 1, data is transferred between the plurality of functional blocks and one memory under the control of the memory controller. At this time, the number of times of memory access for the data of each functional block is increased. Are allocated in a time division manner, and the allocation ratio of the number of times of access is associated with the transfer speed ratio of a plurality of functional blocks.
As a result, the amount of data corresponding to the transfer speed of the plurality of functional blocks is transferred between the memory and the memory controller.

According to the second aspect of the present invention, the data from the plurality of functional blocks and the one memory is first-in first-out in the ring buffer, and the data is continuously transferred.

According to the third and fourth aspects of the invention, if there is an error in the data transferred by the access from the memory controller to the DRAM, the error is corrected by the error correction circuit.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a block diagram showing a memory control method according to a first embodiment of the present invention. In the memory control method of this embodiment, the two functional blocks 1 and 2 are
Under the control of the memory controller 20 which shares one memory 10 and has the FIFOs 21 and 22, data A, between these two functional blocks 1 and 2 and the memory 10 are controlled.
This is a method of transferring B.

First, the data A and B of the functional blocks 1 and 2
A control method when writing data to the memory 10 will be described.
If the transfer rates of the data A and B by the functional blocks 1 and 2 are 10 MB / s and 20 MB / s, respectively, the memory controller 20 transfers the data A and B to the transfer rate of 10 MB / s.
It is necessary to write to the memory 10 at s, 20 MB / s.
Data A and B from the functional blocks 1 and 2 are transferred to the FIFOs 21 and 22 of the memory controller 20 at a transfer rate of 10 MB.
/ S, 20 MB / s. Then, the memory controller 20 determines the number of accesses to the data A and the data B.
And the number of times of access of are assigned in a time-sharing manner. Further, the allocation ratio of the access counts of the data A and B corresponds to the transfer speed ratio of the functional blocks 1 and 2. Specifically, the ratio of the transfer rates of the data A and B is “10 MB / s: 20 MB
/ S ”, that is,“ 1: 2 ”, the memory controller 20 writes the data A from the FIFO 21 to the memory 10 once, and then writes the data B from the FIFO 22 to the memory 10.
Write twice to. By repeating this for 1 second, the memory controller 20 writes the data A and B in the memory 10 at 30 MB / s.

FIG. 2 is a schematic diagram showing an access state to the memory 10. As shown in FIG. 2, the memory controller 20 repeats the access of “data A, data B, data B” within one second, and transfers all the data A, B in the FIFO 21, 22 to the memory 10. This allows
Looking at the span of 1 second, data A is 10MB in 1 second.
This means that the data B has been transferred by 20 MB per second. That is, the data A is written from the FIFO 21 to the memory 10 at a transfer rate of 10 MB / s equal to the transfer rate of the functional block 1, and at the same time, the data B is transferred to the FIFO at a transfer rate of 20 MB / s equal to the transfer rate of the functional block 2.
It is written in the memory 10 from O22.

Writing of such data A and B is performed by the FIF.
It is continuously performed by the functions of O21 and 22. That is, as shown in FIG. 2, since the memory controller 20 repeats the operation of writing the data A once and then the data B twice, as shown in FIG. 3, the memory controller 20 can be regarded as a switch. . According to this switching operation, 1 is stored in the memory 10 for the data A.
After the first access, the access time for the data B is twice before the next data A is accessed, and the data A is in the dormant state during that time. The same applies to the data B, so that the data A and B are transferred intermittently. In contrast, in the present embodiment, FIG.
As shown in FIG.
Since the data A and B are transferred via the st In First Out) 21 and 22, the next data A and B are transferred to the FIFOs 21 and 2 within the pause time of the data A and B.
2 and the data A and B are continuously transferred. It should be noted that the FIFOs 21 and 22 need not be used when the transfer speed has a margin and the continuous operation is not required.

Next, the writing and reading operations to and from the memory 10 by the memory controller 20 will be described. For example,
When the data A from the functional block 1 is written to the memory 10 and the data B is read from the memory 10 and transferred to the functional block 2, the memory controller 20 writes the data A from the FIFO 21 to the memory 10 once, The data B is read from the memory 10 to the FIFO 22 twice. As a result, the data A is transferred to the memory 10 at a transfer rate of 10 MB / s, and the data B is transferred at a transfer rate of 20 MB / s.
The data is transferred from the memory 10 to the FIFO 22 in s. Further, when the data A and B are read from the memory 10, the data A may be read once and then the data B may be read twice.

As described above, according to the memory control method of this embodiment, the data A of the functional block 1 and the data B of the functional block 2 are transferred almost simultaneously at the same time without dividing one memory 10. Because of the configuration, it is not necessary to add control lines between the memory 10 and the memory controller 20 according to the number of the functional blocks 1 and 2, and the cost can be suppressed to that extent. Even if the transfer speeds of the functional blocks 1 and 2 are different as described above, the data A and B can be transferred at the transfer speed of the functional blocks 1 and 2 without using any complicated control technique.

(Second Embodiment) FIG. 4 shows a second embodiment of the present invention.
3 is a block diagram showing a memory control method according to the embodiment of FIG. In the memory control method of this embodiment, the three functional blocks 1, 2, and 3 share one memory 10,
The difference from the first embodiment is that the data A, B, and C are transferred under the control of the memory controller 20 having 1 to 23. In this embodiment, for example, the functional block 1
Data A transfer rate is 10MB / s, functional block 2
Data B transfer rate is 20MB / s, functional block 3
If the transfer rate of the data C of 30 is set to 30 MB / s, writing of these data A, B, and C into the memory 10 is performed as shown in FIG. That is, for data A,
After the write access from the FIFO 21 to the memory 10 is performed once, for the data C, the FIFO 23 to the memory 1
Write to 0 three times, and then, for data B,
Write access to the memory 10 from the FIFO 22 is performed twice. By repeating such access for 1 second, the memory controller 20 can transfer data at a transfer rate of 60 MB / s.
Is written in the memory 10. As a result, the data A has a transfer rate of 10 MB / equal to the transfer rate of the functional block 1.
The data C is written from the FIFO 21 to the memory 10 at s, and the data C is transferred at a transfer rate of 30M which is equal to the transfer rate of the functional block 3.
B / s is written from the FIFO 23 to the memory 10 and the data B is equal to the transfer rate of the functional block 2
The data is written from the FIFO 22 to the memory 10 at 0 MB / s.

FIG. 6 is a block diagram showing an example in which this embodiment is applied to a tape streamer device. The functional block 1 is a SCSI controller, the functional block 2 is a tape recording and reproducing device, and the functional block 3 is a CPU.
It is. As a result, the data A from the SCSI bus is transferred to the SCSI controller 1 via the memory controller 20.
To the memory 10 and temporarily store it in the memory 10. Then, in synchronization with the movement of the tape of the tape recording / reproducing apparatus 2, the data A in the memory 10 can be read to the tape recording / reproducing apparatus 2 and recorded on the tape. On the contrary, the data B on the tape of the tape recording and reproducing device 2 is transferred to the memory 1 via the memory controller 20.
It is also possible to transfer the data B once from the memory 10 to the SCSI controller 1 by a SCSI command or the like. Furthermore, the data C can be read from and written to the memory 10 from the CPU 3 as needed. The other configuration, operation, and effect are the same as those of the first embodiment, and the description thereof is omitted.

(Third Embodiment) FIG. 7 shows a third embodiment of the present invention.
3 is a block diagram showing a memory control method according to the embodiment of FIG. The memory control method according to the present embodiment uses the DRAM 10 as the memory 10, and the error correction circuit 30 performs error correction of data between the DRAM 10 and the memory controller 20. That is, the memory according to the first and second embodiments. Different from the control method. Data A of function blocks 1 to 3
The transfer rate of C to 10 m is set to 10 m as in the second embodiment.
If b / s, 20 MB / s, and 30 MB / s are set, the DRA can be accessed at the access count ratio of the transfer rate ratio “1: 2: 3”.
Data A between M10 and memory controller 20
Transfer of C is performed. Then, the error due to garbled bits in the DRAM 10 is corrected by the error correction circuit 30. As described above, since the data A to C of the functional blocks 1 to 3 are transferred almost simultaneously without dividing one DRAM 10, the error correction circuit 30 provided between the DRAM 10 and the memory controller 20 is provided. One is enough. The other configuration, operation, and effect are the same as those of the first and second embodiments, and thus description thereof is omitted.

The present invention is not limited to the above embodiment, but various modifications and changes can be made within the scope of the invention. For example, in the first to third embodiments described above, the number of functional blocks is two or three, but
It is not limited to this. The number of functional blocks is arbitrary as long as the memory controller allocates the number of memory accesses for the data of each functional block in a time-sharing manner and the allocation ratio of the number of accesses corresponds to the transfer speed ratio of a plurality of functional blocks. Of course, it can be set to. In this case, by providing FIFOs in the memory controller 20 as many as the functional blocks, continuous operation becomes possible.

[0021]

As described in detail above, according to the memory control method of the present invention, the amount of data corresponding to the transfer speed of a plurality of functional blocks is transferred in a time division manner between the memory and the memory controller. Therefore, it is not necessary to add control lines between the memory and the memory controller in correspondence with the number of functional blocks, and as a result, it is possible to reduce the cost of the device that implements the present method.
Further, even if the transfer speed of each functional block is different, it is possible to accurately control the transfer of the data of each functional block. Further, the data of each functional block can be corrected by one error correction circuit without adding an error correction circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a memory control method according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram showing an access state to a memory by the memory control method of FIG.

FIG. 3 is a schematic diagram showing a switch function of a memory controller.

FIG. 4 is a block diagram showing a memory control method according to a second embodiment of the present invention.

5 is a schematic diagram showing a memory access state according to the memory control method of FIG. 4;

6 is a block diagram showing an example in which the memory control method of FIG. 4 is applied to a tape streamer device.

FIG. 7 is a block diagram showing a memory control method according to a third embodiment of the present invention.

FIG. 8 is a block diagram showing a memory control method according to a conventional example.

[Explanation of symbols]

1 to 3 ... Functional block, 10 ... Memory, 2
0 ... Memory controller, 21-23 ... FI
FO, 30 ... Error correction circuit, A, B, C ...
·data.

Claims (4)

[Claims] 1. A memory control method in which a plurality of functional blocks share one memory, and data is transferred between the plurality of functional blocks and the one memory under the control of a memory controller. Allocate the number of memory accesses for the data of each functional block above in a time-sharing manner,
The memory control method, wherein the allocation ratio of the number of accesses corresponds to the transfer speed ratio of the plurality of functional blocks. 2. The memory control method according to claim 1, wherein the memory controller is a first-in first-out first-in first-out mode using a ring buffer for data from the plurality of functional blocks and one memory. Memory control method. 3. The memory control method according to claim 1, wherein a DRAM is used as the one memory, and an error correction circuit is interposed between the memory controller and the DRAM to perform data error correction. A memory control method characterized by the above. 4. The memory control method according to claim 2, wherein a DRAM is used as the one memory, and an error correction circuit is interposed between the memory controller and the DRAM to correct an error in data. A memory control method characterized by the above.