JPH0927454A - Mask for selective evaporation - Google Patents

Mask for selective evaporation

Info

Publication number
JPH0927454A
JPH0927454A JP17721795A JP17721795A JPH0927454A JP H0927454 A JPH0927454 A JP H0927454A JP 17721795 A JP17721795 A JP 17721795A JP 17721795 A JP17721795 A JP 17721795A JP H0927454 A JPH0927454 A JP H0927454A
Authority
JP
Japan
Prior art keywords
mask
vapor deposition
wafer
selective
holder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17721795A
Other languages
Japanese (ja)
Inventor
Akira Amano
彰 天野
Yoshikazu Takahashi
良和 高橋
Koichi Hashimoto
孝一 橋本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP17721795A priority Critical patent/JPH0927454A/en
Publication of JPH0927454A publication Critical patent/JPH0927454A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To eliminate mask displacement during the formation of metal electrodes or the like on a semiconductor device by selective evaporation, and thereby form the electrodes excellent in pattern shape accuracy. SOLUTION: Stress buffering holes 25 are formed between the pattern area 22 of a mask 21 for selective evaporation and mask fixing areas containing fixing holes 23. This prevents the mask 21 from being floated due to thermal expansion during evaporation and from being deformed due to screw tightening pressure in the fixing areas.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、半導体デバイスや半
導体実装基板に金属膜等を選択的に蒸着するための選択
蒸着用マスクに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a selective vapor deposition mask for selectively depositing a metal film or the like on a semiconductor device or a semiconductor mounting substrate.

【0002】[0002]

【従来の技術】半導体基板や実装用基板への電極形成等
を目的として、マスクを使用した金属膜の選択的な蒸着
は通常良く行われている。従来の選択蒸着の方法を図を
用いて説明する。図3は選択蒸着用マスクであり、
(a)は平面図、(b)はそのA−A線における断面図
である。選択蒸着用マスク1は、一般に厚さが0.1m
m程度の金属板で、その中央部は蒸着するためのパター
ンが形成されたパターン部2となっており、周辺部にこ
のマスク1およびウェハを後出のウェハホルダに固定す
るためのマスク固定用穴3および、マスク1とウェハホ
ルダを後出の蒸着ホルダに固定するためのホルダ固定用
穴4が設けられている。図4は蒸着するためのウェハ6
で(a)は平面図、(b)はそのB−B線における断面
図である。図5はウェハを収容しマスクを固定するため
のウェハホルダ7で(a)は平面図、(b)はそのC−
C線における断面図である。ウェハホルダ7にはウェハ
を収容するためのガイド穴9、ウェハを取り出すための
突き上げ穴10、マスク固定用ネジ11およびホルダ固
定用穴12が設けられている。
2. Description of the Related Art Selective deposition of a metal film using a mask is usually well performed for the purpose of forming electrodes on a semiconductor substrate or a mounting substrate. A conventional selective vapor deposition method will be described with reference to the drawings. FIG. 3 shows a mask for selective vapor deposition,
(A) is a top view, (b) is sectional drawing in the AA line. The selective vapor deposition mask 1 generally has a thickness of 0.1 m.
A metal plate having a size of about m, and a central portion thereof is a pattern portion 2 on which a pattern for vapor deposition is formed, and a mask fixing hole for fixing the mask 1 and the wafer to a wafer holder to be described later in the peripheral portion. 3 and a holder fixing hole 4 for fixing the mask 1 and the wafer holder to a vapor deposition holder to be described later. FIG. 4 shows a wafer 6 for vapor deposition.
(A) is a plan view and (b) is a cross-sectional view taken along the line BB. FIG. 5 shows a wafer holder 7 for accommodating a wafer and fixing a mask. (A) is a plan view, (b) is its C-
It is sectional drawing in the C line. The wafer holder 7 is provided with a guide hole 9 for accommodating the wafer, a push-up hole 10 for taking out the wafer, a mask fixing screw 11, and a holder fixing hole 12.

【0003】ウェハホルダ7のガイド穴9にウェハ6を
セットし、その上から選択蒸着用マスク1を被せ、マス
ク固定用ネジ11にナツト13を嵌めてセットした状態
を図6に示す。(a)は平面図、(b)はそのD−D線
における断面図である。図9は、電子ビーム蒸着装置の
概要を示す。図示しない開口扉を持つ真空室41内に、
図7に示すようにウェハ6およびマスク1を固定したウ
ェハホルダ7を、蒸着ホルダ40に多数取りつけた後、
扉を閉め、真空弁42を開け、図示しない真空ポンプに
より、真空室41内を真空にする。所定の真空度に達し
た後、電子銃43から電子ビーム46を発生させ、ハー
ス44内のソース金属45に電子ビーム46を当て、ソ
ース金属45を加熱溶融し、蒸発させて、ソース分子4
7をホルダ7内のウェハ6にマスク1を通して選択蒸着
する。多数のウェハホルダ7は、回転機構等により蒸着
中に位置を変え、多数のウェハが一度に処理できるよう
になっている。
FIG. 6 shows a state in which the wafer 6 is set in the guide hole 9 of the wafer holder 7, the selective vapor deposition mask 1 is covered thereover, and the nut 13 is fitted into the mask fixing screw 11 to set it. (A) is a top view, (b) is sectional drawing in the DD line. FIG. 9 shows an outline of the electron beam evaporation apparatus. In the vacuum chamber 41 having an opening door (not shown),
After attaching a large number of wafer holders 7 to which the wafer 6 and the mask 1 are fixed to the vapor deposition holder 40 as shown in FIG.
The door is closed, the vacuum valve 42 is opened, and the vacuum chamber 41 is evacuated by a vacuum pump (not shown). After reaching a predetermined vacuum degree, an electron beam 46 is generated from the electron gun 43, the electron beam 46 is applied to the source metal 45 in the hearth 44, the source metal 45 is heated and melted, and the source molecule 4 is evaporated.
7 is selectively vapor-deposited on the wafer 6 in the holder 7 through the mask 1. A large number of wafer holders 7 can be processed at once by changing their positions during vapor deposition by means of a rotating mechanism or the like.

【0004】[0004]

【発明が解決しようとする課題】しかし、図6、図9で
説明したような従来の選択蒸着法では、蒸着時の熱によ
りマスク1の中央部が部分的に熱膨張し、その結果マス
ク1の浮き上がり14が起きやすい。蒸着時の昇温は時
に100℃を越えることがある。また、図6(b)に示
すようにマスク固定用ねじ11にナット13を締めつけ
たときのねじ締め圧により、その近傍でマスク1の変形
15を生じ易い。
However, in the conventional selective vapor deposition method described with reference to FIGS. 6 and 9, the central portion of the mask 1 partially thermally expands due to the heat during vapor deposition, and as a result, the mask 1 Uplift 14 is easy to occur. The temperature rise during vapor deposition sometimes exceeds 100 ° C. Further, as shown in FIG. 6B, due to the screw tightening pressure when the nut 13 is tightened to the mask fixing screw 11, the deformation 15 of the mask 1 is likely to occur in the vicinity thereof.

【0005】これらのマスク1の熱膨張による浮き上が
り14や、マスク1をウェハホルダ7にねじ締め固定を
する時のねじ締め圧によるマスクの変形15は、選択蒸
着した金属膜の位置ずれや、形状不正を生ずる。図7
(a)は、選択蒸着後のウェハ6の中の一チップ8の拡
大図、(b)はそのE−E線における断面図であるが、
上述の不具合により選択蒸着された電極16がマスクず
れを起こしており、またマスク1とウェハ6の間隙によ
り滲み出し17を生じている。なお、このウェハ6で
は、既に一層目の電極18が形成されたウェハに二層目
の電極16を選択蒸着した場合である。
The floating 14 due to the thermal expansion of the mask 1 and the deformation 15 of the mask due to the screw tightening pressure when the mask 1 is screwed and fixed to the wafer holder 7 cause the positional deviation of the selectively deposited metal film and the incorrect shape. Cause Figure 7
(A) is an enlarged view of one chip 8 in the wafer 6 after selective vapor deposition, and (b) is a sectional view taken along the line EE in FIG.
Due to the above-mentioned problems, the selectively vapor-deposited electrode 16 causes a mask shift, and a gap 17 between the mask 1 and the wafer 6 causes an exudation 17. In this wafer 6, the electrode 16 of the second layer is selectively vapor-deposited on the wafer on which the electrode 18 of the first layer is already formed.

【0006】以上の問題に鑑みて、本発明の目的は、上
述の不具合を無くし、パターン形状が良好でマスクと被
堆積基板との合わせ精度の良い選択蒸着ができる選択蒸
着用マスクを提供することにある。
In view of the above problems, it is an object of the present invention to provide a selective vapor deposition mask which eliminates the above-mentioned problems, has a good pattern shape, and is capable of performing selective vapor deposition with good alignment accuracy between the mask and a deposition target substrate. It is in.

【0007】[0007]

【課題を解決するための手段】上記課題解決のため本発
明は、被堆積基板に選択的な蒸着を行うためのパターン
部と、被堆積基板を間に挟んでホルダーに固定するため
の固定部とを有する選択蒸着用マスクにおいて、固定部
と、パターン部との間に応力緩衝部を備えるものとす
る。
In order to solve the above problems, the present invention provides a pattern portion for performing selective vapor deposition on a deposition substrate and a fixing portion for fixing the deposition substrate to a holder with the deposition substrate interposed therebetween. In the mask for selective vapor deposition having, a stress buffering portion is provided between the fixed portion and the pattern portion.

【0008】特に、応力緩衝部が穴からなり、その穴が
細長い穴からなるものがよい。更に、応力緩衝部がパタ
ーン部の周囲の50%以上を覆うものがよい。
Particularly, it is preferable that the stress buffering portion is formed of a hole and the hole is formed of an elongated hole. Furthermore, it is preferable that the stress buffering portion covers 50% or more of the periphery of the pattern portion.

【0009】[0009]

【作用】上記の手段を講じて、固定部と、パターン部と
の間に応力緩衝部を備えた選択蒸着用マスクとすること
によって、パターン部の熱膨張や、固定部のねじしめ圧
力等による応力が緩衝部で吸収することができ、マスク
の変形が回避できる。もっともシンプルな応力緩衝部と
しては、細長いスリット状の穴を設ければ、よく、ま
た、応力緩衝部がパターン部の周囲の50%以上を覆う
ものとすれば、緩衝部での応力吸収が確実に行われる。
By taking the above-mentioned means to form a mask for selective vapor deposition having a stress buffer between the fixed portion and the pattern portion, thermal expansion of the pattern portion, screwing pressure of the fixed portion, etc. The stress can be absorbed by the buffer portion, and the deformation of the mask can be avoided. The simplest stress buffering part is to have a long and narrow slit-shaped hole, and if the stress buffering part covers 50% or more of the periphery of the pattern part, the stress absorption in the buffering part is sure. To be done.

【0010】[0010]

【実施例】以下、図面を参照しながら本発明の実施例に
ついて説明する。図1は、本発明第一の実施例の選択蒸
着用マスクであり、例えば厚さ0.15mmのFe−N
i合金板からなる。(a)はその平面図、(b)はその
F−F線における断面図である。図1(a)のマスク2
1は、従来のマスクのように中央部のパターン部22と
マスク固定用穴23、ホルダ固定用穴24の他に、マス
ク固定用穴23とパターン部22の間に細長い形状の緩
衝用穴25が四辺に設けられている。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a mask for selective vapor deposition according to the first embodiment of the present invention, for example, a Fe—N film having a thickness of 0.15 mm.
It consists of an i alloy plate. (A) is the top view, (b) is sectional drawing in the FF line. Mask 2 of FIG. 1 (a)
1 is a buffer hole 25 having an elongated shape between the mask fixing hole 23 and the pattern portion 22 in addition to the central pattern portion 22, the mask fixing hole 23, and the holder fixing hole 24 like a conventional mask. Are provided on all sides.

【0011】図2に、図5に示したウェハホルダ7にウ
ェハ26とマスク21とを動かないようにしっかりと固
定した状態を示す。(a)は平面図、(b)はそのG−
G線における断面図である。ウェハホルダ7のガイド穴
9にウェハ26を挿入し、その上から図1に示すマスク
21を被せて、ウェハパターンとマスクのパターン部2
2を目視合わせをおこない、図2(a)に示すようにウ
ェハホルダ7に設けたマスク固定用ねじ11にナツト1
3をしめて、ウェハ26とマスク21が動かないように
しっかりと固定する。このとき、ワッシャ19を挟むと
なおよい。
FIG. 2 shows a state in which the wafer 26 and the mask 21 are firmly fixed to the wafer holder 7 shown in FIG. 5 so as not to move. (A) is a plan view, (b) is its G-
It is sectional drawing in the G line. The wafer 26 is inserted into the guide hole 9 of the wafer holder 7, and the mask 21 shown in FIG.
2 is visually aligned, and the nut 1 is attached to the mask fixing screw 11 provided on the wafer holder 7 as shown in FIG.
3 is tightly fixed so that the wafer 26 and the mask 21 do not move. At this time, it is better to sandwich the washer 19.

【0012】図2に示すようにウェハ26とマスク21
を固定したホルダ7を、図9に示す電子ビーム蒸着装置
の真空室41内の蒸着ホルダー40に取りつけ、蒸着ホ
ルダ支持棒48に固定する。真空弁42を開けて、図示
されない真空ポンプにより、所定の真空度にした後、電
子銃43から、電子ビーム46を発生させ、ソースハー
ス44の中にあるソース金属45に電子ビーム46を当
てて溶融し、蒸着ソース分子47として飛ばし、ウェハ
26にマスク21を通して選択蒸着する。本実施例にお
いては、既にAlの電極が形成されているウェハ26
に、Ti/Ni/Auの三層を連続して選択蒸着した。
As shown in FIG. 2, the wafer 26 and the mask 21
The holder 7 to which is fixed is attached to the vapor deposition holder 40 in the vacuum chamber 41 of the electron beam vapor deposition apparatus shown in FIG. After the vacuum valve 42 is opened and a vacuum pump (not shown) is used to set a predetermined degree of vacuum, an electron beam 46 is generated from the electron gun 43, and the electron beam 46 is applied to the source metal 45 in the source hearth 44. It melts and is blown as vapor deposition source molecules 47, and is selectively vapor deposited on the wafer 26 through the mask 21. In the present embodiment, the wafer 26 on which Al electrodes have already been formed
Then, three layers of Ti / Ni / Au were continuously and selectively vapor deposited.

【0013】図8(a)は、本発明の実施例の選択蒸着
用マスク21を使用した選択蒸着後のウェハ26の中の
一チップ28の拡大図、(b)はそのH−H線における
断面図である。従来法での図6に示したような熱膨張に
よるマスクの変形14やねじ締め圧によるマスクの変形
15は、本発明では、マスク21に設けた緩衝穴25に
よって防止されている。特にねじ締め圧によるマスクの
変形を避けるには、ナット13の下にワッシャ19を挟
むとなおよい。その結果、図8(a)、(b)に示すよ
うに、上述の不具合によるマスクずれや、マスク21と
ウェハ26の間隙による滲み出しは見られず、一層目の
電極38に精度良くマスク合わせされて選択蒸着された
Ti/Ni/Auの三層からなる電極36が得られてい
る。
FIG. 8A is an enlarged view of one chip 28 in the wafer 26 after the selective vapor deposition using the selective vapor deposition mask 21 of the embodiment of the present invention, and FIG. 8B is the H-H line thereof. FIG. In the present invention, the mask deformation 14 due to the thermal expansion and the mask deformation 15 due to the screwing pressure as shown in FIG. 6 in the conventional method are prevented by the buffer hole 25 provided in the mask 21 in the present invention. Particularly, in order to avoid the deformation of the mask due to the screw tightening pressure, it is more preferable to sandwich the washer 19 under the nut 13. As a result, as shown in FIGS. 8A and 8B, no mask displacement due to the above-described defects and no seeping due to the gap between the mask 21 and the wafer 26 are observed, and the mask 38 is accurately aligned with the electrode 38 of the first layer. Thus, the electrode 36 having the three layers of Ti / Ni / Au selectively deposited is obtained.

【0014】図10は、本発明第二の実施例の選択蒸着
用マスクである。この場合は、マスク61の緩衝用穴6
5は、パターン部62との間のマスク固定用穴63の周
りに円弧状に設けられている。図11は、本発明第三の
実施例の選択蒸着用マスクである。この場合は、マスク
81の緩衝用穴85は、パターン部82とマスク固定用
穴83との間に網状に設けられている。このように緩衝
用穴は、細長い穴に限らず種々の変形が考えられる。
FIG. 10 shows a mask for selective vapor deposition according to the second embodiment of the present invention. In this case, the buffer hole 6 of the mask 61
5 is provided in a circular arc shape around the mask fixing hole 63 between the pattern portion 62 and the pattern portion 62. FIG. 11 is a mask for selective vapor deposition according to the third embodiment of the present invention. In this case, the buffer hole 85 of the mask 81 is provided in a mesh shape between the pattern portion 82 and the mask fixing hole 83. As described above, the buffer hole is not limited to the elongated hole, and various modifications can be considered.

【0015】上記の例では電子ビーム蒸着の例を示した
が、その他に、スパツタやCVD法による蒸着において
も、本発明の選択蒸着マスクは使用できる。また、蒸着
する物質も、金属膜に限らず、絶縁物質や半導体とする
こともできる。
Although the example of electron beam vapor deposition is shown in the above example, the selective vapor deposition mask of the present invention can also be used in vapor deposition by a sputtering method or a CVD method. Further, the substance to be vapor-deposited is not limited to the metal film, but may be an insulating substance or a semiconductor.

【0016】[0016]

【発明の効果】以上説明したように、マスクとウェハ等
の被堆積基板をホルダに固定し、蒸着装置中で金属膜等
の選択蒸着を行うとき、選択蒸着用マスクのパターン部
の周囲に、応力緩衝用の緩衝部を設けたマスクとするこ
とにより、蒸着時の熱膨張や、固定部のねじ締め等によ
る応力が緩和され、マスクの変形等が蒸着膜に影響する
ことがなく、パターンの形状精度が高められる。また、
すでにあるパターンとのマスク合わせを行うものであれ
ば、マスク合わせ精度が向上する。
As described above, when the deposition target substrate such as the mask and the wafer is fixed to the holder and the selective deposition of the metal film or the like is performed in the deposition apparatus, the selective deposition mask is surrounded by the pattern portion. By using a mask provided with a buffer portion for stress buffering, thermal expansion during vapor deposition, stress due to screw tightening of the fixing portion, etc. is relieved, deformation of the mask does not affect the vapor deposition film, and Shape accuracy is improved. Also,
If the mask alignment with the existing pattern is performed, the mask alignment accuracy is improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a)は本発明の実施例の選択蒸着用マスクの
平面図、(b)は、そのF−F線における断面図
1A is a plan view of a mask for selective vapor deposition according to an embodiment of the present invention, and FIG. 1B is a sectional view taken along line FF thereof.

【図2】(a)はホルダにウェハと本発明の実施例の選
択蒸着用マスクをセットした状態の平面図、(b)は、
そのG−G線における断面図
FIG. 2A is a plan view showing a state in which a wafer and a mask for selective vapor deposition according to an embodiment of the present invention are set in a holder, and FIG.
Sectional drawing in the GG line

【図3】(a)は従来の選択蒸着用マスクの平面図、
(b)は、そのA−A線における断面図
FIG. 3A is a plan view of a conventional mask for selective vapor deposition,
(B) is sectional drawing in the AA line.

【図4】(a)はシリコンウエハの平面図、(b)は、
そのB−B線における断面図
FIG. 4A is a plan view of a silicon wafer, and FIG.
Sectional drawing in the BB line

【図5】(a)はホルダの平面図、(b)は、そのC−
C線における断面図
FIG. 5A is a plan view of the holder, and FIG.
Sectional view along line C

【図6】(a)はホルダにウェハと従来の選択蒸着用マ
スクをセットした状態の平面図、(b)は、そのD−D
線における断面図
6A is a plan view showing a state where a wafer and a conventional mask for selective vapor deposition are set in a holder, and FIG. 6B is a DD view thereof.
Sectional view at the line

【図7】(a)は従来の選択蒸着用マスクを使用して選
択蒸着したチップの平面図、(b)は、そのE−E線に
おける断面図
FIG. 7A is a plan view of a chip selectively vapor-deposited using a conventional selective vapor deposition mask, and FIG. 7B is a cross-sectional view taken along the line EE.

【図8】(a)は本発明の実施例の選択蒸着用マスクを
使用して選択蒸着したチップの平面図、(b)は、その
H−H線における断面図
FIG. 8A is a plan view of a chip selectively vapor-deposited by using the selective vapor deposition mask of the embodiment of the present invention, and FIG. 8B is a cross-sectional view taken along the line HH.

【図9】電子ビーム蒸着装置の概要図FIG. 9 is a schematic diagram of an electron beam vapor deposition apparatus.

【図10】本発明の第二の実施例の選択蒸着用マスクの
平面図
FIG. 10 is a plan view of a mask for selective vapor deposition according to a second embodiment of the present invention.

【図11】本発明の第三の実施例の選択蒸着用マスクの
平面図
FIG. 11 is a plan view of a mask for selective vapor deposition according to a third embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1、21、61、81 マスク 2、22、62、82 パターン部 3、23、63、83 マスク固定用穴 4、24 ホルダ固定用穴 6、26 ウェハ 8、28 チップ 7 ウェハホルダ 9 ガイド穴 10 突き出し穴 11 マスク固定用ネジ 12 ホルダ固定用穴 13 ナット 14 浮き上がり 15 変形 16、36 電極 17 滲み出し 18、38 一層目電極 19 ワッシャ 25、65、85 緩衝用穴 40 蒸着ホルダ 41 真空室 42 真空弁 43 電子銃 44 ハース 45 ソース金属 46 電子ビーム 47 烝発分子 48 支持棒 1, 21, 61, 81 Mask 2, 22, 62, 82 Pattern part 3, 23, 63, 83 Mask fixing hole 4, 24 Holder fixing hole 6, 26 Wafer 8, 28 Chip 7 Wafer holder 9 Guide hole 10 Projection Hole 11 Mask fixing screw 12 Holder fixing hole 13 Nut 14 Lifting 15 Deformation 16, 36 Electrode 17 Exudation 18, 38 First layer electrode 19 Washer 25, 65, 85 Buffer hole 40 Evaporation holder 41 Vacuum chamber 42 Vacuum valve 43 Electron gun 44 Hearth 45 Source metal 46 Electron beam 47 Firing molecule 48 Support rod

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】選択的な蒸着を行うためのパターン部と、
被堆積基板を間に挟んでホルダーに固定するための固定
部とを有する選択蒸着用マスクにおいて、固定部と、パ
ターン部との間に応力緩衝部を備えた選択蒸着用マス
ク。
1. A pattern portion for performing selective vapor deposition,
A selective vapor deposition mask having a fixing portion for fixing a deposition target substrate to a holder with the substrate being sandwiched therebetween, wherein the selective vapor deposition mask includes a stress buffer portion between the fixing portion and the pattern portion.
【請求項2】応力緩衝部が穴からなることを特徴とする
請求項1に記載の選択蒸着用マスク。
2. The mask for selective vapor deposition according to claim 1, wherein the stress buffering portion comprises a hole.
【請求項3】応力緩衝部が細長い穴からなることを特徴
とする請求項2に記載の選択蒸着用マスク。
3. The mask for selective vapor deposition according to claim 2, wherein the stress buffering portion comprises an elongated hole.
【請求項4】応力緩衝部がパターン部の周囲の50%以
上を覆うことを特徴とする請求項2または3に記載の選
択蒸着用マスク。
4. The selective deposition mask according to claim 2, wherein the stress buffering portion covers 50% or more of the periphery of the pattern portion.
JP17721795A 1995-07-13 1995-07-13 Mask for selective evaporation Pending JPH0927454A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17721795A JPH0927454A (en) 1995-07-13 1995-07-13 Mask for selective evaporation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17721795A JPH0927454A (en) 1995-07-13 1995-07-13 Mask for selective evaporation

Publications (1)

Publication Number Publication Date
JPH0927454A true JPH0927454A (en) 1997-01-28

Family

ID=16027214

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17721795A Pending JPH0927454A (en) 1995-07-13 1995-07-13 Mask for selective evaporation

Country Status (1)

Country Link
JP (1) JPH0927454A (en)

Cited By (9)

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Publication number Priority date Publication date Assignee Title
JP2004296436A (en) * 2003-03-13 2004-10-21 Toray Ind Inc Organic electroluminescent device, and manufacturing method of the same
US6821348B2 (en) 2002-02-14 2004-11-23 3M Innovative Properties Company In-line deposition processes for circuit fabrication
US6897164B2 (en) 2002-02-14 2005-05-24 3M Innovative Properties Company Aperture masks for circuit fabrication
CN100421283C (en) * 2003-12-02 2008-09-24 索尼株式会社 Deposition mask and manufacturing method thereof
JP2010062125A (en) * 2008-09-01 2010-03-18 Samsung Mobile Display Co Ltd Mask for thin film deposition and method of manufacturing organic electroluminescent element using the same
US7763114B2 (en) 2005-12-28 2010-07-27 3M Innovative Properties Company Rotatable aperture mask assembly and deposition system
WO2015145944A1 (en) * 2014-03-25 2015-10-01 パナソニックIpマネジメント株式会社 Photoelectric conversion element and photoelectric conversion element manufacturing method
WO2020143217A1 (en) * 2019-01-09 2020-07-16 昆山工研院新型平板显示技术中心有限公司 Masking unit, and mask plate assembly provided with masking unit
JP2022532321A (en) * 2019-07-05 2022-07-14 ベイジン・ナウラ・マイクロエレクトロニクス・イクイップメント・カンパニー・リミテッド Mask structure and FCVA device

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6821348B2 (en) 2002-02-14 2004-11-23 3M Innovative Properties Company In-line deposition processes for circuit fabrication
US6897164B2 (en) 2002-02-14 2005-05-24 3M Innovative Properties Company Aperture masks for circuit fabrication
US7241688B2 (en) 2002-02-14 2007-07-10 3M Innovative Properties Company Aperture masks for circuit fabrication
US7297361B2 (en) 2002-02-14 2007-11-20 3M Innovative Properties Company In-line deposition processes for circuit fabrication
JP2004296436A (en) * 2003-03-13 2004-10-21 Toray Ind Inc Organic electroluminescent device, and manufacturing method of the same
JP4506214B2 (en) * 2003-03-13 2010-07-21 東レ株式会社 Organic electroluminescent device and manufacturing method thereof
CN100421283C (en) * 2003-12-02 2008-09-24 索尼株式会社 Deposition mask and manufacturing method thereof
US7763114B2 (en) 2005-12-28 2010-07-27 3M Innovative Properties Company Rotatable aperture mask assembly and deposition system
JP2010062125A (en) * 2008-09-01 2010-03-18 Samsung Mobile Display Co Ltd Mask for thin film deposition and method of manufacturing organic electroluminescent element using the same
US9441288B2 (en) 2008-09-01 2016-09-13 Samsung Display Co., Ltd. Mask for thin film deposition and method of manufacturing OLED using the same
US10147880B2 (en) 2008-09-01 2018-12-04 Samsung Display Co., Ltd. Mask for thin film deposition and method of manufacturing oled using the same
WO2015145944A1 (en) * 2014-03-25 2015-10-01 パナソニックIpマネジメント株式会社 Photoelectric conversion element and photoelectric conversion element manufacturing method
WO2020143217A1 (en) * 2019-01-09 2020-07-16 昆山工研院新型平板显示技术中心有限公司 Masking unit, and mask plate assembly provided with masking unit
JP2022532321A (en) * 2019-07-05 2022-07-14 ベイジン・ナウラ・マイクロエレクトロニクス・イクイップメント・カンパニー・リミテッド Mask structure and FCVA device

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