JPH09270698A - Cmos output buffer circuit for controlling drive current - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the CMOS output buffer circuit for controlling drive current in which the circuit configuration is simplified, high circuit integration is realized and a drive capability of the output buffer is easily in matching with a characteristic impedance of a transmission line. SOLUTION: Plural output buffers 01-04 including series connection of PMOS transistors(TRs) and NMOS TRs are connected in parallel and a switch circuit 3 controlling conduction/interruption of an input current is provided to a pre- stage of all the output buffers 01-04 and only any of the output buffers 01-04 receiving a control signal from the switch circuit 3 is operated and outputs a drive current and the entire drive current is controlled through optional combination of the outputs of the output buffers 01-04. Or the plural output buffers 01-04 may be selected to output different drive currents and the currents are preferably in terms of geometric series based on the reference current.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a drive current control C.
The present invention relates to a MOS output buffer circuit, and more particularly to a drive current control CMOS output buffer circuit for transmitting a signal through a printed wiring board or the like.

[0002]

2. Description of the Related Art Conventionally, a CMOS for driving current control of this type
The output buffer circuit is used for the purpose of supplying a drive current suitable for each of different external loads.

As a recent trend, the number of input buffers excluding the protection diode between the signal and the power supply in order to cope with hot-swap is increasing, so that the signal transmitted from the output buffer is almost entirely in the input buffer. It will return with reflection. Since this reflection amount is proportional to the driving capability of the output buffer, if an output buffer having a driving capability higher than necessary is selected, the reflection will be large and may cause a malfunction. On the other hand, an output buffer with too small drive capacity cannot obtain the required potential at the receiving end, and there is no choice but to wait for several reflections to obtain the required potential, which means that the delay time increases. The drive capability of the output buffer that matches the characteristic impedance of the transmission line is required.

In the techniques disclosed in Japanese Patent Application Laid-Open No. 63-204757 and Japanese Patent Application Laid-Open No. 3-117020, one set of p-channel MOS-FE is used to control the drive current.
To a reference CMOS output buffer composed of T and n-channel MOS-FET, several output buffers with output control capable of operating the output and stopping the output are connected in parallel, and the output buffer with the output control is provided. The technique for controlling the drive current of the CMOS output buffer by adding an additional output to the reference output by changing the operating number of is described.

[0005]

The first problem of the above-mentioned conventional technique is that the number of MOS transistors used becomes large.

The reason is that an output buffer with output control is required for the set type of drive current, and as a result the area becomes large, so the number of output buffers for drive current control that can be accommodated in one semiconductor package is limited. It means that the number will decrease and the degree of integration will deteriorate. The logic circuit for forming the output buffer with output control is a p-channel MOS-FET and an n-channel MOS-F.
Since it is composed of ET, the circuit becomes complicated, which is another reason why the scale becomes large.

The second problem is that it is difficult to match the drive current of the output buffer to the characteristic impedance of the transmission line such as a printed wiring board, and reflection of the transmission waveform cannot be suppressed.
That's what it means.

The reason for this is that the characteristic impedance of a transmission line such as a printed wiring board usually has a large manufacturing variation, and a fine adjustment of the drive current is required to cope with this, but it is required in the prior art. In order to output the drive current corresponding to the above, it is necessary to configure the output buffer circuit with many output buffers with output control, but this is not possible due to the limited area.

The object of the present invention is to simplify the circuit configuration,
It is an object of the present invention to provide a CMOS output buffer circuit for controlling a drive current, which can realize high integration.

Another object of the present invention is to easily control the drive current of the output buffer, and by selecting the drive current most suitable for the characteristic impedance of the transmission line, the signal reflection on the transmission line is reduced and the signal of the signal is reduced. It is an object of the present invention to provide a CMOS output buffer circuit for controlling a drive current that can realize high-speed transmission.

[0011]

In a CMOS output buffer circuit for controlling a drive current according to the present invention, a plurality of output buffers including a series connection structure of a pMOS transistor and an nMOS transistor are connected in parallel, and all output buffers are provided in front stages. Has a switch circuit that controls conduction and interruption of the input current, only the output buffer to which the control signal of the switch circuit is transmitted operates to output the drive current, and the entire drive is performed by an arbitrary combination of the output of the output buffer. It is possible to control the current.

Further, a plurality of output buffers may be set to output drive currents having different values, and the different drive current output values set in the plurality of output buffers are set with reference to the reference current value. It is preferable that they are set in geometric progression.

The switch circuit corresponding to one set of output buffers includes a pMOS transistor and an nMO of the output buffer.
The source is connected to each gate of the S transistor,
Two control nMOS transistors each having a drain connected to an input signal circuit common to all circuits and a gate commonly connected to a control signal circuit corresponding to the output buffer;
It may be composed of a resistor connecting the gate of the pMOS transistor of the output buffer to the power supply circuit and a resistor connecting the gate of the pMOS transistor of the output buffer to the ground circuit.

The output of the entire CMOS output buffer circuit is
It can be set by selecting and combining the individual CMOS output buffer circuits, and if the drive currents of the plurality of CMOS output buffers are changed in a ratio of 1: 2: 4: 8 ... Corresponding to the required output of the entire circuit,
By selecting the combination of CMOS output buffers to be operated by the output control circuit, the drive current can be finely changed with a small number of CMOS output buffers.

As described above, since the drive current can be finely changed, the drive capability of the output buffer can be matched with the characteristic impedance of the transmission line, and the reflection of the waveform due to the mismatch of the characteristic impedance can be suppressed. it can.

[0016]

Next, embodiments of the present invention will be described with reference to the drawings. 1 is a block diagram showing a configuration of a drive current controlling CMOS output buffer circuit according to an embodiment of the present invention, and FIG. 2 is a circuit showing a configuration of a drive current controlling CMOS output buffer circuit according to an embodiment of the present invention. It is a figure. In the figure, reference numeral 3 is a switch circuit, 5 is an input signal circuit, 6 is a control signal line, 7 is an output signal line, 8 and 9 are resistors,
01, 02, 03, 04 are CMOS output buffers, 1
1, 12, 13, and 14 are p-channel MOS-FETs, 2
1, 21, 23, 24 are n-channel MOS-FETs, 3
1, 31, 33, 34 are n-channel MOS-FETs, 4
1, 41, 43, 44 are n-channel MOS-FETs, 6
Reference numerals 1, 62, 63 and 64 are control signal lines.

One of the features of the present invention is that the drive currents of the plurality of CMOS output buffers are set to different values, but in the example shown in FIG. 2, the CMOS output buffers 01, 02, 03, 04 are provided. Has a drive current ratio of 1:
It is adjusted to 2: 4: 8, and the signal from the input signal circuit 5 passes through the switch circuit 3 and the CMOS output buffer 01,
It is configured to be transmitted to 02, 03, 04. Further, the switch circuit 3 has a configuration in which conduction and interruption can be controlled by the control signal line 6.

Next, the operation of the drive current controlling CMOS output buffer circuit of the present invention will be described with reference to the drawings.

Assuming that only the control signal line 61 to the CMOS output buffer 01 is conductive and the control signal lines 62, 63 and 64 to the other CMOS output buffers 02, 03 and 04 are cut off. CMOS output buffer 0
A CMOS output buffer in which only 1 operates and the drive current ratio is 1 can be realized. In addition, the CMOS output buffer 02,
Assuming that the control signal lines 62 and 63 of 03 are conductive and the control signal lines 61 and 64 of the CMOS output buffers 01 and 04 are cut off, the ratio of the drive current to the CMOS output buffer 02 of 2 and the drive current ratio is 2. The CMOS output buffer 03 of 4 operates, and a CMOS output buffer having a drive current ratio of 6 can be realized. As described above, there are 2 4 combinations of conduction and interruption of the control signal line 6, and a CMOS output buffer having a drive current ratio of 0 to 15 can be realized.

1 and 2, the case where four CMOS output buffers are connected in parallel has been described.
When three CMOS output buffers are connected in parallel, by setting the ratio of drive currents to 1: 2: 4, it is possible to realize CMOS output buffers with 2 3 powers, that is, 8 drive currents. Similarly, when 5 CMOS output buffers are connected in parallel, the drive current ratio is 1:
By using 2: 4: 8: 16, it is possible to realize a CMOS output buffer with a driving current of 2 to the fifth power, that is, 32 different driving currents.

Next, the circuit of the present invention will be described in detail with reference to FIG. Referring to FIG. 2, four sets of p-channel MOS-FETs 11, 12, 13, 14 and n-channel MOS-FETs 21, 22, 23, 24 form a CMOS output. With the drive current of the p-channel MOS-FET 11 as a reference, the drive current of the p-channel MOS-FET 11 is 2 of the drive current of the p-channel MOS-FET 11.
The driving current of the p-channel MOS-FET 13 is four times that of the p-channel MOS-FET 11 and the driving current of the p-channel MOS-FET 14 is the p-channel MOS.
-Set to 8 times the FETll. Similarly, n-channel MOS-FET22 and n-channel MOS-FET2
3, the driving current of the n-channel MOS-FET 24 is 2 times that of the driving current of the n-channel MOS-FET 21, respectively.
It is set to double, four, and eight times. With this configuration, the output signal line 7 has a drive current of 1
Double, double, quadruple and octuple CMOS output buffers are connected.

An n-channel MOS-FET 31 is connected to the gate input of the p-channel MOS-FET 11 and an n-channel MO-FET 21 is connected to the n-channel MO-FET 21.
The S-FET 41 is connected. Similarly p channel M
OS-FETs 12, 13, 14 and n-channel MOS-
Each of the FETs 22, 23, and 24 has an n-channel MO.
The S-FETs 32, 33, 34 and 42, 43, 44 are connected.

The signals from the input signal circuit 5 are those n-channel MOS-FETs 31, 32, 33, 34 and 4.
1, 42, 43, 44 to the gate of the CMOS output buffer.

The n-channel MOS-FET 31 and n
Channel MOS-FET 41, n-channel MOS-FE
T32, n channel MOS-FET 42, n channel M
OS-FET 33 and n-channel MOS-FET 43, n
Channel MOS-FET 34 and n-channel MOS-FE
The gates of T44 have common control signal lines 61 and 6
2, 63, 64 are connected and receive the same control signal.

Further, p-channel MOS-FETs 11 and 1
The gate inputs of 2, 13, and 14 are connected to the power supply through resistor 8.
The gate inputs of the n-channel MOS-FETs 21, 22, 23 and 24 are connected to the ground through the resistor 9.

Next, the operation of the circuit will be described in detail with reference to FIG. The signals from the input signal circuit 5 are n-channel MOS-FETs 31, 41, 32, 42, 33, 4
Receive at 3, 34, 44. At this time, the control signal line 6
N channel MOS-FE by 1, 62, 63, 64
T31, 41, 32, 42, 33, 43, 34, 44 are short-circuited or cut off, and output MOS-FETs 11, 21,
Control signals to 12, 22, 13, 23, 14, 24.

Here, the output MOS-FETs 11, 21, 1 in which the signal from the n-channel MOS-FET is blocked
2, 22, 13, 23, 14, 24 are output MOS-FETs 11, 21, 12,
Since 22, 13, 23, 14, 24 are cut off, no current is passed through the output signal line 7. Also, an n-channel MO
S-FETs 31, 41, 32, 42, 33, 43, 3
Output MOS-FETs 11 and 2 receiving signals from 4, 44
1, 12, 22, 13, 23, 14, and 24 can output a current corresponding to the signal of the input signal output to the signal line 7.

Output MOS-FETs 11, 21, 12, 2
The drive currents of 2, 13, 23, 14, and 24 are MOS-F.
Since the ETll and ET21 are 2 times, 4 times, and 8 times respectively, the control can be performed with 2 to the 4th power, that is, 16 kinds of drive currents. In the present embodiment, the drive currents of the respective output buffers are set in geometric series so as to be able to meet the continuous demands from the load.
It may be a circuit in which each is set to an arbitrary different value in accordance with the state of the load, and an arbitrary combination thereof is used to supply a desired drive current to the load.

The switch circuit does not need to have the structure described in this embodiment as long as it is a circuit capable of conducting and blocking the input signal to the gate of the output buffer.

[0030]

As described above, the present invention is a simple circuit in which a plurality of CMOS output buffers having different drive currents are connected in parallel and the operation of each CMOS output buffer is controlled by a switch circuit. Since the configuration is employed, the drive current of the output signal can be finely controlled, but the area is small, and the high integration can be achieved. In particular, if the drive currents of a plurality of CMOS output buffers are changed in a ratio of 1: 2: 4: 8 ... Of the geometric series, the CMOS output buffers to be operated corresponding to the required output of the entire circuit. By selecting a combination with the output control circuit, there is an effect that the drive current can be finely changed with a small number of CMOS output buffers.

Further, by controlling the drive current of the CMOS output buffer in a multi-step combination, it becomes possible to control the drive current most suitable for the characteristic impedance of the transmission line, so that the transmission signal waveform is not deformed due to reflection. The effect is also reduced, and high-speed signal transmission becomes possible.

[Brief description of drawings]

FIG. 1 is a CMOS for controlling a drive current according to an embodiment of the present invention.
It is a block diagram which shows the structure of an output buffer circuit.

FIG. 2 is a CMOS for controlling a drive current according to an embodiment of the present invention.
It is a circuit diagram which shows the structure of an output buffer circuit.

[Explanation of symbols]

 3 switch circuit 5 input signal circuit 6 control signal line 7 output signal line 8, 9 resistance 01, 02, 03, 04 CMOS output buffer 11, 12, 13, 14 p-channel MOS-FET 21, 21, 23, 24 n-channel MOS-FET 31, 31, 33, 34 n-channel MOS-FET 41, 41, 43, 44 n-channel MOS-FET 61, 62, 63, 64 Control signal line

Claims (4)

[Claims] 1. A plurality of output buffers including a series connection structure of a pMOS transistor and an nMOS transistor are connected in parallel, and a switch circuit for controlling conduction and interruption of an input current is provided in a preceding stage of all the output buffers. A drive current control CMOS output buffer in which only the output buffer to which the control signal of the switch circuit is transmitted operates to output a drive current, and the overall drive current can be controlled by an arbitrary combination of outputs of the output buffer. circuit. 2. The CMOS output buffer circuit for controlling drive current according to claim 1, wherein the plurality of output buffers are set to output drive currents having different values. 3. The drive current control CMOS output buffer according to claim 2, wherein the different drive current output values set in the plurality of output buffers are set in geometric progression with reference to a reference current value. circuit. 4. The switch circuit corresponding to a set of output buffers has sources connected to respective gates of pMOS transistors and nMOS transistors of the output buffer, and drains connected to an input signal circuit common to all circuits. , Two control nMOS transistors whose gates are commonly connected to a control signal circuit corresponding to the output buffer, resistors for connecting the gates of the pMOS transistors of the output buffers to a power supply circuit, and the output buffers of the output buffers. The drive current controlling CMOS output buffer circuit according to claim 1, comprising a resistor for connecting a gate of the pMOS transistor to a ground circuit.