JPH05191261A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To allow the subject circuit to be compatible with different interfaces by forming an input circuit so that a threshold voltage of the input circuit is revised from an external setting terminal and an internal register or the like and setting a threshold level of the input circuit with an input threshold level setting circuit. CONSTITUTION:Based on a condition set by an input threshold level setting circuit 6, a signal used to control an input threshold level conversion circuit 3 of input threshold level conversion circuits 2a, 2b is generated. That is, the input threshold voltage is set in the unit of two groups of input terminals Ia1-Ian, Ib1-Ibn. After the input threshold voltage of each of input threshold level conversion circuit sections 2a, 2b is set by a control signal from the input threshold level setting circuit 6, an input signal with a different level is applied to two sets of the input terminals Ia1-Ian Ib1Ibn to activate internal circuits 4, 5. Thus, the input threshold level is set in matching with various interface circuits.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a C which can change a threshold voltage of an input terminal.
The present invention relates to a MOS semiconductor integrated circuit.

[0002]

2. Description of the Related Art FIG. 7 shows a conventional semiconductor integrated circuit CM.
Shows OS input circuit (inverter), power supply V _DD and ground G
A P-channel transistor 11 and an N-channel transistor 12 are connected in series between the NDs, their gates are connected to the input terminal 1, and their drains are connected to the output unit 10. Generally, in the CMOS inverter, the threshold voltage of the input terminal 1 is the P-channel transistor 1
Determined by 1 ratio of the gain coefficient beta _N gain coefficient beta _P and N-channel transistor 12. More specifically, in the CMOS inverter, the input threshold voltage is a voltage at which the output voltage transits from a high level to a low level or from a low level to a high level. At this time, the drain current of the P-channel transistor 11 and the N-channel transistor The drain currents of 12 become equal. The drain current I _D of the MOS transistor in the saturation region is

[0003]

[Equation 1]

It is represented by Here, β is the gain coefficient of the transistor, V _G is the gate voltage, and V _T is the threshold voltage of the MOS transistor.

Now, the gain coefficient of the P-channel transistor is β _P , the threshold voltage is V _THP , the gain coefficient of the N-channel transistor is β _N , the threshold voltage is V _THN , the input voltage of the inverter is V _IN , and the output voltage is V _IN . V _OUT , power supply voltage V
_{If DD} , then the following equation holds.

[0006]

[Equation 2]

Therefore, the input threshold voltage (V _TH
= V _IN ),

[0008]

[Equation 3]

[0009] From Equation 3, V_THN= | V_THP｜
Then, the input threshold voltage V of the inverter_THIs Transis
Gain coefficient β_NAnd β_PIs determined by the ratio of_N= Β
_PThen, V_TH= 1 / 2V_DDBecomes That is, the gainer
Number β_NAnd β_PThe input threshold voltage can be changed by changing the ratio of the
Pressure (V _TH) Can be changed.

In other words, in the conventional CMOS semiconductor integrated circuit, the threshold voltage of the input terminal 1 is determined when the transistor size of the input circuit is determined (at the time of layout design). Must be changed.

[0011]

The conventional semiconductor integrated circuit is constructed as described above, and the input threshold voltage of the CMOS input circuit is determined by the ratio of the gain β of the P-channel transistor and the N-channel transistor. In order to change the input threshold voltage, it is necessary to re-design the layout and change the transistor size, which is a problem of poor versatility.

The present invention has been made to solve the above problems, and it is an object of the present invention to obtain a semiconductor integrated circuit in which an input threshold voltage of an input circuit can be arbitrarily set without changing a layout design. To aim.

[0013]

In a semiconductor integrated circuit according to the present invention, the input circuit has an input threshold level setting means capable of setting the input threshold level of the inverter to an arbitrary level, and the input threshold of the inverter is set. The level is set to a predetermined value according to the level of the external input signal applied to the input terminal.

[0014]

According to the present invention, the input threshold level of the inverter forming the input circuit is changed according to the level of the external input signal input to the input terminal of the integrated circuit. Even if the level of the input signal is different, this can be dealt with.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor integrated circuit according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a semiconductor integrated circuit according to an embodiment of the present invention. In FIG. 1, reference numeral 7 denotes an integrated circuit portion, I _{a1 to} I _an and I _b1 to I _b1 .
_Ibm is an input terminal of a CMOS integrated circuit, 2a and 2b are input threshold level conversion circuit sections, which are composed of an input threshold level conversion circuit 3. The input threshold level conversion circuit 3 is, for example, as shown in FIG.
The configuration is as shown in. Reference numerals 4 and 5 are internal circuits, and 6 is an input threshold level setting circuit connected to the input circuits 2 and 3.

Next, the operation will be described. First of all,
Data is written to an external setting terminal (not shown) or an internal register to set the input threshold voltage of the input circuit. Next, in the input threshold level setting circuit 6, based on the set conditions, the respective input threshold level conversion circuit sections 2a, 2b
A signal for controlling the input threshold level conversion circuit 3 is generated. In FIG. 1, the input threshold voltage is set in units of two groups of the input terminals I _{a1 to} I _an and I _{b1 to} I _bm .

After the input threshold voltage of each of the input threshold level conversion circuit portions 2a and 2b is set by the control signal from the input level setting circuit 6, the input terminals _Ia1 ...
Input signals having different levels are applied to the two sets of input terminals I _an and I _{b1 to} I _bm to operate the internal circuits 4 and 5 to operate the integrated circuit.

With the above configuration, the input threshold level can be set according to various interfaces. That is, when the operation level of the CMOS integrated circuit and the level of the external input signal are different,
You can match these levels.

Next, the input threshold level conversion circuit 3 shown in FIG. 2 will be described. Here, 11 and 12 are P-channel transistors and N-channel transistors forming an inverter, 1 is an input terminal, 10 is an output part, 13 is an N-channel transistor for changing the gate width, and its gate has an input terminal 1 and a control terminal. It is connected to the output of an AND circuit having 9 as an input. In this structure, β _N of the N-channel transistor can be changed by changing the gate width W of the N-channel transistor 12 of the inverter according to the signal level applied to the control terminal 9.

Next, the operation of the input threshold level conversion circuit 3 will be described. When the control terminal 9 is Low level,
The N-channel transistor 13 is turned off, and the input circuit 2
The input level of (3) is P channel transistor 11 and N
It is determined by the ratio of the transistor gain coefficient β of the channel transistor 12. On the other hand, when the control terminal 9 is at the high level, the gate of the N-channel transistor 13 is apparently connected to the input terminal 1 via the AND circuit 8. As a result, the gate width W of the N channel transistor 12 of the inverter becomes large, and the gain coefficient β _N of the N channel transistor 12 becomes large. In other words, the input level becomes low and the interface can be used for low voltage input.

As described above, according to this embodiment, the input circuit is provided with the control terminal 9, the AND circuit 8, and the N-channel transistor 13 so that the input threshold level can be converted, and the input terminal is applied to the control terminal 9. The N-channel transistor 13 is controlled according to the level of the output signal of the input threshold level setting circuit 6 to increase the apparent gate width W of the N-channel transistor 13 that constitutes the inverter. The gain coefficient β _N is increased, and the integrated circuit can be operated by connecting to the interface of low voltage input.

Next, a second embodiment of the present invention will be described with reference to FIG. In this embodiment, an input threshold level conversion circuit configured to change the input level of the input circuit by changing the source voltage of the P-channel transistor of the input stage inverter using the internal power supply (operational amplifier). It is composed. In the figure, 20 is an operational amplifier, and 21 is a constant voltage source.

Next, the operation will be described. When an arbitrary constant voltage (reference voltage) is applied to the control terminal 9, the operational amplifier 2
Through 0, the voltage is applied to the source of each P-channel transistor 11 of the input stage inverter. In the CMOS inverter, the input threshold level is the voltage division ratio between the power supply voltage and GND according to the ratio of the gain coefficient β of the P-channel transistor 11 and the N-channel transistor 12,
That is, it is proportional to the power supply voltage. Therefore, by setting the control terminal 9 to an arbitrary voltage, the power supply voltage of the input stage inverter can be set, and as a result, the input threshold level of the input stage inverter can be made variable.

Although the voltage is set from the external setting terminal 9 in FIG. 3, a constant voltage may be generated in the CMOS integrated circuit and switched by the control circuit.

Next, a third embodiment of the present invention will be described with reference to FIG. In this embodiment, in the configuration of the first embodiment, as the input circuits 2 and 3, a voltage drop element is inserted in the source preceding stage of the P-channel transistor 11 of the input stage inverter, and the power supply voltage of the input stage inverter is dropped to input. The input threshold level conversion circuit that changes the threshold level is configured. Reference numerals 14 and 16 denote P connected between the power supply voltage _VDD and the source of the P-channel transistor 11.
It is a channel transistor, 14 is a voltage drop element, and 16 is its switch. Reference numeral 17 is a constant current source for turning on the transistor 16.

Next, the operation will be described. Control terminal 9
When the level is High, the P-channel transistor 16 is off, so that a voltage drop corresponding to the threshold value of the transistor 14 occurs. On the other hand, when the control terminal 9 is at the low level, the transistor 16 is turned on, the conduction of the transistor 14 is short-circuited, and the voltage drop at the source of the P-channel transistor 11 of the inverter disappears. By the above operation, the power supply voltage of the inverter can be lowered, and as a result, the input threshold level of the inverter can be changed.

The P-channel transistor 16 is a switch element for short-circuiting the voltage drop element 14, and an N-channel transistor and a transmission gate can be used instead. FIG. 5 and FIG. 6 are modified examples of the third embodiment and show an example in which the N-channel transistor 15 and the diodes 18 and 19 are used as the voltage drop element, and in this case also, the same effect as the above-mentioned embodiment is obtained. ..

[0028]

As described above, according to the semiconductor integrated circuit of the present invention, the input circuit has the input threshold level setting means capable of setting the input threshold level of the inverter to an arbitrary level, and the above-mentioned inverter is provided. Since the input threshold level of is set to a predetermined value according to the level of the external input signal applied to the input terminal, the input threshold of the integrated circuit can be set arbitrarily according to the interface when in use. Therefore, there is an effect that it is not necessary to change the layout of the circuit itself for changing the input threshold voltage.

[Brief description of drawings]

FIG. 1 is a diagram showing a semiconductor integrated circuit including an input circuit according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of an input circuit including the input threshold level conversion circuit.

FIG. 3 is a configuration diagram of an input circuit including an input threshold level conversion circuit according to a second embodiment of the present invention.

FIG. 4 is a configuration diagram of an input circuit including an input threshold level conversion circuit according to a third embodiment of the present invention.

FIG. 5 is a diagram showing a modification of the input threshold level conversion circuit.

FIG. 6 is a diagram showing a further modified example of the input threshold level conversion circuit.

FIG. 7 is a diagram showing an input circuit of a conventional semiconductor integrated circuit.

[Explanation of symbols]

1 Input Terminal 2 Input Threshold Level Conversion Circuit Section 3 Input Threshold Level Conversion Circuit 4, 5 Internal Circuit 6 Input Threshold Level Setting Circuit 7 Integrated Circuit 8 AND Gate 9 Input Threshold Level Control Terminal or Wiring 10 Input Circuit Output Section 11 P Channel Transistor 12 N-channel transistor 13 N-channel transistor 14 P-channel transistor 15 N-channel transistor 16 P-channel transistor 17 Constant current source 18, 19 Diode 20 Operational amplifier 21 Reference voltage source I _{a1 to} I _an input terminal I _{b1 to} I _bm input terminal

Claims (5)

[Claims] 1. A semiconductor integrated circuit having an input circuit composed of an inverter for receiving and processing an external input signal applied to an input terminal, wherein the input circuit sets the input threshold level of the inverter to an arbitrary level. A possible input threshold level setting means is provided, and the input threshold level of the inverter is set to a predetermined value according to the level of the external input signal applied to the input terminal. Semiconductor integrated circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the input threshold level setting means has an additional transistor connected in parallel to one of the transistors forming the inverter, and turns the transistor on and off. Accordingly, the semiconductor integrated circuit is characterized in that the gain of the one transistor is changed. 3. The semiconductor integrated circuit according to claim 1, wherein the input threshold level setting means includes an internal power supply, a voltage changing transistor connected between the power supply and a power supply side transistor of the inverter, and the internal power supply. A semiconductor integrated circuit, comprising: an operational amplifier driven by a power source to control the gate voltage of the voltage changing transistor, and changing the source voltage of the power source side transistor of the inverter. 4. The semiconductor integrated circuit according to claim 1, wherein the input threshold level setting means short-circuits the voltage drop element connected between the power supply side transistor of the inverter and the power supply, or the voltage drop element. A semiconductor integrated circuit comprising: a short circuit for opening, wherein the source voltage of the transistor is changed by the short circuit or opening. 5. The semiconductor integrated circuit according to claim 1, wherein the input circuit is provided for each of a plurality of internal circuits, and the input threshold level setting means of the input circuit is based on a control signal of a predetermined level. A semiconductor integrated circuit for setting an input threshold level to a predetermined value, wherein the input threshold level setting means of each of the input circuits has signal output means capable of outputting control signals of different levels. circuit.