JP2007158567A - Attenuator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem of a conventional attenuator that noises due to variations in an offset are produced when a switch is changed over. <P>SOLUTION: The attenuator includes: a switch group 20 including a plurality of switches SW1 to SW4 for outputting either of an input signal and a signal with a prescribed level in response to a control signal; a buffer circuit group 30 provided with a plurality of buffer circuits 31 to 34 that receive outputs of the switches SW1 to SW4 and provide outputs each through a resistor with a prescribed output resistance; and a load circuit group 40 comprising series connection of resistance load circuits whose resistance is two kinds substantially equal to or a half the prescribed output resistance and provided with connection points (taps) for receiving the outputs of the buffer circuits. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an attenuator that controls a gain in accordance with a control signal, and more particularly to an attenuator formed as a semiconductor integrated circuit that switches a gain in a stepped manner by a digital control signal.

  In recent devices such as flat TVs, the demand for the image quality of the display screen has become strict as the screen becomes larger. For this reason, these devices perform signal processing such as complicated filter processing for improving image quality after converting an analog video signal into a digital signal in the device.

  Furthermore, in order to reduce the board area used for equipment, a device in which these signal processing functions are housed in a single LSI (Large Scale Integrated circuit) has been put into practical use. Such an LSI has an analog-to-digital converter (hereinafter abbreviated as AD converter) that converts an analog video input signal into a digital signal, and a logic circuit that performs main signal processing. An analog signal processing circuit is provided so as to be within the input range of the AD converter.

  In this analog signal processing circuit, in order to keep the peak potential in the analog video input signal waveform within the input range of the AD converter, a clamp circuit that maintains a DC operating point and an excessive signal amplitude with an appropriate value And an attenuator for attenuating.

  Since the gain of the attenuator needs to be controlled so that the amplitude of the digitized video signal output from the AD converter becomes an appropriate value, the digital control generated by the logic circuit that receives the AD converter output Controlled by signal. Therefore, the attenuator having a digital control signal input is generally used so that the interface with the digital circuit can be easily performed. Patent Document 1 discloses an example of such an attenuator.

  FIG. 9 shows a circuit diagram of the attenuator 100 of Conventional Example 1 disclosed in Patent Document 1. In FIG. As shown in FIG. 9, the attenuator 100 includes an input terminal 101, a control input terminal 102, an output terminal 103, an input buffer 110, a switch group 120, and an R-2R resistance ladder circuit 130.

  The input buffer 110 is composed of a voltage follower composed of an operational amplifier that connects the output and the inverting input V− and applies full feedback. The input signal received at the input terminal 101 is received by the non-inverting input V + and subjected to impedance conversion. Output to the switch group 120.

  The switch group 120 includes four switches SW11 to SW14. The switches SW11 to SW14 have terminals A, B, and C, respectively, and one of the terminals A and B is connected to the terminal C according to the control signals S11 to S14 input from the control input terminal 102. Connected. The terminals A and B of SW11 to SW14 are connected to the output of the input buffer 110 and the ground potential, respectively.

  The R-2R resistor ladder circuit 130 includes resistors R16 to R18 having a resistance value R, and 2R resistors R11 to R15 having a resistance value twice that of R. The resistors R15 to R18 are connected in series between the output terminal 103 and the ground potential. The connection points of the resistors R15 to R18 connected in series and the connection points between the resistor R18 and the output terminal are: Terminals C of the switches SW11 to SW14 are connected through the resistors R11 to R14, respectively.

Next, the operation of the attenuator having the above configuration will be described. A signal input to the input terminal 101 is commonly supplied to the terminals A of the switches SW11 to SW14 via the input buffer 110. The input buffer 110 receives an input signal input from the input terminal 101 with a high input resistance, and drives the R-2R resistance ladder circuit 130 connected via the switch group 120 connected to the output. In this way, the input buffer 110 increases the input resistance of the input terminal 101 by preventing the R-2R resistance ladder circuit 130 and the input terminal 101 of the attenuator from being directly connected.
The switches SW11 to SW14 are connected to the terminal A and the terminal C when the control signals S11 to S14 are at the power supply potential VDD (hereinafter abbreviated as high level), and the output of the input buffer is output to the terminal C. In the case of (hereinafter abbreviated as low level), the terminal B and the terminal C are connected and the ground potential is output to the terminal C. Thereby, each terminal C of the switches SW11 to SW14 outputs a signal input to the input terminal 101 when S11 to S14 are at a high level, but becomes no signal when it is at a low level. The gain in the signal until the signals output from the terminals C of the switches SW11, SW12, SW13, SW14 to the resistors R11, R12, R13, R14 are output to the output terminal 103 is 1/16 [times], respectively. 1/8 [times], 1/4 [times], and 1/2 [times], for example, when only the control signal S11 is at a high level, the input terminal 101 to the output terminal 103 The gain is 1/16 [times], which is the gain until output to the output terminal 103 via the resistor R11. Similarly, the gain when only S12, only S13, and only S14 are at the high level is 1/8 [times], which is the gain until output to the output terminal 103 via the resistors R12, R13, and R14, respectively. / 4 [times] and 1/2 [times].

The gain obtained by any combination of the high level and the low level of the control signals S11 to S14 is obtained by adding all the gains provided by the control signal at the high level. Here, for each of the control signals S11, S12, S13, and S14, if the coefficients that are “1” when the signal level is high and “0” when the signal level is low are W1, W2, W3, and W4, the input The gain G of the attenuator from the terminal 101 to the output terminal 103 can be expressed by equation (1).
G = (8 · W4 + 4 · W3 + 2 · W2 + W1) / 16 [times] (1)
Equation (1) indicates that the gain G of the attenuator is controlled by whether the control signals S11, S12, S13, and S14 are at a high level or a low level. That is, the attenuator 100 can switch the gain from the input terminal 101 to the output terminal 103 according to the control signal given to the control input terminal 102.

  Further, in the first conventional example, the gain is switched by switching a switch provided in a path for supplying a signal to the R-2R resistor ladder circuit. However, the operational amplifier, the input resistor that receives the input signal, and the arithmetic operation are switched. In an inverting amplifier circuit having a feedback resistor for applying negative feedback to the amplifier, a series resistor circuit having taps for the input resistor and the feedback resistor is used, and the tap of the series resistor circuit is selected according to the control signal. The gain is switched by changing the value of the resistor distributed to the input resistor and feedback resistor from the entire series resistor circuit, and as an improved technology, the feedback resistor is a fixed resistor, and the conversion gain is controlled by the control current instead of the input resistor. Patent Document 2 discloses a technique for controlling a gain by varying a control current using a voltage-current conversion circuit composed of a bipolar transistor for controlling the current. It has been disclosed. FIG. 10 shows a circuit diagram of an attenuator 300 of Conventional Example 2 disclosed in Patent Document 2, and FIG. 11 shows a circuit diagram of an attenuator 200 of Conventional Example 3.

  The attenuator 300 shown in FIG. 10 includes an operational amplifier 310 having a non-inverting input connected to the ground potential, and resistors R301 to R306 connected in series between the input terminal IN and the output terminal OUT to form a series resistance circuit. An inverting amplifier circuit. Further, tap switches SW301 to SW305 are connected between the connection points of the resistors R301 to R306 and the inverting input of the operational amplifier 310, respectively.

  The attenuator 300 conducts any one of the tap switches SW301 to SW305 in accordance with the tap switching control, thereby distributing the resistance to the input resistance and the feedback resistance from the entire series resistance circuit in which the resistors R301 to R306 are connected in series. Is changed, the gain of the inverting amplifier circuit determined by the ratio of the input resistance and the feedback resistance is changed, and the gain from the input terminal IN to the output terminal OUT is controlled. For example, when the tap switch SW301 is turned on, the values of the input resistance and the feedback resistance are R301 and R302 + R303 + R304 + R305 + R306, respectively, and the gain of the entire attenuator is − (R302 + R303 + R304 + R305 + R306) / R301 [times]. Also. When the tap switch SW305 is turned on, the values of the input resistance and the feedback resistance are R301 + R302 + R303 + R304 + R305 and R306, respectively, and the gain of the entire attenuator is −R306 / (R301 + R302 + R303 + R304 + R305) [times]. Thus, the attenuator 300 can switch the gain according to the tap switching control.

  The attenuator 200 of the prior art 3 which is an improved technique of the prior art 2 includes a voltage / current conversion circuit 201 that converts an input signal received via the input terminal IN into a current and outputs the current, and a non-inverting input V + that is grounded and inverted. An operational amplifier 210 that receives the output current of the voltage-current conversion circuit 201 at the input V− and outputs the output current to the output terminal OUT, and a feedback resistor ROUT connected between the output of the operational amplifier 210 and the inverting input V− are provided. The gain of the attenuator 200 is controlled by controlling the conversion gain of the circuit 201. Control of the gain of the attenuator 200 will be described.

The voltage-current conversion circuit 201 includes an input resistor RIN, bipolar transistors Q1, Q2, active loads Q5, Q6, a first differential amplifier having a current source IA, bipolar transistors Q3, Q4, active loads Q7, Q8, and current. A second differential amplifier having a source IB. The base and collector of the bipolar transistor Q1 and the base of the bipolar transistor Q4 are connected to the input terminal IN via the input resistor RIN, and the collector of the bipolar transistor Q4 is connected to the output of the voltage-current conversion circuit 201. The conversion gain of the voltage / current conversion circuit 201 is IB / IA, which is the ratio of the output currents of the current sources IA and IB included in the voltage / current conversion circuit 201, respectively, IA and IB. The output current IOUT of the voltage-current conversion circuit is expressed by the following equation (2) obtained by multiplying the current IIN flowing through the input resistor RIN by this conversion gain (IB / IA).
IOUT = IIN × (IB / IA) (2)

The output voltage VOUT of the attenuator becomes VOUT = ROUT × IOUT using the feedback resistor ROUT and the output current IOUT of the voltage-current conversion circuit 201, and the input voltage VIN of the attenuator is the input resistance RIN of the voltage-current conversion circuit 201. And using the fact that VIN = RIN × IIN using the input current IIN flowing through the input resistor RIN, and using the equation (2), the gain G2 = VOUT / VIN of the attenuator 200 is given by the equation (3) Can be represented by
G2 = (ROUT / RIN) × (IB / IA) (3)
From equation (3), the attenuator 200 of Conventional Example 3 can change the gain according to the output currents of the current sources IA and IB.

Note that the active loads Q5 and Q6 of the first differential amplifier of the voltage-current converter circuit 201 supply a current equal to the collector current of the bipolar transistor Q2 to the collector of Q1, so that a part of the output current of the current source IA. Prevents the occurrence of an input DC offset voltage due to a steady flow to the input terminal via the input resistor RIN. The active loads Q7 and Q8 of the second differential amplifier supply a current equal to the collector current of the bipolar transistor Q3 to the collector of Q4, so that a part of the output current of the current source IB is converted into the voltage-current conversion circuit 201. The output DC offset current is prevented from being generated due to the steady flow of the output.
Japanese Patent Laid-Open No. 5-95239 Japanese Utility Model Publication No. 5-46113

  However, in the attenuator 100 of the prior art example 1, in order to obtain a high input resistance, the input buffer 110 composed of an operational amplifier in which a total feedback is applied to the previous stage of the switch group for switching the gain is provided. In the case of having an input DC offset voltage, the gain switching is performed on the input signal on which the input DC offset is superimposed, so that an offset voltage that varies with the gain switching is generated at the output terminal. .

  Also in the attenuator 300 of the conventional example 2, since the operational amplifier 310 is used in the inverting amplifier circuit, when the operational amplifier 310 has an input DC offset voltage, the offset voltage is equivalent to the gain of the attenuator 300. Since the signal is amplified and output, an offset voltage that fluctuates with the gain switching is generated at the output terminal.

  Further, in the attenuator 300 of the conventional example 2 and the attenuator 200 of the conventional example 3, in each of the voltage-current conversion circuit 201, between the bipolar transistors Q1 and Q2 forming the first differential amplifier and active When the characteristics do not completely match between the loads Q5 and Q6, a part of the output current of the current source IA constantly flows to the input terminal via the input resistor RIN, thereby generating an input DC offset voltage. When the gain is changed by changing the output current of the current source IB of the second differential amplifier, the DC offset voltage that varies according to the change in gain is applied to the output terminal. Is output. Further, when the characteristics do not completely match between the bipolar transistors Q3 and Q4 forming the second differential amplifier and between the active loads Q7 and Q8, a part of the output current of the current source IB is An output DC offset current is generated due to a steady flow at the output of the voltage-current conversion circuit 201, and the output DC offset current fluctuates according to a change in the current source IB for changing the gain. When the gain is changed by changing the output current of the current source IB of the differential amplifier 2, a DC offset voltage that varies according to the change in gain is output to the output terminal.

  In the attenuators of Conventional Example 1, Conventional Example 2, and Conventional Example 3, a DC offset voltage that fluctuates according to gain switching or control is output, so that the gain is stepped with a digital control signal. However, there is a problem that step-like noise is generated at the output terminal.

  In the attenuator 300 of the conventional example 2 and the attenuator 300 of the conventional example 3, since the input resistance is directly connected to the input terminal IN, it is inevitable that a current flows to the input terminal, and therefore, the high It is difficult to obtain input resistance. As in Conventional Example 1, it is possible to increase the input resistance by adding an input buffer, but in this case, the added input buffer further adds a DC offset voltage to the input signal. There is a problem that the fluctuation of the offset voltage that fluctuates with the switching of the gain becomes larger, and the fluctuation of the DC offset voltage generated at the output terminal and the noise caused thereby become larger.

  An attenuator according to the present invention includes a switch group having a plurality of switches that output either one of an input signal and a predetermined potential according to a control signal, and a plurality of outputs that receive an output of the switch and output at a predetermined output resistance value. The output of the buffer circuit is received in a series circuit composed of a buffer circuit group including a plurality of buffer circuits and two types of load circuits having resistance values substantially equal to or half the predetermined output resistance value. And a load circuit group provided with a connection point (tap) of the load circuit.

  According to the attenuator of the present invention, the buffer circuit is provided in the subsequent stage of the switch group, and there is no device for switching the gain in the path from the output of the buffer circuit to the output terminal. Therefore, in the conventional attenuator, noise is generated due to the potential fluctuation caused by switching the offset voltage of the input buffer provided in the previous stage of the switch group by the switch, whereas the attenuator of the present invention switches the switch. Even in such a case, no noise caused by potential fluctuations is generated at the output terminal.

  According to the attenuator of the present invention, when the gain is changed, the fluctuation of the output DC offset voltage and the generation of noise caused by the fluctuation can be eliminated.

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a circuit diagram of an attenuator 1 according to the first embodiment.

  The attenuator 1 includes an input terminal 10, a control input terminal 11, a switch group 20, a buffer circuit group 30, and a load circuit group 40. An input signal having a predetermined amplitude is input to the input terminal 10. Control signals S1 to S4 for controlling the state of the switch group 20 are input to the control input terminal 11. The output terminal 12 is an output terminal of the present embodiment, and amplifies an input signal with a gain corresponding to the control signal and outputs the amplified signal.

  The switch group 20 includes switches SW1 to SW4 having terminals A, B, and C. The switches SW1 to SW4 select one of the signals input to the terminal A or the terminal B and output the selected signal to the terminal C according to the control signals S1 to S4, respectively. In the present embodiment, an input signal is input to the terminal A via the input terminal 10, and the terminal B is connected to a predetermined potential (ground potential). The switch selects the terminal A when the control signal is at a high level, and selects the terminal B when the control signal is at a low level to output either an input signal or a predetermined potential. A detailed circuit of the switch will be described later.

  The buffer circuit group 30 includes a plurality of buffer circuits 31 to 34 that output the output signals from the switches SW1 to SW4 with a predetermined output resistance. In the present embodiment, the buffer circuits 31 to 34 have differential transconductance amplifiers OTA1 to OTA4. The differential transconductance amplifiers OTA1 to OTA4 have an inverting input terminal I-, a non-inverting input terminal I +, an inverting output terminal O-, and a non-inverting input terminal O +. The non-inverting input terminal I + is a buffer circuit 31-34. The inverting output terminal O− is connected to a first potential (for example, ground potential) which is a predetermined potential, and the non-inverting output terminal O + is connected to each inverting input terminal I− to apply negative feedback. At the same time, it is taken out as the output of the buffer circuits 31-34. In addition, the connection type of each terminal of the differential transconductance amplifiers OTA1 to OTA4 as described above is hereinafter abbreviated as the first connection type for the sake of simplicity. Inputs of the buffer circuits 31 to 34 are respectively connected to terminals C of the corresponding switches SW1 to SW4, and outputs of the buffer circuits 31 to 34 are output to the load circuit group 40. Details of the circuits of the differential transconductance amplifiers OTA1 to OTA4 will be described later.

  The load circuit group 40 includes a first load circuit having a resistance value substantially half of a predetermined output resistance of the buffer circuits 31 to 34 and a first load circuit having a resistance value substantially the same as the output resistance of the buffer circuit. 2 load circuits. In the present embodiment, load circuits 42 to 44 are used as the first load circuit, and load circuit 41 is used as the second load circuit. Each of the load circuits 41 to 44 uses, as a load, OTA that is negatively feedback-connected. The load circuits 41 to 44 are connected in series between the output terminal 12 and the ground potential. The output of the corresponding buffer circuit is connected to each connection point of the load circuits connected in series. In the present embodiment, load circuits 41 to 44 are connected in cascade from the ground potential to the output terminal 12, and buffer circuits are connected to other connection points except for the connection point between the ground potential and the load circuit 41. Outputs 31 to 34 are connected.

  In the present embodiment, the load circuit 41 includes the differential transconductance amplifier OTA5, the load circuit 42 includes the differential transconductance amplifiers OTA6 and 7, the load circuit 43 includes the differential transconductance amplifiers OTA8 and 9 and the load circuit 43. The circuit 44 includes differential type transconductance amplifiers 10 and 11, respectively. Two differential type transconductance amplifiers respectively included in the load circuits 42 to 44 are connected in parallel. The differential transconductance amplifiers OTA5 to OTA11 are connected to the non-inverting input terminal I + and the inverting output terminal O−, and are connected to the inverting input terminal I− and the non-inverting output terminal O +. Note that the connection type of each terminal of the differential transconductance amplifiers OTA5 to OTA11 as described above is hereinafter abbreviated as the second connection type for the sake of simplicity.

  In the two differential transconductance amplifiers included in the load circuits 42 to 44, the two non-inverting input terminals I + are connected together with the two inverting output terminals O− to be input to the load circuit. It is connected together with the inverting input terminal I− and the two non-inverting output terminals O + to become an output of the load circuit. The inputs of the load circuits 44, 43, 42 are connected to the outputs of the load circuits 43, 42, 41, respectively.

  In the differential transconductance amplifier included in the load circuit 41, the non-inverting input terminal I + is connected together with the inverting output terminal O− to be an input of the load circuit, and the inverting input terminal I− is connected together with the non-inverting output terminal O +. And becomes the output of the load circuit. The input of the load circuit 41 is connected to the ground potential, and the output is connected to the input of the load circuit 42.

  Here, the circuit of the switch will be described in detail. A circuit diagram of the switch is shown in FIG. As shown in FIG. 2, the switch includes terminals A, B, and C, a control signal input terminal S, inverters INV1 and INV2, and transfer gates TG1 and TG2.

  The inverter INV1 includes an NMOS transistor M15 and a PMOS transistor M16 connected in series between a second potential (for example, the power supply potential VDD) and the ground potential VSS. The gate of the NMOS transistor M15 and the gate of the PMOS transistor M16 are connected to each other and output a signal obtained by inverting the control signal input from the control signal input terminal S. The INV2 includes an NMOS transistor M17 and a PMOS transistor M18 connected in series between the power supply potential VDD and the ground potential VSS. The gate of the NMOS transistor M17 and the gate of the PMOS transistor M18 are connected to each other and output a signal obtained by inverting the signal input from INV1.

  The transfer gate TG1 includes an NMOS transistor M11 and a PMOS transistor M12. The source of the NMOS transistor M11 and the drain of the PMOS transistor M12 are connected to the terminal A. The drain of the NMOS transistor M11 and the source of the PMOS transistor M12 are connected to each other. Is connected to terminal C. The gate of the NMOS transistor M11 is connected to the output of the inverter INV2, and the gate of the PMOS transistor M12 is connected to the output of the inverter INV1. With such connection, the transfer gate TG1 becomes non-conductive when the control signal is at a low level, and becomes conductive when the control signal is at a high level.

  The transfer gate TG2 includes an NMOS transistor M13 and a PMOS transistor M14. The source of the NMOS transistor M13 and the drain of the PMOS transistor M14 are connected to the terminal B. The drain of the NMOS transistor M13 and the source of the PMOS transistor M14 Is connected to terminal C. The gate of the NMOS transistor M13 is connected to the output of the inverter INV1, and the gate of the PMOS transistor M14 is connected to the output of the inverter INV2. With such a connection, the transfer gate TG2 becomes conductive when the control signal is at a low level, and becomes non-conductive when it is at a high level.

  From the above description, the switch outputs the signal at the terminal B to the terminal C when the control signal is at the low level, and outputs the signal at the terminal A to the terminal C when the control signal is at the high level.

  Next, an internal circuit of the differential transconductance amplifiers OTA1 to OTA11 will be described in detail. An internal circuit of the differential transconductance amplifiers OTA1 to OTA11 is shown in FIG. As shown in FIG. 3, the differential transconductance amplifier 50 includes PMOS transistors 51 and 52 and current sources 53 to 55. The sources of the PMOS transistors 51 and 52 are commonly connected to form a differential pair. A non-inverting input terminal I + is connected to the gate of the PMOS transistor 51, and a first current source (current source 53) is connected between the drain and the ground potential VSS. An inversion output terminal O− is connected to a connection point between the current source 53 and the drain of the PMOS transistor 51. An inverting input terminal I− is connected to the gate of the PMOS transistor 52, and a second current source (current source 54) is connected between the drain and the ground potential VSS. A connection point between the current source 54 and the drain of the PMOS transistor 52 is connected to a non-inverting output terminal O +. A current source 55 is connected between the connection point of the sources of the PMOS transistors 51 and 52 and the power supply potential VDD. Here, if the currents output from the current sources 53 to 55 are I53 to I55, the currents have a relationship of I55 / 2 = I53 = I54.

  Next, the operation of the differential transconductance amplifier 50 will be described. In the differential transconductance amplifier 50, when the voltage difference between the voltage at the non-inverting input terminal I + and the voltage at the non-inverting input terminal I + is expressed as “vin”, the PMOS transistors 51 and 52 are configured by the PMOS transistors 51 and 52. A drain current proportional to the transconductance gm of the moving pair is passed. The transconductance gm is the reciprocal of the sum of the source resistances of the PMOS transistors 51 and 52. The drain current (for example, the first drain current) of the PMOS transistor 51 is (I55 / 2−gm · vin), and the drain current (for example, the second drain current) of the PMOS transistor 52 is (I55 / 2 + gm · vin). The differential transconductance amplifier 50 outputs a current of (I55 / 2−gm · vin) −I53 = −gm · vin from the inverting output terminal O− based on the difference between the drain current and the currents I53 and I54. Then, a current satisfying (I55 / 2 + gm · vin) −I54 = gm · vin is output from the non-inverting output terminal O +. Here, the polarity of the current is positive in the direction of flowing out from each terminal.

  Accordingly, when the differential transconductance amplifier 50 is used in a negative feedback connection buffer circuit in which the inverting output terminal O− is connected to the ground potential and the non-inverting output terminal O + and the inverting input terminal I− are connected. It can be seen that the buffer circuit is an element that outputs a current of gm · vin when the difference voltage between the input voltage and the output voltage is vin. That is, the buffer circuit can be regarded as an element having an output resistance of 1 / gm from the relationship between the potential difference between the input terminal and the output terminal and the current flowing with respect to the potential difference. Here, since the input terminal of the OTA 50 serves as the gate of the PMOS transistor, no current flows from the input terminal. That is, each of the buffer circuits 31 to 34 has an infinite input resistance, the output voltage of the voltage follower in which the input voltage is 1 × the voltage gain and the output resistance is 0Ω, and the output resistance is 1 / gm. Can be equivalently expressed as a circuit connected in series.

  Further, the differential transconductance amplifier 50 is used in a negative feedback connection load circuit in which the inverting output terminal O− and the non-inverting input terminal I + are connected and the non-inverting output terminal O + and the inverting input terminal I− are connected. In this case, when the difference voltage between the input voltage and the output voltage is vin, the load circuit receives a current of gm · vin from the non-inverting output terminal O + and becomes gm · vin from the inverting output terminal O−. It can be seen that this is an element from which current flows out. That is, the load circuit can be regarded as a resistance element having a resistance value of 1 / gm from the relationship between the potential difference between the input terminal and the output terminal and the current flowing with respect to the potential difference. From the above, the load circuit 41 can be equivalently expressed as a resistor having a resistance value of 1 / gm. The load circuits 42 to 44 include two differential transconductance amplifiers 50 that connect the inverting output terminal O− and the non-inverting input terminal I + and connect the non-inverting output terminal O + and the inverting input terminal I−. Since they are connected in parallel, they can be equivalently expressed as two resistors having a resistance value of 1 / gm in parallel, and the resistance value is 1 / (2 · gm).

  Here, FIG. 4 shows a circuit diagram in which the buffer circuits 31 to 34 and the load circuits 41 to 44 of the attenuator 1 shown in FIG. 1 are replaced with equivalent circuits. As shown in FIG. 4, the buffer circuits 31 to 34 are expressed as circuits in which voltage followers VF1 to VF4 and resistors R1 to R4 having a resistance value of 2R are connected in series, respectively. The load circuit 41 can be represented as a resistor having a resistance value of 2R, and the load circuits 42 to 44 can be represented by resistors R6 to R8 having a resistance value of R, respectively. Here, in order to simplify the description, the resistance value 1 / (2.gm) is replaced with the resistance value R. From the circuit diagram shown in FIG. 4, it can be seen that the attenuator of the present embodiment is an R-2R resistor ladder circuit. Furthermore, the attenuator of this embodiment has no input buffer between the input terminal 10 and the switch group 20, and a voltage follower serving as an input buffer is connected to a terminal C serving as an output terminal of the switches SW1 to SW4.

  Next, the operation of the attenuator 1 according to the first embodiment will be described. The attenuator 1 controls the switches SW1 to SW4 of the switch group 20 based on the control signals S1 to S4 input from the control input terminal 11, respectively. As a result, the combination of the buffer circuits 31 to 34 and the load circuits 41 to 44 connected to the switch group 20 is changed, and an output signal having a predetermined gain with respect to the input signal is output from the output terminal.

  The gains from the input of the buffer circuits 31 to 34 to the output terminal 12 are 1/16 [times], 1/8 [times], 1/4 [times], and 1/2 [times], respectively. When only S1 is at a high level, the gain from the input terminal 10 to the output terminal 12 is 1/16 [times] that is a gain obtained by a path passing through the switch SW1 and the buffer circuit 31. Similarly, the gains when only S2, only S3, and only S4 are at the high level are 1/8 [times] and 1/4 [times], respectively, which are gains when inputs are provided via the buffer circuits 32-34, respectively. ], [1/2] times.

The gain obtained by any combination of the high level and the low level of the control signals S1 to S4 is the sum of all the gains provided by the control signal at the high level. Here, for each of the control signals S1, S2, S3, and S4, if the coefficients that are “1” when the signal is high and “0” when the signal is low are W1, W2, W3, and W4, The gain G of the attenuator from the input terminal 10 to the output terminal 12 can be expressed by equation (4).
G = (8 · W4 + 4 · W3 + 2 · W2 + W1) / 16 [times] (4)
From the equation (4), it can be seen that the attenuator 1 can switch the gain from the input terminal 10 to the output terminal 12 in accordance with the control signal applied to the control input terminal 11.

  From the above description, the attenuator 1 according to the first embodiment has a resistance value of 1 / gm and a resistance value of 1 / (1) due to the buffer circuit group 30 and the load circuit group 40 using the differential transconductance amplifier. 2 · gm), and an output signal having a predetermined gain with respect to the input signal is generated by the R-2R resistance ladder method. The buffer circuits 31 to 34 have an infinite input resistance, a voltage gain of 1 and a resistance value connected in series to the output of the voltage follower and an output resistance of 0Ω. It can be expressed by an equivalent circuit as a resistance of gm. As a result, the buffer circuit group 30 can have a high input resistance at the subsequent stage of the switch group 20, and the switch group 20 can be directly connected to the input terminal without providing an input buffer between the input terminal 10 and the switch group 20. 10 can be connected.

  Further, in the conventional attenuator, a circuit block that generates a DC offset voltage such as an operational amplifier is disposed in the previous stage of the circuit that performs gain switching, and this DC offset voltage is input to the circuit that performs gain switching. Noise was generated when switching the gain. On the other hand, in the attenuator 1 according to the first embodiment, the input of the switch group 20 for switching the gain can be directly connected to the input terminal 10, so that the DC offset voltage is generated between the input terminal 10 and the switch group 20. Since the DC offset voltage that does not exist between them and causes noise is not applied to the switch group 20, it is possible to eliminate the generation of noise when performing gain switching.

  In the attenuator 1 according to the present invention, the buffer circuits 31 to 34 and the load circuits 41 to 44 are configured using differential transconductance amplifiers having the same configuration. Therefore, resistance values generated by the differential transconductance amplifiers having the same configuration can be well aligned, so that a relatively high resistance ratio can be realized.

  Therefore, a highly accurate resistance element is not required for the circuit. That is, since it is not necessary to form a high-precision resistance element on the semiconductor substrate in the manufacturing process, the process for forming the resistor can be omitted, and the manufacturing process can be simplified.

Embodiment 2
The attenuator 1 according to the first embodiment has an R-2R resistance ladder system that includes a buffer circuit having an output resistance having a resistance value of 1 / gm and a load circuit having a resistance value of 1 / gm or 1 / (2.gm). A circuit is realized. On the other hand, the attenuator 2 according to the second embodiment realizes an R-2R resistance ladder type circuit by using a buffer circuit having an output resistance having a resistance value of 2 / gm and a resistance having a resistance value of 1 / gm. Is. FIG. 5 shows an attenuator 2 according to the second embodiment. The same blocks as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  As shown in FIG. 5, in the attenuator 2 according to the second embodiment, the buffer circuit group 30 and the load circuit group 40 of the attenuator 1 according to the first embodiment are replaced with a buffer circuit group 30 ′ and a load circuit group 40 ′. Is.

  The buffer circuit group 30 ′ is obtained by sequentially replacing the buffer circuits 31 to 34 included in the buffer circuit group 30 of the attenuator 1 according to the first embodiment with buffer circuits 31 ′ to 34 ′. Each of the buffer circuits 31 ′ to 34 ′ has a first connection in which the inverting output terminal O− is connected to a first potential (for example, ground potential), and the inverting input terminal I− and the non-inverting output terminal O + are connected. A differential transconductance amplifier (for example, OTA12 to 15) connected to each terminal in a form, an inverting output terminal O- and a non-inverting input terminal I + are connected, and a non-inverting output terminal O + and an inverting input terminal I- And a differential transconductance amplifier (for example, OTA16 to 19) connected to each terminal in a second connection type. Here, in the OTAs 12 to 15, the non-inverting input terminal I + is connected to the terminal C of the corresponding switch of the switch group 20, and the non-inverting output terminal O + is an output. The non-inverting input terminals I + of the differential transconductance amplifiers OTA16 to 19 are connected to the non-inverting output terminals O + of the differential transconductance amplifiers OTA12 to OTA15, respectively. The output terminals are output to the load circuit group 40 ′ as outputs of the buffers 31 ′ to 34 ′, respectively.

  Due to the connection of the differential transconductance amplifiers in the buffer circuits 31 ′ to 34 ′, the buffer circuits 31 ′ to 34 ′ each have an infinite input resistance, a voltage gain of 1 and an output resistance of 0Ω. An equivalent circuit having a voltage follower having a resistance value of 1 / gm connected in series to the output of the voltage follower, and a resistor having a resistance value of 1 / gm connected in series to the output resistance. Can be represented. That is, each of the buffer circuits 31 ′ to 34 ′ has an infinite input resistance, a voltage gain of 1 time, and a resistance value connected in series to the output of the voltage follower with an output resistance of 0Ω. Can be represented by an equivalent circuit having an output resistance of 2 / gm. This is the same as the equivalent circuit of the buffer circuits 31 to 34 in the first embodiment in which the value 1 / gm of the output resistance is replaced with 2 / gm which is a value of 2 [times].

  The load circuit group 40 ′ is obtained by sequentially replacing the load circuits 41 to 44 included in the load circuit group 40 of the attenuator 1 according to the first embodiment with load circuits 41 ′ to 44 ′.

  The load circuit 41 ′ is connected to each other terminal in the second connection form in which the inverting output terminal O− and the non-inverting input terminal I + are connected, and the non-inverting output terminal O + and the inverting input terminal I− are connected. Differential transconductance amplifiers OTA20 and 21 are connected in series. From this, the load circuit 41 ′ can be expressed by an equivalent circuit as a resistor having a resistance value of 2 / gm. This is the same as replacing 1 / gm, which is the resistance value of the equivalent circuit of the load circuit 41 in Embodiment 1, with 2 / gm, which is a value of 2 [times].

  Each of the load circuits 42 'to 44' has a second connection form in which the inverting output terminal O- and the non-inverting input terminal I + are connected, and the non-inverting output terminal O + and the inverting input terminal I- are connected to each terminal. Therefore, the load circuits 42 ′ to 44 ′ are represented by equivalent circuits as resistors having a resistance value of 1 / gm. be able to. This is the same as replacing 1 / (2 · gm), which is the resistance value of the equivalent circuit of the load circuits 42 to 44 in the first embodiment, with 1 / gm, which is twice that value.

  From the above description, the attenuator 2 in the second embodiment is equivalent to the resistance values R (= 1 / (2 · gm)) and 2R in the equivalent circuit of the attenuator 1 of the first embodiment shown in FIG. (= 1 / gm) is simply changed to 2R and 4R, respectively, and the resistor connection is maintained in the same R-2R resistance ladder circuit form as the attenuator 1 of the first embodiment. From this, the attenuator 2 according to the second embodiment operates as an R-2R resistance ladder type attenuator in the same manner as the attenuator 1 according to the first embodiment, and the gain G thereof is the attenuator according to the first embodiment. Similar to 1, G = (8 · W4 + 4 · W3 + 2 · W2 + W1) / 16 [times].

  On the other hand, the attenuator 1 according to the first embodiment and the attenuator 2 according to the second embodiment are different from each other in the connection between the differential transconductance amplifiers used in the buffer circuit and the load circuit. The amplitude of the signal applied between the non-inverting input terminal I + and the inverting input terminal I− of the dynamic transconductance amplifier can be made smaller than that used in the first embodiment. Thereby, the maximum value of the input signal amplitude that can be received at the input terminal of the attenuator can be expanded to 2 [times] that of the attenuator according to the first embodiment. Details will be described below.

  FIG. 6 shows the amplitude of a signal input between the non-inverting input terminal I + and the inverting input terminal I− of each differential transconductance amplifier in the attenuator 1 according to the first embodiment. The numerical values shown in FIG. 6 indicate the magnitude of the amplitude of the signal input between the non-inverting input terminal I + and the inverting input terminal I− of each differential transconductance amplifier when the amplitude of the input signal is 1. It is. Further, since the amplitude varies depending on the states of the control signals S1 to S4, the signal states are also shown in FIG. 6 that the maximum amplitude of the signal input between the input terminals of the differential transconductance amplifier of the attenuator 1 according to the first embodiment is 170/256 [times] that of the input signal.

  FIG. 7 shows the amplitude of a signal input between the non-inverting input terminal I + and the inverting input terminal I− of each differential transconductance amplifier in the attenuator 2 according to the second embodiment. The numerical values shown in FIG. 7 are input between the non-inverting input terminal I + and the inverting input terminal I− of each differential transconductance amplifier when the amplitude of the input signal is 256, as in FIG. Is the magnitude of the amplitude of the signal to be transmitted. Further, since the amplitude varies depending on the states of the control signals S1 to S4, the signal states are shown in FIG. 7 as in FIG. 7 that the maximum amplitude of the signal input between the input terminals of the differential transconductance amplifier of the attenuator 1 according to the first embodiment is 85/256 [times] that of the input signal.

  From the above description, when the differential type transconductance amplifier having the same input signal voltage range (input range) is used in the first embodiment and the second embodiment, the attenuator 1 of the first embodiment has an allowable input. Whereas the signal voltage range is 256/170 [times] the input signal voltage range of the differential transconductance amplifier, the attenuator 2 of the second embodiment has an input of the differential transconductance amplifier. It is 256/85 [times] with respect to the range of the signal voltage. That is, the attenuator 2 of the second embodiment receives an input signal voltage of (256/85) ÷ (256/170) = 2 [times] at the input terminal 10 as compared with the attenuator 1 of the first embodiment. Is possible.

Embodiment 3
FIG. 8 shows a circuit diagram of the differential transconductance amplifier 60 according to the third exemplary embodiment. The attenuator according to the third embodiment is obtained by replacing the differential transconductance amplifier 50 shown in FIG. 3 used in the attenuator 1 according to the first embodiment with a differential transconductance amplifier 60 shown in FIG. . Therefore, here, the circuit of the differential transconductance amplifier 60 will be described in detail, and the description of the attenuator will be omitted.

  As shown in FIG. 8, the differential transconductance amplifier 60 according to the third embodiment includes PMOS transistors 61 and 62, an impedance element 63, current sources 64 to 67, a non-inverting input terminal I +, an inverting input terminal I−, It has a non-inverting output terminal O + and an inverting output terminal O-. The PMOS transistors 61 and 62 constitute a differential pair, and the sources of the PMOS transistors 61 and 62 are connected via the impedance element 63. The impedance element 63 includes PMOS transistors 63a and 63b in the present embodiment. The PMOS transistor 63 a has a source connected to the source of the PMOS transistor 62 and a drain connected to the source of the PMOS transistor 61. The PMOS transistor 63 b has a source connected to the source of the PMOS transistor 61 and a drain connected to the source of the PMOS transistor 62. A current source 66 is connected between the source of the PMOS transistor 61 and the power supply potential VDD, and a current source 67 is connected between the source of the PMOS transistor 62 and the power supply potential VDD. Further, a first current source (for example, a current source 64) is connected between the drain of the PMOS transistor 61 and the ground potential VSS, and a second current is connected between the drain of the PMOS transistor 62 and the ground potential VSS. A source (eg, current source 65) is connected.

  The non-inverting input terminal I + is connected to the gates of the PMOS transistor 61 and the PMOS transistor 63b, respectively. The inverting input terminal I- is connected to the gates of the PMOS transistor 62 and the PMOS transistor 63a. The inverting output terminal O− is connected to the connection point between the drain of the PMOS transistor 61 and the current source 64, and the non-inverting output terminal O + is connected to the connection point between the PMOS transistor 62 and the current source 65. Here, the current sources 64 to 67 are circuits that output the current I having the same current value.

  Next, the operation will be described. The input signal voltage vin at the non-inverting input terminal with respect to the inverting input terminal I− of the differential transconductance amplifier 60 is applied between the gates of the PMOS transistors 61 and 62. The input signal voltage applied between the gates of the PMOS transistors 61 and 62 is applied to a series resistance circuit composed of the source resistance of the PMOS transistor 61, the impedance element 63, and the source resistance of the PMOS transistor 62, and the resistance of the series resistance circuit. It is converted into a current that is inversely proportional to the value. When the reciprocal of the resistance value of the series resistor circuit is gm, the value of the current converted from the input signal voltage is gm · vin. The currents flowing through the drains of the PMOS transistors 61 and 62 (for example, the first drain current and the second drain current) are a current converted from the input signal voltage and a current source connected to the sources of the PMOS transistors 61 and 62. 66 and 67 are added to each other, so that I-gm · vin and I + gm · vin respectively, and in addition to the output currents of the current sources 64 and 65, respectively, the inverted output terminal O− It is output to the non-inverting output terminal O +. Here, the output currents of the current sources 64 and 65 are added so as to cancel the output currents I of the current sources 66 and 67 included in the drain currents I−gm × vin and I + gm × vin of the PMOS transistors 61 and 62, respectively. Therefore, the output currents of the inverting output terminal O− and the non-inverting output terminal O + are the currents −gm · vin and gm · vin obtained by converting the input voltage, respectively. That is, the differential transconductance amplifier 60 receives the input signal voltage vin received between the non-inverting input terminal I + and the inverting input terminal I−, the source resistances of the built-in PMOS transistors 61 and 62, and the built-in impedance element 63. The current is converted to a current proportional to the transconductance gm determined by the reciprocal of the sum of the resistances, and converted from the non-inverting output terminal O + and the inverting output terminal O− to currents having values of gm · vin and −gm · vin. To do.

  On the other hand, in the attenuator according to the third embodiment, the range of the input signal voltage of the attenuator can be expanded as compared with the first embodiment, and will be described in detail below.

  Since the sum of the source resistances of the PMOS transistors 51 and 52 that form a differential pair in the differential transconductance amplifier 50 according to the first embodiment changes depending on the input signal voltage, the transconductance that is the reciprocal thereof is also the input signal. Varies depending on the voltage. For this reason, in the first embodiment in which the differential transconductance amplifier 50 is used for the attenuator 1, the resistance value of the R-2R resistance ladder circuit configured equivalently using the differential transconductance amplifier 50 is input. Since it changes depending on the signal voltage, the output signal voltage of the attenuator 1 includes a distortion component. For this reason, the range of the input signal voltage allowable in the first embodiment is limited to a range in which the amount of the distortion component included in the output signal voltage is allowable. On the other hand, the transconductance of the differential transconductance amplifier 60 in the third embodiment is added to the PMOS transistors 61 and 62 forming a differential pair similar to the differential pair of the differential transconductance amplifier 50 in the first embodiment. In addition, since the impedance element 63 is connected between the sources of the PMOS transistors 61 and 62, the transconductance is obtained by adding the resistance of the impedance element 63 to the sum of the source resistances of the PMOS transistors 61 and 62. It is the reciprocal. Here, with respect to the change in the input signal voltage, the sum of the source resistances of the PMOS transistors 61 and 62 changes to the minimum when the input signal voltage is 0 and increases as the absolute value of the input signal voltage increases. On the other hand, the resistance of the impedance element 63 is set so as to be maximum when the input signal voltage is 0 and to decrease as the absolute value of the input signal voltage increases. Can be reduced compared to the differential transconductance amplifier 50 without the impedance element 63. Thus, when the same input signal voltage is received, the third embodiment using the differential transconductance amplifier 60 has an amount of distortion component included in the output signal voltage as compared with the first embodiment. When the amount of distortion component included in the output signal voltage may be the same as that in the first embodiment, the range of the input signal voltage can be further expanded.

  In the above, the attenuator according to the third embodiment replaces the differential transconductance amplifier 50 shown in FIG. 3 used in the attenuator 1 according to the first embodiment with the differential transconductance amplifier 60 shown in FIG. Similarly, in the attenuator 2 according to the second embodiment, the differential transconductance amplifier 50 can be replaced by the differential transconductance amplifier 60. It is possible to further increase the range of the input signal voltage that can be received from such an attenuator.

  The present invention is not limited to the above embodiment, and can be modified as appropriate. For example, the present invention can be realized by using a differential transconductance amplifier having a differential pair of NMOS transistors instead of a differential transconductance amplifier having a differential pair of PMOS transistors. In the above embodiment, a circuit having four switches, four buffer circuits, and four load circuits has been described. However, the number of switches, buffer circuits, and load circuits may be changed as appropriate. Is possible.

FIG. 3 is a circuit diagram of an attenuator according to the first embodiment. FIG. 2 is a circuit diagram of a switch according to the first embodiment. 1 is a circuit diagram of an OTA according to a first embodiment. FIG. 3 is an equivalent circuit diagram of the attenuator according to the first embodiment. FIG. 6 is a circuit diagram of an attenuator according to the second embodiment. 3 is a table showing amplitudes of signals applied to input terminals of the OTA according to the first embodiment; 6 is a table showing the amplitude of a signal applied to an input terminal of an OTA according to a second embodiment. FIG. 6 is a circuit diagram of an OTA according to a third embodiment. It is a circuit diagram of the attenuator of the prior art example 1. FIG. 10 is a circuit diagram of an attenuator of Conventional Example 3. It is a circuit diagram of the attenuator of the prior art example 2.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Attenuator 2 Attenuator 10 Input terminal 11 Control input terminal 12 Output terminal 20 Switch group 30, 30 'Buffer circuit group 31-34, 31-34' Buffer circuit 40, 40 'Load circuit group 41-44, 41'-44' Load circuit 50, 60 OTA
51, 52, 61, 62, 63a, 63b PMOS transistors 53 to 55, 64 to 67 Current source 63 Impedance elements M11 to M18 MOS transistors R11 to R18 Resistors SW1 to SW4 Switches TG1, TG2 Transfer gates INV1, INV2 Inverters VF1 to VF4 Voltage follower

Claims (8)

A switch group having a plurality of switches for outputting either an input signal or a predetermined potential in response to a control signal;
A buffer circuit group having a plurality of buffer circuits equivalently having an amplifier for driving a signal from each connected switch and an output resistor having a predetermined resistance value connected in series to the output of the amplifier;
A plurality of load circuits each connected to an output terminal of the buffer circuit and having a load resistance whose relative accuracy with respect to the output resistance is within a predetermined value are connected in cascade, and an output signal is output from one end of the cascade connected load circuit. And an attenuator having a load circuit group that outputs a signal.   The attenuator according to claim 1, wherein a ladder resistor network is constituted by the plurality of output resistors and the plurality of load resistors.   2. The buffer circuit is configured by an equivalent circuit of an amplifier having a predetermined output impedance and an input impedance larger than the output impedance, and the output impedance connected in series to the output of the amplifier. Attenuator described in 1. The buffer circuit has a non-inverting input terminal connected to the corresponding switch, an inverting output terminal connected to a first potential, and a difference in a first connection type in which the inverting input terminal and the non-inverting output terminal are connected. A dynamic transconductance amplifier,
The load circuit group includes a differential transconductance amplifier of a second connection type in which a non-inverting input terminal and an inverting output terminal are connected, and an inverting input terminal and a non-inverting output terminal are connected in parallel. A first load circuit having two differential connection-type transconductance amplifiers connected to each other; a second load circuit having one differential connection-type transconductance amplifier of the second connection type; The attenuator according to any one of claims 1 to 3, wherein the attenuators are connected in cascade. The buffer circuit has a non-inverting input terminal connected to the corresponding switch, an inverting output terminal connected to a first potential, and a difference in a first connection type in which the inverting input terminal and the non-inverting output terminal are connected. A dynamic transconductance amplifier and a differential transconductance amplifier of a second connection type in which the non-inverting input terminal and the inverting output terminal are connected and the inverting input terminal and the non-inverting output terminal are connected are connected in cascade. And
The load circuit group includes a first load circuit having a differential transconductance amplifier of the second connection type, and two differential transconductance amplifiers of the second connection type connected in series. The attenuator according to any one of claims 1 to 3, wherein the second load circuit is cascade-connected. The first and second connection type differential transconductance amplifiers are respectively connected to the first and second transistors constituting the differential pair and to the drains of the first and second transistors, respectively. First and second current sources that output substantially equal currents,
The first and second transistors have first and second drain currents based on a product of a potential difference between signals input to the gates of the first and second transistors and the transconductance of the differential pair, respectively. And a differential current between the current generated by the first current source and the first drain current flows from the inverting output terminal, and the current generated by the second current source from the non-inverting output terminal and the first current The attenuator according to claim 4 or 5, wherein a difference current from the drain current of 2 flows out.   7. The differential transconductance amplifier of the first and second connection types is further connected with an impedance element connected between the sources of the first and second transistors. Attenuator. The impedance element has a drain connected to the source of the first transistor, a source connected to the source of the second transistor, a gate connected to the non-inverting input terminal, and a source connected to the non-inverting input terminal. 8. The fourth transistor according to claim 7, further comprising: a fourth transistor connected to a source of the first transistor, a drain connected to a source of the second transistor, and a gate connected to an inverting input terminal. Attenuator.

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