JPH1056135A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device having low power consumption and capable of effective mounting, along with an optimum through rate. SOLUTION: A plurality of output buffers B3 in a parallel configuration are constituted at the last stage of a buffer circuit of a digital integrated circuit in a semiconductor integrated circuit device LSI. An output switch circuit is provided for switching the output buffers B3 . The output buffers B3 are selectively operated by the output switch circuit SW according to an outer load of the semiconductor integrated circuit device LSI to change the performance of the output power.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly, to a processor for performing logic signal processing, for example, an MPU.
(Microprocessor unit) or DSP
The present invention relates to a semiconductor integrated circuit device LSI having a digital integrated circuit such as a (digital signal processor), a memory, and a gate array.

[0002]

2. Description of the Related Art In recent years, digitalization of signal transmission, signal processing, and recording has been progressing in AV (audio / video) devices such as personal digital cellular phones, VCRs (video camera recorders), and terrestrial or satellite broadcast tuners. .

Also, the amount of information to be handled tends to increase, and the system clock also tends to increase year by year.

[0004] The speeding up of these digital signals causes various noises. These various noises include reflection noise due to characteristic impedance mismatch, crosstalk noise due to electromagnetic interaction between adjacent wirings, and switching by simultaneous switching of IC (integrated circuit) buffers.
EMC radiated by noise and current flowing through conductors
(Electro Magnetic Compatibility) noise, EMI (Electro Magnetic Immunity) noise, and the like.

In the current electronic equipment,
How to reduce these is a major issue at the product development or design stage.

Incidentally, such a semiconductor integrated circuit LS
The most important factor that determines the magnitude of noise at I is the through rate (= dV / d) of the signal.
t). Generally, the slew rate of a digital signal increases as the clock becomes higher, that is, the rise and fall of the signal become steeper, but correctly, the clock frequency is determined by the relationship between the current driving capability of the semiconductor element to be driven and the load. It is irrelevant in nature.

[0007] and wherein the resistance component is negligible, indicating the slew rate by the _{formula, dV / dt = 2πC L /} gm ‥‥‥ (1) where, gm is the transconductance of the drive element,
C _L is expressed by the sum of the total load capacity up integrated circuit LSI driven. That is, C _L = C _p + C _Int + C _input ‥‥‥ (2) where C _p package capacitance, C _Int is the wiring capacitance, and C _Int is the wiring capacitance.
_input is the input capacity of the buffer.

Accordingly, the slew rate dV / dt is
It is determined by the characteristics of the driving device and the load present on the connection line, especially the capacitance.

On the other hand, personalization and miniaturization of devices are progressing, and high-density mounting technology using so-called bare chips such as multichip modules and flip chip mounting is being developed.

[0010] The bare chip mounting method of this semiconductor chip includes a wire bonding method, a TAB (tape automated bonding) method, and a flip chip (Fl).
The flip-chip method is the best in consideration of high density and high-speed operation.

In the case of bare-chip mounting such as multi-chip module or flip-chip mounting, mounting without a conventional package is possible, so that wiring between integrated circuits LSI can be formed short. The above means that the parasitic components existing in the signal transmission path such as the package, the connection portion, and the wiring are reduced. From the viewpoint of the output buffer of the LSI, the driving load is reduced.

[0012]

Therefore, when the parasitic components are eliminated by mounting a bare chip such as a multi-chip module and the wiring length is shortened to increase the density, the signal becomes clearer from the above equation (1). Has a large slew rate,
That is, the rise and fall become steep, and a situation arises in which the advantage of high density cannot be used in terms of noise.

Therefore, the slew rate is optimized by designing the buffer current of the LSI mounted on the bare chip to a small value in advance, and at the same time, low power consumption is achieved, thereby realizing a very effective mounting. It becomes possible.

However, in this case, the drive circuit is designed to be useful only for the wiring and mounting configuration of the circuit, so that the LSI cannot be shared with other circuits and has an extremely narrow applicable range. That is, an LSI designed according to the mounting form is required, which is very disadvantageous in terms of cost and development period, which is a practical problem.

In the present invention, there is provided an LSI which can solve such inconveniences, can be shared by other circuits, and can widen its application range.

[0016]

According to the present invention, a plurality of output buffers at the last stage of an output buffer circuit of a digital integrated circuit of a semiconductor integrated circuit device LSI are configured in parallel, and the plurality of output buffers are configured in parallel. And an output switch circuit for performing a switching operation. The output switch circuit selectively operates the plurality of parallel-configured output buffers according to the external load of the LSI to change the output current capability.

That is, in the present invention, specifically, a control terminal is provided externally to enable the drive current of the buffer to be changed stepwise.

According to the configuration of the present invention described above, a plurality of parallel-configured output buffers are selectively operated in accordance with an external load so that the output current capability, that is, the output drive current is changed stepwise. That we can do,
While optimizing the slew rate, it is possible to share the circuit with another circuit having a different external load, and to widen the applicable range.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor integrated circuit device LSI according to the present invention will be described. In the present invention, for example, a control terminal is provided outside the LSI so that the drive current of the buffer can be changed stepwise.

FIG. 1 shows a circuit configuration of an example of an output buffer circuit section of a digital integrated circuit of the device of the present invention, and FIG. 2 shows a detailed circuit configuration of an example of a final-stage buffer. In the present invention, the output buffer of the last stage of the output buffer circuit 1 of the digital integrated circuit, in the example shown in FIG.
Of the output buffers B ₁ , B ₂ , and B ₃ provided in stages, the buffer B ₃ in the last stage has a parallel configuration of a plurality of divided buffers. The output buffer circuit 1 is configured so that the drive current is sequentially amplified so as not to increase the delay, and a buffer B _{3 of the} last stage is divided into, for example, 2 ^N (N is a positive integer) divided buffers. In a parallel configuration. In the configuration shown in FIG. 2, in ^the 2 ^N, a case of the parallel configuration of N = 2 and four buffers B _{31 that, B 32, B 33, B} 34. Then, the buffers _{B 31, B 32, B 33} , B switch circuit SW for switching the operation _34, the buffer _{B 31, B 32, B 33} , B ₃₄ of providing the respective input side.
The switch circuit SW includes, for example, a two-input AND circuit (2
(Input AND circuit) An AND circuit configuration may be employed.
That is, in this example, AND ₁ to AND ₄ are arranged at each input of each of the buffers B _{31 to} B ₃₄ , and one input terminal of FIG.
, The output from the buffer B2 in the _second stage in this example. On the other hand, from the external control terminal Tc, N bits, ie, 2 bits in this example,
2 ^N by the bit control signals S _c1 and S _c2
That is, in this example, a decoder 3 for obtaining four signals S _{B1 to} S _B4 is provided, and the respective outputs S _{B1 to} S _B4 are input to the other input terminals of the AND circuits AND _{1 to} AND _4. .

[0021] Figure 3 shows an input signal or control signal S _c1 and S _c2 decoder 3, the relationship between the output signal S _B1 to S _B4 by decoding the control signal S _c1
And the combination of "0" and "1" of the S _c2, the output signal S _B1 to S _B4 combination state of the four "0" and "1" is obtained. That is, for example, by the AND circuit AND ₁ ~AND _4, the buffer B _31,
When all of B ₃₂ , B ₃₃ , and B ₃₄ are operated, the buffer B is operated by AND circuits AND ₂ , AND _3, and AND ₄ .
Buffer B ₃₂ except _31, B _33, and the case of the B ₃₄ is operated, when operating the buffer B ₃₃ and B ₃₄ by the AND circuit the AND ₃ and the AND _4, AND circuit AN
D ₄ by can be obtained operating state when operating only the buffer B _34, can be driven current control of the output buffer.

The buffers B ₃₁ , B ₃₂ , B ₃₃ , and B ₃₄ are, for example, p-channel MOS (insulated gate field effect transistors) (p-
MOS) and n-channel MOS (n-MOS)
A MOS configuration can be used. In the configuration shown in FIG. 4, a two-stage CMOS configuration is used. However, an even-numbered stage having two or more stages and an odd-numbered stage can be used in some cases.
T _in is an input terminal to which the output of the AND circuit AND ₁ ~AND ₄ is input.

AND circuit A constituting switch circuit SW
Each of ND _{1 to} AND ₄ has two input terminals T _i1 and T _i2 as shown in FIG.
It is possible to adopt a configuration in which a CMOS ₁ and a CMOS ₂ having an input configuration are used, and a buffer of a CMOS ₃ is connected to the output side.

FIG. 6 is a plan view of an example of the LSI semiconductor chip 4 of the device of the present invention, and FIG.
FIG. 11 is a cross-sectional view of a main part of a multi-chip module on which another semiconductor chip such as another LSI semiconductor chip is mounted. The semiconductor chips 4 and 41, especially the semiconductor chip 4, are not subjected to a package or resin molding, that is, the semiconductor chip is exposed to the outside, and is formed on the semiconductor chip, for example, at four sides thereof. The terminal portion 10 (including the above-described external control terminal Tc) is exposed in a bare chip configuration, that is, a so-called bare chip configuration. The terminal portion 10 is formed by applying a metal layer 12 to an end portion of a wiring pad 11 derived from a required portion of an IC circuit formed on a semiconductor chip, and soldering the metal layer 12 on the metal layer 12 in a ball shape. That is, the solder protrusions 13 are formed by being piled up. The metal layer 12 is formed of a metal layer that serves to apply a solder material in a limited manner, so-called BLM (ball limiting metal).

The multi-chip module MCM shown in FIG.
In the configuration, a configuration in which a plurality of wiring patterns, in the illustrated example, the wiring patterns P ₁ , P ₂ , and P ₄ are stacked is illustrated. The wiring patterns P ₁ and P ₂ , P ₃ and P ₄
For example, it is formed by performing pattern etching by photolithography on Cu foils respectively adhered to both sides of two glass epoxy substrates (substrates of non-woven glass fibers impregnated with epoxy resin) 5, for example. The two substrates 5 are laminated in a predetermined positional relationship by an insulating adhesive layer 6 and joined and integrated, and a through hole or a via hole 7 is formed in a predetermined portion of the laminated substrate. The inside is metallized by a method such as electroless plating or electroplating to form the conductive layer 8, and electrical connection between required wiring patterns can be made. The conductive layer 8 is entirely formed on the upper and lower outer surfaces of the laminated board, which by pattern etching, can also be a wiring pattern P ₁ or (and).

Then, the semiconductor chip 4 and, in some cases, the bare chip of another semiconductor chip 41 are connected to the wiring pattern P ₁ of the upper layer wiring of the laminated substrate, for example, by the terminal portion 10.
For the corresponding wiring patterns P ₁ and the solder bumps 13
The semiconductor chips 4 and 41 are mounted by the so-called flip chip method. Further, a sealing resin 9 is provided between the semiconductor chips 4 and 41 and the substrate.
Is filled, and the effect of reinforcing the mechanical and electrical bonding of the semiconductor chip to the substrate can be obtained to improve the reliability.

The laminated board on which the bare chip is mounted is
Further, as shown by a chain line in FIG. 7, for example, the printed circuit board 21 is mounted on required wiring by solder bumps 22.

As described above, by forming the bare chip directly on the substrate, the package is eliminated, and the parasitic L, C, and R (parasitic inductance, capacitance, and impedance) components associated with the package are reduced. Since the interposition of a wire or the like in the connection between the wiring and the wiring pattern is eliminated, the wiring length is reduced.

In the above-described bare chip configuration,
Circuit configuration, fan in and fan in
Drive waveform when fan out is 1
FIG. 8 shows the results of the application. The broken line curve in FIG.
Adopts a PCB (Print Circuit
Board), that is, a printed circuit board drive
When using the bare chip configuration,
Solid line curve when each buffer current is 100% controlled
Line 81, 75% control Solid line curve 82, 50% control
If it is controlled, the broken line curve in the case of package configuration and almost
Matching curve 83, solid curve 84 when 25% control is performed
In the case of a bare chip configuration, the buffer current is set to 1
If it is set to 00%, the rise becomes steep.
As described above, the control from the external control terminal Tc
Buffer B₃₁, B ₃₂, B₃₃, B₃₄To
By performing the switching selection operation, the buffer current can be reduced.
Sharp rise of drive waveform by reducing
It turns out that you can control it wonderfully.
And, in this example, when it is reduced to about 50%,
Drive waveforms that are almost the same as when mounting with the package
It can be seen that it can be obtained. That is, using a package
Inconveniences such as noise impairing characteristics compared to mounting
And its power consumption is reduced to 50%, ie
It can be reduced to half. Further, the driving current is set to 2
When reducing it to about 5%, lower noise can be achieved.
And the power consumption of the buffer is about 1/4
It can be reduced.

As described above, according to the configuration of the present invention, since the buffer current can be controlled, the sharp rise of the drive waveform, that is, the slew rate can be selected in the optimum state, and the power consumption can be reduced at the same time. Can be measured.

According to the above-described configuration, the wiring taken in the multi-chip module MCM, for example, a signal line group SL such as a bus line and a clock, can significantly reduce the driving current. However, among the outputs output from the LSI, the load of the signal line SLo output outside the module MCM in which this LSI is arranged is unknown, and therefore the level of the signal line group SL in the module MCM is the same. Output current cannot be adjusted.

Further, there is a difference in the number of fan-outs, that is, the original drive current between a signal line group having a large number of fan-outs such as a bus line and a clock and other data lines and control lines.
The degree of load reduction by the bare chip mount is different.

Therefore, in order to solve these problems, a plurality of sets of the output buffers having the parallel configuration are provided, and the output current capability is changed independently for each set. That is, as shown in a schematic configuration diagram of FIG. 9, for example, among the outputs of the LSI chip 4 mounted in the module MCM, a signal line SL such as a bus line in the module MCM is connected to the external control terminal having the above-described configuration. Tc
However, regarding the signal line SLo such as a bus line outside the module MCM, another external control terminal Tco
So that the external signal line SLo is independently controlled. Note that FIG. 9 shows a case where only one set of signal lines SLo such as bus lines outside the module MCM is shown. However, when there are two or more sets of this signal line SLo, the LSI chip 4 Inside, an output buffer for changing the output current capability independently for each group and an external control terminal are arranged.

In the above-described example, the CMOS logic circuit is exemplified. However, any type of digital logic circuit, for example, Bi-CMOS (CMOS with a bipolar transistor configuration), ECL (Emitter Coupled) is used.
Logic), DCFL (Direct Coupled FE)
T (feed effect transistor logic), GTL (gunning transfer logic), HSTL (high speed transistor logic), and the like can also be used.

In the above example, the switch circuit SW
Is an AND circuit configuration as shown in FIG. 2, but may be a flip-flop circuit configuration as shown in FIG.

In the configuration shown in FIG. 10, a D flip-flop (D-FF) having a data input terminal (D), a clock terminal (CK), a Q output terminal (Q), an inverted Q terminal, and a clear terminal (CLR). This is a case where the switch circuit SW is configured by the following. Also in this example, the buffer B ₃ at the final stage is This is a case in which four buffers B ₃₁ , B ₃₂ , B ₃₃ , and B ₃₄ are arranged in parallel with 2 ^N and N = 2. In FIG. 10, portions corresponding to those in FIG. In this example, a clock signal is applied to the clock terminal CK in common to each D-FF, a clear signal is obtained from the decoder 3, and the D signal is selectively supplied by the clear signal. -By operating the FF, the buffer B _{2 of the} previous stage input to the input terminal D
Is taken out as a Q output. That is, FIG.
In the configuration described above, the buffers B ₃₁ , B ₃₂ , B ₃₃ , and B ₃₄ having a plurality of parallel configurations can be driven in combination. That is, also in this case, the same operation and effect as in the example of FIG. 2 described above can be obtained.

In the above-described configuration of the present invention, the final
Stage buffer B₃₁, B₃₂, B₃₃, B ₃₄The same configuration,
That is, the same drive current can be used, but different
Drive current.

The present invention is not limited to the configuration of the wiring patterns P _{1 to} P ₄ according to the configuration described with reference to FIG.
Various configurations can be used, such as by laminating a small or large number of wiring patterns, a fine pattern configuration in which holes such as via holes are formed by photolithography using photoresist as an insulating layer, and The present invention is not limited to the above-described example. For example, the present invention can be applied to various so-called bare chip mounting configurations in which a chip is directly mounted on the printed circuit board 21 instead of such a configuration. Can be.

[0039]

As described above, according to the present invention, since the buffer current can be controlled, the sharp rise of the drive waveform, that is, the slew rate can be selected in the optimum state, and at the same time, the power consumption can be reduced. Reduction can be achieved. Therefore, when performing bare chip mounting, the load on the mounting system is reduced, and in increasing the density, the signal slew rate can be optimized. Therefore, various types of noise, that is, reflection noise, switching noise, and crosstalk noise can be obtained. In addition, it is possible to reduce electromagnetic radiation noise and the like.

Further, according to the present invention, in the development, design, and manufacture of a semiconductor integrated circuit device, it is possible to greatly reduce the time required for noise suppression by trial and error. Labor and cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an output buffer circuit unit of an example of an integrated circuit device according to the present invention.

FIG. 2 is a detailed configuration diagram of a final-stage buffer of an output buffer circuit section of the integrated circuit device according to the present invention.

FIG. 3 is a table showing input-output signal conversion of a decoder in the apparatus of the present invention.

FIG. 4 is a configuration diagram illustrating a circuit example of a buffer in the device of the present invention.

FIG. 5 is a configuration diagram of an example of a switch circuit (AND circuit) in the device of the present invention.

FIG. 6 is a schematic plan view of an example of a semiconductor chip of the device of the present invention.

FIG. 7 is a sectional view of a main part of a multi-chip module as an example of the device of the present invention.

FIG. 8 is a simulation diagram of slew rate control of the device of the present invention and the conventional device.

FIG. 9 is a schematic configuration diagram of another example of the device of the present invention.

FIG. 10 is a configuration diagram of another example of the switch circuit of the device of the present invention.

[Explanation of symbols]

 1 output buffer circuit, 2 logic circuits, 3 decoders,
B₁, B_Two , B_Three, B ₃₁, B₃₂, B₃₃, B₃₄ Buff
A, SW output switch circuit, 4,41 LSI semiconductor
Chip, 5 substrate, 6 insulating adhesive layer, 7 holes, 8
 Conductive layer, 9 sealing resin, 11 terminals, 12 metal
Layers, 13, 22 solder bumps, 21 printed circuit board

Claims (4)

[Claims] An output buffer circuit for a digital integrated circuit of a semiconductor integrated circuit device, wherein an output buffer at the last stage of an output buffer circuit has a plurality of parallel configurations, and an output switch circuit for switching between the plurality of parallel configuration output buffers is provided. A plurality of parallel-configured output buffers selectively operated by the output switch circuit in accordance with an external load of the semiconductor integrated circuit to change an output current capability. apparatus. 2. The output buffer circuit at the last stage of the output buffer circuit has a parallel configuration of 2 ^N (N is a positive integer), and a 2-input OR circuit is arranged at each input of the output buffer. The output from the internal logic circuit is input to one input of the OR circuit, and the control output of 2 ^N control decoded from the N-bit external control terminal is input to the other input. 2. The semiconductor integrated circuit device according to claim 1, wherein an output switch circuit selectively operates said plurality of parallel-configured output buffers to change an output current capability. 3. The semiconductor integrated circuit according to claim 1, wherein said output switch circuit comprises a flip-flop circuit. 4. The semiconductor integrated circuit device according to claim 1, wherein a plurality of sets of the output buffers having the parallel configuration are provided, and the output current capability is independently changed for each set.