JP3093991B2 - Switchable multi-chip module complementary MOS input / output buffer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an input / output buffer for an integrated circuit chip and an integrated circuit chip package, and more particularly, to an input / output buffer for an integrated circuit chip packaged by a multi-chip module technology.

[0002]

2. Description of the Related Art Multi-chip modules (multi-chip modules) are known.
The simplest definition of a chip module (MCM) is an integrated circuit module (chip carrier) having two or more chips, as shown in FIG. The research and efforts devoted to MCMs for the purpose of overcoming the density and performance limitations of single-chip modules have recently become understood. A multi-chip module combines many high performance integrated circuit chips into a custom substrate structure to allow the full use of integrated circuit functions. For example, Fujitsu's MLG-MCM module contains 144 integrated circuit chips. The composite substrate structure is at the heart of MCM technology, which is a multilayer structure composed of ceramic, polymer, silicon, metal, glass ceramic, printed circuit board (PCB).

[0003] The formal definition of MCM is the Institute for Integrating and Packaging of Electronic Circuits.
erconnecting and Packagin
gElectronic Circuits (IPC)
, Which includes three major MCM categories. 1. MCM-C: A module using thick-film technology, which forms a conductive pattern with a fireable material and is entirely made of ceramic or glass ceramic or another material having a dielectric constant greater than 5. Simply put, MC
The MC is built on a ceramic or glass ceramic substrate. 2. MCM-L: Using a thin-layer structure and employing printed wiring board technology to form a dominant copper conductor. Such a structure includes a thermal expansion control metal layer. Briefly, MCM-L utilizes reinforced plastic thin film printed wiring board technology. 3. MCM-D: A module with multiple signal conductors on a substrate, thin film metal on a non-reinforced dielectric with a dielectric constant less than 5, above a support structure such as silicon, ceramic or metal. Is formed. Briefly, MCM-D uses an unreinforced dielectric on an adherent metal and various rigid substrates.

[0004] Chip on board
ard; COB) technology is widely used for multi-chip module packages. COB is an attachment technique using wire bonding, TAB, or flip chip attachment (FCA) on a printed wiring board or substrate. As shown in FIG. 2, a substrate or printed wiring board 201 is used to mount an integrated circuit chip thereon. The first integrated circuit chip 202 is connected to a substrate or a printed wiring board 201 by a wire loop 203 and attached using a wire bonding technique. The second integrated circuit chip 204 is a substrate or a printed wiring board 20.
1 is attached using TAB technology with a tape-like lead terminal 205. The third integrated circuit chip is flipped and solder balls 2 are placed on the substrate or printed wiring board 201.
07 and attached using FCA technology. F
By using small balls as the connection structure, CA can obtain the following effects over other package technologies.・ High-density input / output connection by area array joint ・ Excellent electrical performance by using small pads for connection ・ Multi-chip connection by single reflow of solder pads

[0005] Because of the connection traces on the MCM substrate, the load is mostly capacitive and only a small p
Fs is required. The trace load is so small that it can be compared to several heavily loaded lines on the chip. These connection traces are treated as extensions of the on-chip network. Small trace load (tra
The size of multi-chip module I / O buffers designed in the chip to connect to these traces for ce-load) can be reduced in chip-to-chip communication.

Recently, in MCM designs, traditional I / O buffers (conventional I / O) have been developed.
(Buffers; CIOB) has been used for FCA. This is mainly because these chips are already completed and ready for use. Otherwise, the CIOB for these chips is M
Not very suitable for CM environment. The performance of the MCM has not been optimized and has certain properties, namely, power dissipation and increased chip-to-chip delay. in addition,
Traditional I / O buffers are typically based on electrostatic charge protection (E
SD). Some MCM I / O buffers have E
No SD structure is required, since the buffer is only used for chip-to-chip communication in the MCM package.

[0007] As MCM and FCA technologies have improved, the properties of low inductance, reduced size, and low disturbance capacitance have been obtained. These properties are VL
It is used to realize high speed and downsizing of SI (very large scale integrated circuit) systems. However, there is room for improvement in chip design to achieve a better system optimized in the MCM packaging environment.

A differential input / output buffer (DIOB) used as a reduced input / output buffer in an MCM-FCA environment
Is T. 'An I / O Bu by Gabara et al.
offer Set Silicon Multi-Ch
ip Module (MCM), pp. 147-152, I
EEE Multi-Chip Module Con
reference, MCMC-93, March 1993 '
It is described in. Although this DIOB provides good operating speed and noise margin, it requires extra bonding pads, thus reducing the yield of MCM manufacturing. Tailoring the MCM-D to market requirements required specialized I / O buffers to achieve high performance with low power dissipation.

[0009]

The present invention relates to the above-described MC.
Made as needed for specialized I / O buffers for M technology.

It is a first object of the present invention to provide a switchable input / output buffer for achieving high performance with low power consumption in an MCM module. The switchable I / O buffers include a minimized single-ended MCM I / O buffer without ESD and a traditional ES
MCM I / O buffer with D and path
Pre-buffer having a selection switch (pre-buff
er). Depending on whether the connection is for chip-to-chip communication within the module or for access to the outside world outside the module, both the minimized buffer and the traditional I / O buffer
Can be used for performance optimization.

A second object of the present invention is to provide a method for forming a path switching structure of an input / output buffer. The mechanisms that provide path switching control include cell-programmable, mask-programmable,
Alternatively, it is completed by a pad programmable method. Of these methods, the cell programmable method has the most applicability, but requires extra area cost. Mask-programmable methods require extra processing costs for additional masks. The pad programmable method replaces the switching structure from a chip layer to an MCM substrate, is suitable for use in FCA technology, and can reduce switching pad dimensions and bonding complexity.

A third object of the present invention is to provide a layout structure for configuring a switchable MCM input / output buffer. A first layout structure applicable to both the cell programmable method and the mask programmable method is provided, wherein the first layout structure is an MCM-type.
It can be used for FCA or PWB single package environment. A second layout structure for use with the pad programmable method is also provided. This second layout structure is designed for an MCM package employing FCA technology.

A fourth object of the present invention is to provide a circuit structure for realizing a switchable MCM input / output buffer. Four different types of circuits for switchable input / output buffers are described. The input / output buffer is divided into a transmitter and a receiver according to functions. In using the input / output buffer of the present invention,
Transmitter and receiver must be of the same type. The circuit structure of both the transmitter and the receiver has been described for four different types of input / output buffers.

According to the present invention, the switchable input / output buffers are compatible with the MCM environment and are CMOS or B
It is a general input / output buffer that can be used for any chip processed by iCMOS or similar technology. It is divided by function into transmitter and receiver. The transmitter performs signal transmission off one chip, while a corresponding receiver on another chip receives the signal. Further, both the transmitter and the receiver have three functional blocks. That is, CI
Pre-buffer having OB (with ESD), MIOB (without ESD), and path switch
r).

By providing a method of providing path switching control, two types of layout structures are offered for selection for switchable I / O buffers. Wherein, the first layout structure leaves traditional large sized I / O pads in harmony with traditional wire bonding techniques, and the first layout structure can be either cell-programmable or mask-programmable. used. It can be applied to MCM as well as PWB single package environment. In the second layout structure, an additional input pad is provided on the transmitter to receive the switching control signal, and all pads are the same size to apply to FCA technology.

The present invention provides four different embodiments of switchable input / output buffers. Each type of input / output buffer has a transmitter and a receiver. Both the transmitter and the receiver have a traditional buffer path and a minimized buffer path. The first input / output buffer type uses an OR gate for path switching control of the transmitter. The second input / output buffer type uses two tri-state inverters as path switching gates.
Two transmission gates are used for buffer path selection for the third input / output buffer type. The fourth input / output buffer type uses an OR gate and a three-state inverter for path switching control.

[0017]

SUMMARY OF THE INVENTION The invention of claim 1 is a switchable input / output buffer structure for a kind of multi-chip module, including one transmitter, the transmitter comprising a transmitter input signal and a path selection signal. A pre-buffer including an output path switch for receiving a signal, a traditional output buffer, and a minimized output buffer, wherein the path selection signal controls the output path switch to provide a traditional output of the transmitter. When the pad is bonded for connection outside the multi-chip module, the transmitter input signal is transmitted through a traditional output buffer to the traditional output pad of the transmitter, minimizing the transmitter. The output pad is used for chip-to-chip communication in a multi-chip module. When bonded for communication, the transmitter input signal is transmitted to the minimized output pad via the minimized output buffer, and the input / output buffer structure further includes one receiver; The receiver includes an input path switch, a traditional input buffer, and a minimized input buffer, wherein the receiver receives a minimized receiver input signal from a minimized input pad or receives a traditional receiver input signal from a traditional input pad. Receiving and generating one receiver output signal, the input path switch is adapted to output the receiver output signal when the traditional input pad is bonded for connection outside a multi-chip module; Pass the traditional receiver input signal through a traditional input buffer and In the case where coded entry pad is bonded to the chip-to-chip communication within the multi-chip module,
In order to output the receiver output signal, the minimized receiver input signal is made to pass through the minimized input buffer, and a switchable input / output buffer structure for a multi-chip module having the above configuration is provided.

According to a second aspect of the present invention, there is provided a switchable input / output buffer structure for a multichip module according to the first aspect, wherein the layout structure of the transmitter includes the output path switch. Area 401 for the traditional output buffer, two areas 402 and 403 for the traditional output buffer, an area 404 for the minimized output buffer, an area 405 for the minimized output pad, The receiver layout structure includes an area 406 for the output pad, an area 406 for the traditional input buffer, an area 409 for the minimized input buffer, and an area 409 for the traditional input buffer. Area 410 for pads and area 411 for the minimized input pad
And a switchable input / output buffer structure for a multi-chip module.

According to a third aspect of the present invention, there is provided a switchable input / output buffer structure for a multichip module according to the first aspect, wherein the layout structure of the transmitter includes the output path switch. Area 501 for the traditional output buffer, two areas 502 and 503 for the traditional output buffer, an area 504 for the minimized output buffer, an area 505 for the minimized output pad, and the traditional An area 506 for an output pad and an area 507 for one input pad for providing a path switching signal from the base of the multi-chip module, wherein the layout structure of the receiver is the traditional input buffer. And two areas 508, 509 for the minimizing input buffer. 510, an area 511 for the traditional input pad, and an area 512 for the minimized input pad. .

According to a fourth aspect of the present invention, there is provided a switchable input / output buffer structure for a multi-chip module according to the third aspect, wherein an area 505 for the minimized output pad and the traditional output. An area 506 for a pad and an area 507 for one input pad for providing a path switching signal from the base of the multi-chip module have the same size, It has a switchable input / output buffer structure for a multichip module.

According to a fifth aspect of the present invention, there is provided a switchable input / output buffer for a kind of multi-chip module, including one transmitter and one receiver,
The transmitter includes a first inverter, an OR gate, a traditional output buffer, and a second inverter;
The first inverter has an input terminal and an output terminal, the input terminal receiving a transmitter input signal, and the OR gate has a second input terminal in addition to a first input terminal for receiving a path selection signal, and one or more input terminals. An output terminal, wherein the traditional output buffer has one input terminal connected to the output terminal of the OR gate, one output terminal connected to the first transmitter output terminal, and the second inverter. Includes one input terminal connected to the output terminal of the first inverter, and one output terminal connected to the second input terminal of the OR gate, and the output terminal of the second inverter has one output terminal. Connected to a second transmitter output, the receiver including a first receiver input, a second receiver input, a traditional input buffer, a NAND gate, and a third inverter; Is connected to the first pull high active register one, first receiver input receives a first receiver input signal, the second receiver input,
Connected to one second pull high active register, the second receiver input receiving a second receiver input signal, the traditional input buffer comprising one input connected to the first receiver input; One output terminal, wherein the NAND gate has a first input terminal connected to the output terminal of the traditional input buffer, a second input terminal connected to the second receiver input terminal, and one output terminal. With an end,
The third inverter has an input terminal connected to the output terminal of the NAND gate, and an output terminal connected to one receiver output terminal, and the first transmitter output terminal is connected to a connection outside the multi-chip module. If the bonding is performed, the path selection signal is set to low level to control the transmitter so that the transmitter input signal is sent to the first transmitter output terminal, and the second transmitter output terminal is connected to the multi-chip module. If the chip is bonded for chip-to-chip communication, the path select signal is set to a high level to control the transmitter to send the transmitter input signal to the second transmitter output, The receiver input terminal is The first receiver input signal is sent to the receiver output if bonded for out-of-module connections, and the second receiver input is bonded for chip-to-chip communication in a multi-chip module. If so, the second receiver input signal is sent to the receiver output terminal to provide a switchable input / output buffer for a multi-chip module having the above configuration.

According to a sixth aspect of the present invention, there is provided a switchable input / output buffer for the multichip module according to the fifth aspect, wherein the transmitter is further provided as a fourth inverter, and the fourth inverter receives the path selection signal. An inverter having an input terminal and an output terminal, a fifth inverter having an input terminal connected to the output terminal of the fourth inverter, and an output terminal connected to a first input terminal of the OR gate; A first input terminal of the OR gate is separated from the path selection signal, a sixth inverter, an input terminal connected to the first inverter input terminal,
An input terminal connected to the output terminal of the sixth inverter; an inverting gate control input terminal connected to the output terminal of the fourth inverter; A multi-chip module comprising: a non-inverting gate control input terminal connected to the output terminal of the fifth inverter; and an output terminal connected to the output terminal of the second inverter. And a switchable input / output buffer.

According to a seventh aspect of the present invention, there is provided a switchable input / output buffer for a kind of multi-chip module, including one transmitter and one receiver,
The transmitter includes a first inverter, a second inverter, a third inverter, a first three-state inverter, and a second inverter.
A tri-state inverter, a traditional output buffer, and a fourth inverter, wherein the first inverter has one input and one output, the first inverter input receiving a transmitter input signal; The second inverter has one input connected to the output of the first inverter and one output, and the third inverter has one input for receiving a transmitter input signal;
An output terminal of the third inverter, and an inverting gate control input terminal connected to an output terminal of the first inverter. One non-inverting gate control input connected to the output of the second inverter;
An output terminal connected to a first pull high active register, the second tri-state inverter having one input terminal connected to an output terminal of the third inverter, and an output terminal of the second inverter; One inverting gate control input connected to the first terminal, one non-inverting gate control input connected to the output of the first inverter, and one output connected to the second pull high active register. The traditional output buffer has one input connected to the output of the second three-state inverter and one output connected to one first transmitter output. The receiver has a first receiver input and a second receiver input.
A receiver input, a traditional input buffer, a fifth inverter, a NAND gate, and a sixth inverter;
The first receiver input is connected to a third pull high active register, the first receiver input receives a first receiver input signal, and the second receiver input is connected to one pull low active register, The second receiver input receives a second receiver input signal, the traditional input buffer has one input connected to the first receiver input, one output, and the fifth input.
An inverter has one input connected to the second receiver input and one output, and the NAND gate has a first input connected to the output of the traditional input buffer. , A second input terminal connected to the output terminal of the fifth inverter, and one output terminal. The sixth inverter has one input terminal connected to the output terminal of the NAND gate, and one output terminal. One output terminal connected to one receiver output terminal, and if the first transmitter output terminal is bonded for connection outside the multi-chip module, the path selection signal is set to a low level. Control the transmitter to send the transmitter input signal to the first transmitter output terminal, and the second transmitter output terminal is connected to the multi-chip module. Chip-to-chip the transmitter input signal the second and if are bonded by the path selection signal is set to a high level controls the transmitter for communication
A first receiver input signal is sent to the receiver output terminal if the first receiver input terminal is bonded for connection outside the multi-chip module; If the end is bonded for chip-to-chip communication in a multi-chip module, the second receiver input signal is sent to the receiver output end, for a multi-chip module having the above configuration. And a switchable input / output buffer.

According to an eighth aspect of the present invention, there is provided a switchable input / output buffer for the multichip module according to the seventh aspect, wherein a first pull-low active register is used instead of the first pull-high active register. A second pull-low active register is used instead of the second pull-high active register, and a first transmission gate is used instead of the first three-state inverter, and the first transmission gate is connected to the third inverter. One input terminal connected to the output terminal,
One inverting gate control input connected to the output of the first inverter, one non-inverting gate control input connected to the output of the second inverter, and the first pull-low active register. And a second transmission gate is used in place of the second three-state inverter, and the second transmission gate is connected to the one output terminal of the third inverter. The input end and the second
One inverting gate control input terminal connected to the output terminal of the inverter, one non-inverting gate control input terminal connected to the output terminal of the first inverter, and one inverting gate control input terminal connected to the second pull-low active register. And the output terminal of the NAND gate is directly connected to the receiver output terminal by omitting the sixth inverter, thereby enabling switching for the multi-chip module having the above configuration. I / O buffer.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG. 3, the switchable input / output buffer (SIOB) for the multichip module of the present invention is functionally divided into two parts. One is a transmitter 310, which is used to transmit signals off-chip, and the other is a receiver 320.
Used to receive signals outside of the chip. Furthermore, each part is divided into three smaller functional blocks.
That is, (1) a traditional input / output buffer (CIOB) 311, 321 having ESD, and (2) a minimized single-ended MCM input / output buffer (MIO) without ESD.
B) 312, 322, and (3) three pre-buffers 313 and 323 having a path switch. The transmitter has one signal input, one path switching control input, a traditional buffer output, and a minimized buffer output. The receiver has one traditional buffer input and one minimized buffer output.

When using SIOB, CIOB and MIO
The choice of which of the B paths to use must be the same for the corresponding transmitter 310 and receiver 320. The selection is made based on the module on / off characteristics of the input / output signal. At the transmitter, a path switching signal 'sel' is provided to select one of the two paths. At the receiver, two pull high and low (p
(ull-high / low) active registers are used for the same task.

In the present invention, the buffer is designed for chip-to-chip communication in an MCM package, so that the ESD protection structure is eliminated from the MIOB of the present invention. The buffer of the present invention is directly external, ie, MC
There is no access outside the M module. But E
SD protection is reserved in each I / O buffer, as in CIOB, which is provided for connection with the MCM package. Since the ESD protection structure has been removed, the required chip area for the pre-buffer block and the MIOB block is about one tenth of that of the CIOB block.
Becomes Reduction of chip area reduces capacitive load by 3-4p
It is effective to decrease to F, thereby increasing the operation speed.

The path switching signal 'se at SIOB
There are several ways to provide l '. But,
It is necessary to make a choice between these methods. The Cell Programmable (CP) method can provide the best flexibility because it allows user choice by software using switching control bits stored on the chip. However, there is a problem that extra area cost is required. If the storage cells for the switching control bits were merged into other available mechanisms, such as those used for boundary scan testing, the extra area cost could be reduced to a minimum.

The mask programmable (MP) method is a selectable method, which does not require the extra area cost to provide the path switching signal. But,
The need for an additional mask creates a need for extra processing costs. MP or CP method uses control signal 'se
When adopted in SIOB to provide 1 ', its I / O buffer can be used in both MCM-FCA environment and PWB single package. Then, the first SIOB layout structure shown in FIG. 4 should be applied. In FIG. 4, parts A and B show the layout structure of the transmitter and receiver of the SIOB of the present invention, respectively. The switching control signal for the layout structure is M
Both P and CP methods are provided.

In FIG. 4, the layout structure of the transmitter shown by A is such that an area 401 having an output signal pre-buffer having a path switch and an area
CIO with ESD protection for transmission outside M package
Areas 402 and 403 containing B and M without ESD protection
MIOB for chip-to-chip communication in CM
, An area 405 having solder ball output pads for MIOB, and an area 406 having traditional CIOB output pads. In FIG. 4, the layout structure of the receiver indicated by B is a pull high and low register (pull high) for receiving a signal from outside the CIOB having the ESD protection and the MCM package.
Area 407, which includes / low resistor).
408, an area 409 including pull-high and low registers without ESD protection for chip-to-chip communication in MIOB and MCM packages, and a traditional CIO.
An area 410 including a B input pad and an area 411 having a solder ball input pad for MIOB are included.

In a third selectable layout structure, using the Pad Programmable (PP) method, one extra input pad is required for the MIOB transmitter to send a 'sel'. Unlike the mask-programmable method, the control signal 'sel' comes from the substrate rather than the chip layer. Therefore, the control signal 'se
An MCM substrate is used instead of a chip as a structure to provide l ′. Switching pad dimensions and bonding complexity must be reduced to be cost effective. Because of the potential for minimizing the complexity of the chip design, the pad programmable method is more compatible with FCA environments. FIG. 5 shows a second layout structure of the SIOB transmitter and receiver. Its layout structure is specifically designed for the MCM-FCA environment.

In FIG. 5, the transmitter layout structure shown in FIG. 5A includes an area 501 including an output signal prebuffer having a path switch, and a CIOB with an ESD for transmitting a signal to the outside world, that is, outside the MCM package. Two areas 502, 503 including an MIOB without ESD for chip-to-chip communication in an MCM package; an area 505 including solder ball output pads for the MIOB;
An area 506 including an IOB output pad and an area 507 including a solder ball input pad for providing a path switching signal from the MCM substrate are included. In FIG. 5, B
Shows the layout structure of the receiver, which is an area 50 including a CIOB with ESD protection and a pull high and low register for receiving signals from outside the MCM package.
8, 509, area 510 including pull-high and low registers without ESD protection for chip-to-chip communication in MIOB and MCM packages, and traditional C
Area 511 including IOB solder ball input pad
And an area 512 including a solder ball input pad for MIOB.

The first layout structure shown in FIG. 4 retains traditional large size I / O pads for compatibility with traditional wire bonding techniques. Therefore, it is M
It can be used in either a CM or PWB single package environment. It is also a non-switchable CI
An OB set is needed to store the switching control bits in the chip. In the second layout structure, an extra input pad is added to the transmitter and used to receive the control signal 'sel',
All pads have side lengths of about 35 due to the use of FCA technology
It has the same dimensions of micrometers. The extra pad is fixed in the position shown in the figure, or is implanted at another ideal location in the chip. Three pads 505,5
06, 507 all have the same dimensions and are small enough to benefit from FCA technology. SI
Both of the two types of OB layout structures are arranged in a precise and compact manner, and thus can achieve a smaller chip area. The switchable input / output buffer is designed to have various operational possibilities. Therefore, they can be a set of standard cells used during general ASIC design.

What is important is that both of the layout structures shown in FIGS. 4 and 5 have the same basic form, which shows the functional blocks of all the SIOB circuits of the present invention described later. Used for In the following, four preferred embodiments will be described in order to understand the switchable MCM input / output buffer. The focus of the description is on the minimized input / output buffer and the path switch. A traditional input / output buffer, well known to those skilled in the art, is indicated in the figure by a simplified black line box with two inverters.

FIG. 6 shows a first embodiment of the SIOB. In FIG. 6, a transmitter according to the first embodiment indicated by A includes a first inverter 601 and a second inverter 60.
2, OR gate 603, and traditional output buffer TB
FF604 is included. 'In' and 'sel' for input signal
And the output signals are 'outA' and 'outA'.
There are two of B '. The traditional output buffer path includes first and second inverters 601, 602 and a traditional output buffer 604. The minimized output buffer path of the present invention only includes first and second inverters 601, 602.
The input signal 'in' comes from the core logic of the chip, and the input control signal 'sel' determines whether the input signal goes through a traditional buffer path or a minimized buffer path. When 'sel' is pulled high, the output of OR gate 603 goes high, whether by the signal coming from the internal programmable storage cell or the signal coming from the solder ball input pad, and the output signal ' outA 'is kept at a constant level. Under this circumstance, only one signal path goes through the minimized output buffer path. When 'sel' goes low, 'outA' and 'ou
tB 'is output. However, in embodiments where only one output pad is bonded to the substrate, either 'outA' or 'outB' is transmitted, depending on whether a traditional output buffer 604 or a minimized output buffer is desired. Note that the traditional output buffer 60
Switching activity to 4 is to be avoided due to its large size and problematic power consumption. In FIG. 6, the receiver of the first embodiment of the SIOB of the present invention shown in B is
First pull high active register 605, traditional input buffer RBUFF 606, second pull high active register 607, NAND gate 608, third inverter 6
09. There are two input signals, 'inA' and 'inB', to receive signals sent from the traditional input pad and the minimized input pad respectively. Only the output signal enters the core logic in the chip. No switching signal is required at the receiver because each input pad has a pull-high active register. The pull-high effect ensures NA
There is no interference between the two input signal paths at the ND gate 608. When the receiver runs, only one input pad is bonded for connection. If the input pad for the input signal 'inA' is bonded, while the other input pads are not connected, the input signal will be the traditional input buffer 606, NAND gate 608,
And the third inverter 609 to reach the output node.
Input signal 'inA' passes through NAND gate 608,
This is because the input to the other NAND gate 608 is pulled high. Similarly, if the input pad for input signal 'inB' is bonded and no other input pad is connected, signal 'inB' will be
Directly reaches the output node 609 via the gate 608 and the inverter 609.

Second Embodiment: A second embodiment of the SIOB of the present invention is shown in FIG. The transmitter of the second embodiment is as shown at A in FIG.
01, the second inverter 702, the third inverter 703,
The fourth inverter 704 and the first three-state inverter 705 (f
first gated tri-state inve
rter), second three-state inverter 706, first pull high active register 707, second pull high active register 708, and traditional output buffer TBUFF 70
9 inclusive. The input signal has two of 'in' and 'sel', and the output signal has two of 'outA' and 'outB'. The traditional output buffer path is the third inverter 70
3, a second three-state inverter 706, and a traditional output buffer 709. The minimized output buffer path of the present invention includes a third inverter 703, a first three-state inverter 705, and a fourth inverter 704. When signal 'sel' is pulled high, the minimized output buffer path is selected, whether from a signal coming from an internal programmable storage cell or from a wired solder ball input pad. Because the first three-state inverter 705
Is active. Conversely, when the second tri-state inverter 706 is active, the traditional output buffer path is selected. A pull high active register follows either of the two tri-state inverters. These active registers remove the ambiguity of the outputs of the three-state inverters 705, 506 and prevent the possibility of large power consumption by the fourth inverter and the traditional output buffer 709 when the three-state inverter is in the three-state. Used for SI
The receiver of the second embodiment of the OB is almost the same as that of the first embodiment, except that it has an additional inverter. It is the third pull high active register 7
10, a traditional input buffer RBUFF 711, a first pull-low active register 712, a NAND gate 713, a fifth inverter 714, and a sixth inverter 715. Then, there are two input signals 'inA' and 'inB' to receive signals sent from the traditional input pad and the minimized input pad, respectively, and the output signal only goes to the core logic in the chip. It is. The addition of the fifth inverter 714 is necessary because the corresponding minimized output buffer path of the transmitter has three inverters. Each signal is therefore kept in the same phase. First pull low active receiver 71
2 ensures that the output of the fifth inverter 714 is maintained at a high level when the input pad for 'inB' is not bonded.

Third Embodiment: A third embodiment of the SIOB of the present invention is shown in FIG. 8, in which the transmitter shown at A uses a transmission gate instead of a three-state inverter. The transmitter includes a first inverter 801, a second inverter 802, a third inverter 803, a fourth inverter 804, a first transmission gate 805, a second transmission gate 806, and a first pull-low active register 807 (fi
rst pull low active resistance
tor), a second pull-low active register 808, and a traditional output buffer TBUFF 809. Two transmission gates are used in place of the two three-state inverters of the second embodiment to perform a gate operation.
Two pull low active registers are used relatively more often than pull high active registers to match the use of transmission gates. While the three-state inverter of the second embodiment can perform signal enhancement and inversion, the transmission gate of the third embodiment has the feature that it requires less area. The choice between the second and third embodiments is determined by the needs of the actual application. Second
As in the transmitter of the embodiment, the input signal is "in"
And 'sel', and the output signal is 'outA'
And 'outB'. The traditional output buffer path includes a third inverter 803, a second transmission gate 806,
Includes a traditional output buffer 809. The minimized buffer path of the present invention includes the third inverter 803 and the first transmission gate 80.
5 and a fourth inverter 804. The receiver of the third embodiment of the SIOB is almost the same as that of the second embodiment, except that one inverter is removed in the third embodiment. The receiver of the third embodiment includes a first pull high active register 810 and a traditional input buffer RB.
UFF 811 and third pull-low active register 81
2, a NAND gate 813, and a fifth inverter 814
including. The reason why the number of inverters is reduced by one compared with the receiver of the second embodiment is that it is necessary to design an input / output buffer. Typically, the total number of inverters is the same for the receiver and the transmitter, thereby maintaining an in-phase relationship between the transmitter and the receiver.

Fourth Embodiment: A fourth embodiment of the SIOB of the present invention is shown in FIG. 9, in which the transmitter shown at A differs from that of the second embodiment shown in FIG. The difference is that three three-state inverters are used. The transmitter according to the third embodiment includes a first inverter 901, a second inverter 902, a fourth inverter 904, a fifth inverter 905, a sixth inverter 906, and a three-state inverter 9
07, OR gate 908 and traditional output buffer TB
UFF909. 'In' and 'se
l ', and the output signals are' outA 'and' ou
tB '. When the signal 'sel' is pulled high, a minimized output buffer path is used and the tri-state inverter is active but not tri-state. The input signal 'in' is supplied to the sixth inverter 906 and the three-state inverter 90.
7 to the minimized output pad. At the same time, the signal 'in' also passes through the first and second inverters to the same output pad. In the ideal case, the two signals are in phase and reinforce each other. In practice, there is a phase difference between them. However, it is important that this phase difference be kept very small. If the signal 'sel' is low, the first inverter 901 and the second inverter 9
02, OR gate 908 and traditional output buffer TBU
A traditional output buffer path including FF909 is used. The receiver of the fourth embodiment shown in FIG. 9B is the same as that of the first embodiment shown in FIG. 6B except for the assembly dimensions. It comprises a first pull high active register 910 and a traditional input buffer RBUFF 911
, The second pull high active register 912, and the NAN
It includes a D gate 913 and a third inverter 903. The operation of this receiver has already been described in the first embodiment. When using SIOB, CI
The choice between using the OB or MIOB path must be made at both the transmitter and the receiver. However, transmitters and receivers of the same type are paired. All four types of SIOB were tested in a 0.9 um CMOS process. Typically, the measurement performance of SIOB exceeded 250 MHz when the MIOB path was used. CIOB path is selected and general type CIOB is TBUFF and RB
When used for UFF, only an operating speed of 80 MHz was measured for SIOB. The measured power consumption of each pair of SIOBs using MIOB is 250
It was about 25 mW at MHz and the power consumption was as predicted by simulation. In addition, at the same power consumption, the operating speed achieved by the CIOB path was only 80 MHz.

The above is a description of a preferred embodiment of the present invention for explaining the present invention, and is not intended to limit the present invention, and various changes in details made within the spirit scope of the present invention are also described. It belongs to the present invention.

[0040]

The present invention has been made with the need for specialized input / output buffers for MCM technology,
The present invention provides a switchable input / output buffer for achieving high performance with low power consumption in an MCM module. The switchable input / output buffer is ES
It includes a minimized single-ended MCM I / O buffer without D, an MCM I / O buffer with traditional ESD, and a pre-buffer with a path selection switch. Both the minimized buffer and the traditional I / O buffer optimize MCM performance depending on whether the connection is for chip-to-chip communication within the module or for access to the outside world outside the module. It can be used for conversion.

[Brief description of the drawings]

FIG. 1 is a partially broken perspective view of a known MCM package including a plurality of chips.

FIG. 2 is a cross-sectional view of an MCM substrate or printed wiring board having three dies bonded by known wire bonding, TAB, and flip chip mounting techniques.

FIG. 3 is a block diagram showing a structure of a switchable input / output buffer including a transmitter and a receiver according to the present invention.

FIG. 4 is a first view of a switchable input / output buffer including a transmitter (A) and a receiver (B) according to the present invention;
It is a layout structure diagram. Note that any of the cell programmable method and the mask programmable method can be used to perform path switching control.

FIG. 5 shows a second example of a switchable input / output buffer including a transmitter (A) and a receiver (B) according to the present invention.
It is a layout structure diagram. Note that a pad programmable method is always used to perform path switching control.

FIG. 6 is a circuit diagram of a transmitter and a receiver of a first embodiment of a switchable input / output buffer according to the present invention, in which an OR gate is used for performing path switching control.

FIG. 7 is a circuit diagram of a transmitter and a receiver according to a second embodiment of the switchable input / output buffer of the present invention, in which two three-state inverters are used for performing path switching control. .

FIG. 8 is a circuit diagram of a transmitter and a receiver according to a third embodiment of the switchable input / output buffer of the present invention, in which two transmission gates are used for performing path switching control.

FIG. 9 is a circuit diagram of a transmitter and a receiver of a fourth embodiment of a switchable input / output buffer according to the present invention, in which one OR gate and one three-state inverter perform switching control. in use.

[Explanation of symbols]

Reference Signs List 201 substrate or printed wiring board 202 first integrated circuit chip 203 wire loop 204 second integrated circuit chip 205 tape-shaped lead terminal 207 solder ball 310 transmitter 320 receiver 311, 321 Traditional input / output buffer (CIOB) 312 having ESD 322 Minimized single-ended MCM input / output buffer (MIOB) without ESD 313, 323 Prebuffer with path switch 401 Area for prebuffer 402, 403 Area for traditional output buffer 404 Minimized output buffer Area 405 area for minimized output pads 406 area for traditional output pads 407, 408 area for traditional input buffers 409 area for minimized input buffers 41 Area for traditional input pad 411 Area for minimized input pad 501 Area for prebuffer 502, 503 Area for traditional output buffer 504 Area for minimized output buffer 505 Area for minimized output pad Area 506 for traditional output pads 507 area for one input pad to provide path switching signals from the base of the multi-chip module 508, 509 area 510 for traditional input buffers 510 minimization Area for input buffer 511 Area for traditional input pad 512 Area for minimized input pad 601 First inverter 602 Second inverter 603 OR gate 604 Traditional output buffer 605 First pull high active register 606 Tradition Dynamic input buffer 607 second pull high active register 608 NAND gate 609 third inverter 701 first inverter 702 second inverter 703 third inverter 704 fourth inverter 705 first three state inverter 706 second three state inverter 707 first pull high Active register 708 Second pull high active register 709 Traditional output buffer 710 Third pull high active register 711 Traditional input buffer 712 First pull low active register 713 NAND gate 714 Fifth inverter 715 Sixth inverter 801 First inverter 802 First 2 inverter 803 3rd inverter 804 4th inverter 805 1st transmission gate 806 2nd transmission gate 807 1st pull-low active register 808 Second pull-low active register 809 Traditional output buffer 810 First pull-high active register 811 Traditional input buffer 812 Third pull-low active register 813 NAND gate 814 Fifth inverter 901 First inverter 902 Second inverter 904 Fourth inverter 905 Fifth inverter 906 Sixth inverter 907 Three-state inverter 908 OR gate 909 Traditional output buffer 910 First pull high active register 911 Traditional input buffer 912 Second pull high active register 913 NAND gate 903 Third inverter

Claims (8)

(57) [Claims] 1. A switchable input / output buffer structure for a kind of multi-chip module, including a transmitter, the transmitter including an output path switch for receiving a transmitter input signal and a path selection signal. A pre-buffer, a traditional output buffer, and a minimized output buffer, wherein the path select signal controls the output path switch so that the traditional output pad of the transmitter is connected to the outside of the multi-chip module. The transmitter input signal through a traditional output buffer to the traditional output pad of the transmitter when the transmitter minimizes the output pad of the transmitter in a multi-chip module. Bondin for communication And transmitting the transmitter input signal via the minimized output buffer to the minimized output pad, wherein the input / output buffer structure further includes a receiver, the receiver comprising an input path. A switch, a traditional input buffer, and a minimized input buffer, wherein the receiver receives a minimized receiver input signal from a minimized input pad or receives a traditional receiver input signal from a traditional input pad to form one receiver. Generating an output signal; the input path switch connecting the traditional receiver input to output the receiver output signal when the traditional input pad is bonded for connection outside a multi-chip module; The signal is passed through a traditional input buffer and the minimized input pad is When bonded for chip-to-chip communication within the tool, the minimized receiver input signal is passed through the minimized input buffer to output the receiver output signal. A switchable input / output buffer structure for a multi-chip module having the following configuration. 2. A switchable input / output buffer structure for a multi-chip module according to claim 1, wherein:
Wherein the layout structure of the transmitter includes an area 401 for the pre-buffer including the output path switch, two areas 402 and 403 for the traditional output buffer, and an area 401 for the minimized output buffer. Area 404, an area 405 for the minimized output pad, and an area 40 for the traditional output pad
6 wherein the layout structure of the receiver comprises two areas 407, 408 for the traditional input buffer.
And an area 409 for the minimized input buffer;
A switchable input / output buffer structure for a multi-chip module, comprising an area 410 for the traditional input pad and an area 411 for the minimized input pad. 3. A switchable input / output buffer structure for a multi-chip module according to claim 1, wherein:
The transmitter layout structure includes an area 501 for the pre-buffer including the output path switch, two areas 502 and 503 for the traditional output buffer, and an area 501 for the minimized output buffer. Area 504, an area 505 for the minimized output pad, and an area 50 for the traditional output pad
6 and an area 507 for one input pad for providing a path switching signal from the base of the multi-chip module, wherein the layout structure of the receiver comprises two areas for the traditional input buffer. 508, 509, area 510 for the minimized input buffer, and area 5 for the traditional input pad
11. A switchable I / O buffer structure for a multi-chip module, comprising: an area 512 for the minimized input pad. 4. A switchable input / output buffer structure for a multi-chip module according to claim 3, wherein:
And an area 505 for the minimized output pad.
The area 506 for the traditional output pad and the area 507 for one input pad for providing a path switching signal from the base of the multi-chip module have the same dimensions. A switchable input / output buffer structure for a multichip module, characterized in that: 5. A switchable input / output buffer for a kind of multi-chip module, comprising one transmitter and one receiver, said transmitter comprising a first inverter, an OR gate, a traditional output buffer and , A second inverter, the first inverter having an input terminal and an output terminal, the input terminal receiving a transmitter input signal, the OR gate having a first input terminal for receiving a path selection signal, The traditional output buffer has a second input and an output, the traditional output buffer having one input connected to the output of the OR gate and one output connected to the output of the first transmitter. The second inverter has one input terminal connected to the output terminal of the first inverter and one input terminal connected to the second input terminal of the OR gate. An output of the second inverter is connected to one second transmitter output, the receiver comprising a first receiver input, a second receiver input, a traditional input buffer, A NAND gate;
A third inverter, wherein the first receiver input is connected to one first pull high active register, the first receiver input receives a first receiver input signal, and the second receiver input is Connected to two second pull-high active registers, the second receiver input being connected to a second
Receiving a receiver input signal, the traditional input buffer has one input connected to the first receiver input, and one output; and the NAND gate is an output of the traditional input buffer. , A second input terminal connected to the second receiver input terminal, and one output terminal, and the third inverter is connected to an output terminal of the NAND gate. An input terminal, and an output terminal connected to one receiver output terminal, wherein if the first transmitter output terminal is bonded for connection outside the multi-chip module, the path selection signal is low. To control the transmitter to send the transmitter input signal to the first transmitter output terminal, and the second transmitter output terminal to If the chip is bonded for chip-to-chip communication in the multi-chip module, the path selection signal is set to a high level to control the transmitter to send the transmitter input signal to the second transmitter output end; If the first receiver input is bonded for connection outside a multi-chip module, the first receiver input signal is sent to the receiver output, and if the second receiver input is A switchable input / output buffer for a multi-chip module, wherein the second receiver input signal is sent to the receiver output if bonded for chip-to-chip communication. . 6. A switchable input / output buffer for the multichip module according to claim 5, wherein:
The transmitter further includes a fourth inverter having an input terminal for receiving the path selection signal and an output terminal; and a fifth inverter having an input terminal connected to an output terminal of the fourth inverter. And an output connected to a first input of the OR gate, wherein the first of the OR gate
An input terminal separated from the path selection signal, a sixth inverter, an input terminal connected to the first inverter input terminal, and an output terminal; and a three-state inverter; And an input terminal connected to the output terminal of the sixth inverter, an inverting gate control input terminal connected to the output terminal of the fourth inverter, and a non-inverting gate control connected to the output terminal of the fifth inverter. A switchable input / output buffer for a multi-chip module, comprising: an input terminal and an output terminal connected to an output terminal of the second inverter. 7. A switchable input / output buffer for a kind of multi-chip module, comprising one transmitter and one receiver, wherein the transmitter has a first inverter, a second inverter, a third inverter and , A first three-state inverter, and a second
A third inverter, a traditional output buffer, and a fourth inverter, the first inverter having one input and one output, the first inverter input receiving a transmitter input signal; The second inverter has one input terminal connected to the output terminal of the first inverter, and one output terminal. The third inverter has one input terminal for receiving a transmitter input signal, and one input terminal. An output terminal of the third inverter; an input terminal connected to an output terminal of the third inverter; one inverting gate control input terminal connected to an output terminal of the first inverter;
The second three-state inverter has one non-inverting gate control input terminal connected to the output terminal of the second inverter and one output terminal connected to the first pull high active register. One input terminal connected to the output terminal of the three inverters, one inverting gate control input terminal connected to the output terminal of the second inverter, and one non-inverting terminal connected to the output terminal of the first inverter. A gate control input, and one output connected to a second pull high active register, wherein the traditional output buffer has one input connected to the output of the second three state inverter; One receiver connected to one first transmitter output, the receiver comprising a first receiver input, a second receiver input, and a traditional input buffer. And a fifth inverter,
A NAND gate and a sixth inverter, wherein the first receiver input is connected to a third pull high active register, the first receiver input receives a first receiver input signal, and the second receiver input is , One pull-low active register, the second receiver input receiving a second receiver input signal, the traditional input buffer comprising one input connected to the first receiver input, and one input connected to the first receiver input. The fifth inverter has one input connected to the second receiver input, and one output, and the NAND gate is connected to the traditional input buffer. A first input terminal connected to the output terminal, a second input terminal connected to the output terminal of the fifth inverter, and one output terminal; One input terminal connected to the output terminal of the gate and one output terminal connected to one receiver output terminal, wherein the first transmitter output terminal is bonded for connection outside the multi-chip module. If so, the path selection signal is set to low level to control the transmitter to send the transmitter input signal to the first transmitter output, and the second transmitter output is connected to the chip in the multichip module. If bonding is performed for chip-to-chip communication, the path select signal is set to a high level to control the transmitter so that the transmitter input signal is sent to the second transmitter output, and the first receiver input is Of the connection outside the multi-chip module The first receiver input signal is sent to the receiver output terminal if bonded for connection to the receiver, and the second receiver input signal is bonded for chip-to-chip communication within a multi-chip module if the second receiver input signal is bonded for chip-to-chip communication within the multi-chip module. A switchable input / output buffer for a multi-chip module, wherein a second receiver input signal is sent to the receiver output terminal. 8. A switchable input / output buffer for the multi-chip module according to claim 7, wherein:
A first pull low active register is used instead of the first pull high active register, a second pull low active register is used instead of the second pull high active register, and a second pull low active register is used instead of the first three state inverter. One transmission gate is used and the first
A transmission gate is connected to one input terminal connected to the output terminal of the third inverter, one inverting gate control input terminal connected to the output terminal of the first inverter, and to the output terminal of the second inverter. One non-inverting gate control input terminal and one output terminal connected to the first pull-low active register.
A transmission gate is used, the second transmission gate having one input connected to the output of the third inverter, and one inverting gate control input connected to the output of the second inverter;
It includes one non-inverting gate control input connected to the output of the first inverter and one output connected to the second pull-low active register, and the sixth inverter is omitted. The above NAN
A switchable input / output buffer for a multi-chip module having the above configuration, wherein the output terminal of the D gate is directly connected to the receiver output terminal.