JPH09270694A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce noise outputted to an external circuit by operating an internal circuit at a low power supply voltage so as to suppress a level of a noise component generated from an internal operation clock and providing an output to an output terminal via an output buffer. SOLUTION: A power supply voltage VDD1 is fed to an internal circuit and a power supply voltage VDD2 by means of a booster regulator 6 is fed to an output buffer 4. That is, the booster regulator 6 is provided to apply the power supply voltage VDD2 exclusively for the output buffer in addition to the power supply voltage VDD1 applied to the internal circuit to allow an internal CPU1, an output latch 2 and an oscillator 3 to be operated at a low power supply voltage and the output buffer 4 is operated by a usual operating voltage such as 5V by means of the booster regulator 6. A conventional circuit is enough for the booster regulator employed for the semiconductor device and has only to produce a voltage difference to reduce a noise component between the internal circuit and the output buffer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having improved noise characteristics.

[0002]

2. Description of the Related Art Referring to FIG. 6, which is a block diagram showing the structure of a conventional semiconductor device of this type, a CPU 1 for controlling an internal circuit and an output latch for temporarily holding a signal output from the CPU 1 to the outside are provided. 2, an oscillator 3 which is composed of a crystal oscillator or a ceramic oscillator and a capacitor, and which generates a reference frequency of a clock signal supplied to an internal circuit including the CPU 1, an output latch 2 and an external circuit, which serves as an interface. The signal output from the outside to the high level of the power supply potential VDD level or the ground potential VSS
Output buffer 4 that outputs low-level voltage value of level
And an output terminal 5 connected to this output buffer.

Here, the CPU 1, the output latch 2, and the oscillator 3
The output buffer 4 is supplied with the same power supply potential VDD and the same ground potential VSS. Therefore, the high-level signal voltage value output from the output terminal 5 is equal to the power supply potential VD.
A voltage level approximately equal to D is output.

Further, referring to FIG. 2 which compares the noise characteristics superimposed on the power supply line between the conventional example and the present invention, the output terminal 5
A harmonic component of noise generated by the CPU 1 or the oscillator 3 is superimposed on the signal output from the power supply potential VDD via the supply line 6.

[0005]

In the above-described conventional semiconductor device, the internal CPU 1, the output latch 2, the oscillator 3, and the output buffer 4 are connected by the supply line 6 of the same power supply potential VDD and the ground potential VSS. Therefore, the internal CPU1,
Alternatively, there is a drawback in that the harmonic component of noise generated in the oscillator 3 is output from the output terminal 5 to the external circuit through the supply line 6 of the power supply potential VDD which is commonly connected.

Therefore, the external circuit connected to the external terminal 5 may malfunction.

An object of the present invention is to solve the above-mentioned drawbacks, and to reduce the harmonic components of noise generated in an internal CPU or an oscillator output to an external circuit via an external terminal.

[0008]

The semiconductor device of the present invention is characterized by an internal circuit including at least an oscillator for generating a reference frequency and an internal CPU operating with an internal operation clock generated from the reference frequency, and the internal circuit. And an external circuit, which serves as an interface between the internal circuit and an external circuit, and outputs the output signal of the internal circuit to the outside as a high-level signal of the first power supply potential level or a low-level signal of the ground potential level, and the output buffer supplied only to this output buffer. A regulator that generates the other power supply potential from one power supply potential of the first power supply potential and the second power supply potential that is lower than the first power supply potential and is supplied to the internal circuit including the CPU. And suppressing the level of the noise component generated from the internal operation clock by operating the internal circuit at a low voltage. It is to output via the serial output buffer to an output terminal.

Further, the regulator means includes the second
It is a booster regulator that generates the first power supply potential from the power supply potential.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION First, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a main part of an embodiment of a semiconductor device of the present invention. Referring to FIG. 1, this semiconductor device includes a CPU 1 that controls an internal circuit, an output latch 2 that temporarily holds a signal 101 output from the CPU 1 to the outside, a crystal oscillator or a ceramic oscillator, and a capacitor. An oscillator 3 that generates a reference frequency of a clock signal that is configured and is supplied to an internal circuit including the CPU 1 and an output latch 2 and an external circuit that serve as an interface and output a signal 102 output from the output latch 2 to a power supply potential VDD2 level. An output buffer 4 that outputs a low-level voltage value of a high level or a ground potential VSS level, a booster regulator 6 that generates a power supply potential VDD2 supplied to this output buffer 4 from an internal power supply potential VDD1, and an output buffer are connected. And an output terminal 5 that has a Source potential VDD1 is supplied, and a low voltage operation.

That is, the difference from the conventional example is that the power supply potential VDD1 supplied to the internal circuit and the power supply potential VDD2 supplied to the output buffer 4 are divided and supplied by the boost regulator 6.

As can be understood from the above-mentioned configuration, by providing the booster regulator 6 for supplying the power supply potential VDD2 dedicated to the output buffer 4 in addition to the power supply potential VDD1 supplied to the internal circuit, the internal CPU 1 and the output The latch 2 and the oscillator 3 are operated at a low voltage, and the output buffer 4 is operated at a normal operation voltage, for example, 5V through the boost regulator 6.

The boosting regulator 6 applied here may be a generally used circuit, as long as it can generate a potential difference enough to reduce a noise component between the internal circuit and the output buffer. For example, referring to FIG. 3 showing an example of a booster circuit of a known technique, the booster circuit includes a high-speed level fluctuation compensating circuit 31 and a low-speed level fluctuation compensating circuit 3.
2 circuits of 2 are connected in parallel.
The boosted VDH is output from the parallel connection point C of the two circuits. Low speed level compensation circuit 32 when deactivated during standby
Only works. The level of the boosted power supply potential VDH is secured by the pulse constantly applied from the ring oscillator OSC.

When active, the pump circuits in the high speed level fluctuation compensating circuit 31 are driven by the clocks φ1, φ2 and φH. Therefore, the charge is injected into the load every cycle to compensate the charge consumed in the load.

By supplying the above-mentioned two systems of power source potential,
Operating the internal circuit at low voltage means that the internal CP
The harmonic components of the noise component generated in U1, the output latch 2, the oscillator 3, etc. also have a low output level value, and the level difference relative to the output level value output from the output buffer 4 also becomes large.

Referring again to FIG. 2, the horizontal axis shows the reference frequency f in MHz, the vertical axis shows the amount of noise generated in the internal circuit in decibel dB, and the noise characteristic in the conventional example is shown by the curve 7. The curve 8 shows the noise characteristic in the present embodiment.

From this figure, it can be seen that the noise level of the curve 8 in the present embodiment is reduced as compared with the curve 7 of the conventional example.

Referring to FIG. 4 which is a block diagram showing the main part of the modification of the first embodiment, this semiconductor device
A CPU 1 for controlling an internal circuit, an output latch 2 for temporarily holding a signal output from the CPU 1 to the outside, a clock signal composed of a crystal oscillator or a ceramic oscillator and a capacitor and supplied to an internal circuit including the CPU 1. , An OR3 for ORing the output signal 106 of the output of the peripheral function 9 and the output signal 105 of the output latch 2, and a peripheral function 9 for counting the operation time of the CPU1. And an output buffer 4 for outputting the signal output from the OR 10 as an interface between the output signal 107 of FIG. 1 and an external circuit to a high level of the power supply potential VDD2 level or the low level of the ground potential VSS level, and the output buffer 4 Power supply potential VDD2 supplied to the internal power supply potential VDD1 6 and an output terminal 5 connected to the output buffer 4, each component other than the output buffer 4 is supplied with the low power supply potential VDD1, and these components operate at a low voltage. There is.

In this circuit, the function of the output terminal 5b is different from that of the first embodiment. That is, while the output terminal 5a of the first embodiment has a normal output buffer function, the output terminal 5b is used when any one of the peripheral functions 9 is selected and output to the outside. One terminal is shared as an output terminal for a plurality of output signals to reduce the increase in the number of terminals.

For example, while the output signal 105 of the output latch 2 is set to the low level, the output signal 106 of the peripheral function is output.
Is output to the output terminal via the output buffer 4, and the output of the peripheral function 9 is set to the low level.
The output signal 105 of 1 is similarly output to the output end 5b via the output buffer 4.

Also in this example, since the internal CPU 1, the output latch 2, the oscillator 3, and the peripheral function 9 can be operated at a low voltage, they are output from the output terminal 5b as in the first embodiment. The noise component generated is reduced as shown by the curve 8 in FIG.

The noise component that can be reduced in the above-described first embodiment and its modification is the power supply potential VDD1.
Referring to FIG. 4, which shows a waveform diagram of an example of the operation clock of the CPU 1 which is a transmission noise superimposed on the supply line of the CPU 1 and causes the noise component, CP
The waveform 11 of the operation lock of U1 is the voltage value V, the horizontal axis is time t, the vertical axis is the time function g (t), and the width of the square wave is T,
Fourier transform of this square wave gives: g (t) = [2V (cost− (1/3) cos3t +
(1/5) cos5t- (1/7) cos7t + ...
...)] / T.

Since this Fourier transform value is generally proportional to the transmission noise, it is proportional to the voltage V of the waveform 11 in the above equation.

If, for example, the voltage value is halved as compared with the conventional case, the noise level will be reduced to ½ of the conventional case.

[0025]

As described above, the semiconductor device of the present invention has an internal circuit including at least an oscillator for generating a reference frequency and an internal CPU operating with an internal operation clock generated from the reference frequency, and this internal circuit. And an output buffer that serves as an interface between the external circuit and outputs the output signal of the internal circuit to the outside as a high-level signal of the first power supply potential level or a low-level signal of the ground potential level, and a first buffer supplied only to this output buffer. Of the power supply potential and the second power supply potential lower than the first power supply potential and supplied to the internal circuit including the CPU, the regulator means for generating the other power supply potential from the one power supply potential. The internal circuit is operated at a low voltage to suppress the level of the noise component generated from the internal operation clock and pass through the output buffer. Since the output to the output terminal Te, can reduce the noise output to an external circuit, which contributes to the improvement of the reliability of the semiconductor device.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a characteristic diagram for comparing noise component reduction characteristics of the present invention and a conventional example.

FIG. 3 is a block diagram showing an example of a booster circuit.

FIG. 4 is a block diagram showing a modification of the first embodiment of the present invention.

FIG. 5 is an operation clock waveform diagram of the CPU 1.

FIG. 6 is a block diagram of an example of a conventional semiconductor device.

[Explanation of symbols]

 1 Internal CPU 2 Output Latch 3 Oscillator 4 Output Buffer 5 Output Terminal 6 Boost Regulator (Buck Regulator) 9 Peripheral Circuit 10 OR 21 Current Mirror Differential Amplifier 22 pMOS Transistor 31 High Speed Level Fluctuation Compensation Circuit 32 Low Speed Level Fluctuation Compensation

Claims (2)

[Claims] 1. An internal circuit including at least an oscillator that generates a reference frequency and an internal CPU that operates with an internal operation clock generated from the reference frequency, and an interface between the internal circuit and an external circuit, and an output of the internal circuit. An output buffer which outputs a signal of a high level of the first power supply potential level or a low level signal of the ground potential level to the outside, the first power supply potential supplied only to this output buffer and the first power supply potential And a regulator means for generating the other power supply potential from one power supply potential of the second power supply potential supplied to the internal circuit including the CPU, and operating the internal circuit at a low voltage. By so doing, the level of the noise component generated from the internal operation clock can be suppressed and output to the output terminal via the output buffer. A semiconductor device characterized by the following. 2. The semiconductor device according to claim 1, wherein the regulator means is a booster regulator that generates the first power supply potential from the second power supply potential.